JPS58197848A - Manufacture of multi-layer wiring structure - Google Patents

Abstract

PURPOSE:To prevent short-circuit disconnections in multi-layer wiring by a method wherein silicon dioxide (PSG) film containing phosphorus, a titanium chelate compound heat-treated substance thin film, a thermosetting resin film, and further thereon a composite film with the titanium chelate compound heat-treated substance thin film are formed, as the intermediate insulation film between the first layer conductor layer and the second layer conductor layer. CONSTITUTION:A Si oxide film 12 is formed on a Si semiconductor substrate 11, and the first layer conductor layer 13 having a fixed wiring pattern is formed by a photo lithography method, using a metal wherein 2% of Si is contained to Al as the first conductor later. Next, the PSG 14 is deposited in thickness approx. 9,000Angstrom , further theron titanium chelate compound is coated and heat- treated at 300Angstrom in the air, and accordingly a Ti oxide film 15 is formed. Then, a hole 14a is opened on this Ti oxide film 15 and the PSG 14, then polyimide precursor solution is coated on the first layer conductor layer 13 and the Ti oxide film 15 through this aperture 14a, and a polyimide film 16 is obtained by heating in the air or nitrogen. Thtanium chelate compound is coated, thereafter heated in the air, and thus a titanic acid compound 17 is formed on the polyimide film 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring structure that is applied to a semiconductor integrated circuit and has a wiring structure of 21W1 or more.

A conventional example of the manufacturing method of conductor wiring, typically made of metal, in a conventional semiconductor integrated circuit is shown in Fig. 1-) to Fig. 1->
I will explain from k. 11-) to 1(-) are a silicon semiconductor substrate in which elements such as diodes and transistors are formed, and the elements are placed at a predetermined position k on this silicon semiconductor substrate 1 as a matrix. A silicon dioxide film 2 having a window for connection is formed.

For example, the following types of silicon semiconductor substrates 1 in which element regions such as transistors, diodes, and resistors are formed are widely known.

That is, it consists of a donor (N) type single crystal layer epitaxially grown on an N donor type single crystal silicon substrate and circuit components such as transistors, diodes, and resistors formed in the epitaxially grown long chest.

These circuit components include resistors and diodes formed by diffusion of acceptor (P) type impurities, N type emitter regions,
A transistor having a P-type space region, a collector region, etc.

Furthermore, the above-mentioned 1-way component and the IJK above the Evita Kinyar layer
This is achieved using a well-known method using an inert film such as silicon dioxide or silicon nitride. The I membrane is eclipsed,
A diagonal opening is provided in this silicon dioxide film or silicon nitride film to connect to the desired circuit element portion.

A conductive metal is deposited on the entire surface of the silicon dioxide film 2 by vapor deposition, as shown in FIG. Unnecessary portions of the metal film are removed by photolithography to obtain a desired wiring pattern 3.

Furthermore, a polyimide precursor solution is coated and heated on the semiconductor substrate to form a polyimide film 4 as shown in FIG. 1g1 figure (d)).

Next, a metal film is deposited again, and the second layer metal wiring 5 is provided. These methods are described in detail in a series of publications, typified by Japanese Patent Publication No. 51-31185.

Application of the polyimide film disclosed in Japanese Patent Publication No. 11851-31185 to multilayer interconnection is an excellent method for flattening the level difference of an integrated circuit board, but it has the following characteristics.

(1)/Liimide film may contain mobile ions.

(2) Polyimide family members are hygroscopic.

(3) The J-type film has poor adhesion to the metal film.

The characteristics of these I-liimide conversions are such that the second layer metal wiring (mostly aluminum) reacts with the oxidation ions, often corroding the metal wiring, which poses a very serious problem in terms of reliability.

Furthermore, it has been found that the adhesion between the polyimide group 4 and the m2 layer gold metal @IIk5 is not sufficient, and the second layer metal film 11/ii5 may peel off from the polyimide film 4.

Furthermore, it is extremely difficult to form the opening 4a in the polyimide film 4, and as the size of the tree 7 of the opening 4a becomes finer, it becomes even more difficult. It has serious drawbacks that contribute to a decrease in yield.

This invention was made in order to eliminate the above-mentioned conventional drawbacks, and it is possible to prevent short circuits and disconnections in multilayer wiring, to flatten board steps, and to form a patterned binder of hardening-resistant resin, such as polyimide resin. It is an object of the present invention to provide a method for manufacturing a multilayer wiring structure that is simple.

Examples of the method for manufacturing a multilayer wiring structure according to the present invention will be described below.
First, an overview of this invention will be described.

In this invention, a conventionally used phosphorus-containing silicon dioxide film (hereinafter referred to as PSG) is placed as the bottom layer, and a titanium chelated metal compound (hereinafter referred to as a chelate compound) is placed on top of the bottom layer to strengthen the adhesion with polyimide 1. A thin film of a heat-treated material (which is formed by bonding a metal ion with an organic substance having a donor group to form a cyclic structure) is formed, a thermosetting resin typified by polyimide is formed on the thin film, and a thermosetting resin, typically polyimide, is formed on the thin film. The intermediate insulating film is characterized by forming a thin film of a heat-treated titanium chelate compound, and the lowermost PSG film is characterized by making mobile ions inactive and preventing M corrosion. The compound strengthens the adhesion between the thermosetting resin and PSG, and further strengthens the adhesion between the thermosetting resin and At
C has the role of strengthening the adhesion with the thermosetting resin, and also has the role of flattening the PSG film surface and preventing the formation of pinholes due to KAA hillocks, etc. This method significantly improves the shortcomings of the conventional method.

Next, embodiments of the present invention will be described based on the drawings. 1g2-) to FIG. 2 (JI) are diagrams for explaining the process of one embodiment. As shown in FIG. 2-), a silicon oxide film 12 is formed on a silicon semiconductor substrate 11, kL K 2 % as the first conductor layer on the upper surface.
A first oil conductor layer 13 having a predetermined wiring pattern is formed by a well-known photolithography method using a metal containing 81 as shown in FIG.

Next, as shown in FIG. 2-), % PSGI 4 was deposited to a thickness of approximately 9000, and a titanium chelate compound was further applied thereon. A titanium oxide film 15 is formed by thermal geography at 300° C. in air.

Next, hole 14m for connection with the first layer conductor 13
into this titanium oxide M15 and PS G14 (
Fig. 2 o)) A 4-limide precursor solution is applied on the first conductor layer 13 and the titanium oxide film 15 through this opening 14m, and the solution is applied in air or nitrogen at a temperature of 100 to 400°C. Heat with inert gas) to a thickness of approximately 100OOX.
/IJ imide film 16 is obtained.

Next, as shown in FIG. 2(e)K, a titanium chelate compound is applied, and then heated in air at 300C for 30 minutes to form a titanium acid compound 17 on the polyimide film 16 to a thickness of about 100 to 200X.

Thereafter, a hole is made in the titanium oxide film 17 as shown in FIG.
．． Polyimide film 16 KN mouth.

Thereafter, as shown in FIG. 2(b)K, aluminum is deposited as a %JI2 conductor layer 18 on the opened portion and the titanium oxide film 17, and predetermined arm turns are formed by photolithography.

As explained above, in the first embodiment, P is used as the intermediate insulating film between the gIJl* conductor layer 13 and the second conductor layer 18.
SGml4, titanium chelate compound heat-treated thin film,
That is, titanium oxide lX15 and polyimide film 16
Furthermore, a thin film of heat-treated titanium chelate compound (
Since a composite film with a titanium oxide film 17) is used, each individual film has its own advantages, thereby forming an excellent intermediate insulating film.

In other words, the heat-treated titanium chelate compound thin film 15, 17 strengthens the adhesion of the film, the PSGii 14 immobilizes mobile ions, and the polyimide film 16 prevents pinholes caused by kA hillocks and flattens the substrate level. This has the advantage that a multilayer wiring structure can be formed without causing disconnection in the multilayer wiring of an LSI.

In addition, an advantage in forming fine #/4 turns is that PS (4) can be etched with high precision because the openings are formed before the formation of the imide film 16. The opening is extremely loose.
It has the advantage of being able to form 9 turns, which simplifies the formation of polyimide films.

2 m yt, silicone matrix &1
1 uses a ceramic substrate for LSI.

The following steps were performed as described in Example 1. As a result, it has been confirmed that monolithic LSI, SIQ) multi-distribution kO, and hybrid LSI wiring boards are also effective without any problems.

As described above, according to the method for manufacturing a multilayer wiring structure of the present invention, the intermediate gap between the #11 conductor layer and the second conductor layer is
h! In addition, a composite film is formed with %PSG & titanium chelate compound heat-treated lumber thin film, thermosetting resin film, and on top of that a titanium chelate compound heat-treated thin film, so short circuits can be prevented in multi-level wiring. Moreover, it is possible to form a gentle pattern in the openings of the thermosetting resin layer, to flatten the steps of the substrate, and to prevent disconnection of multilayer wiring, which can be used for LSI.

[Brief explanation of the drawing]

FIGS. 1(a) to 1-) are process explanatory diagrams of a conventional method for manufacturing a multilayer wiring structure, and FIGS. FIG. DESCRIPTION OF SYMBOLS 11...Silicon substrate, 12...Silicon dioxide layer, 13...First oil conductor layer, 14...PSGJ[,1
5, 17...Titanium oxide film, 16...Polyimide film, 18"...Second conductor layer. Patent applicant Oki Electric Industry Co., Ltd. 1l1 2 O 211 Procedural amendment September-3, 1988 Mr. Kazuo Chikusugi, Commissioner of the Patent Office, 1. Indication of the case. 1927 Patent Application No. 80167 2. Title of the invention: Method for manufacturing a multilayer wiring structure 3. Relationship with the amended person case. Patent Applicant (02G) ) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order Showa year, month, day (#1
6. Subject of amendment @ Detailed section of the invention in the specification and part of the drawings 7. Contents of amendment (1) As shown in the attached sheet, Figure 11M1 (at, (d)) is fixed, No. 1 figure

Claims (1)

[Claims] a step of forming a first Nk conductor layer having predetermined wiring no-turns on a semiconductor substrate via an insulating film; and a step of forming a silicon dioxide film containing phosphorus and a first titanium chelate on the first conductor layer. A step of forming an intermediate insulating film by sequentially forming a thin film of heat-treated heat-treated material, a thermosetting resin film, and a second thin film of titanium chelated heat-treated material; and after forming the intermediate insulating film, forming the first layer. A method for manufacturing a multilayer wiring structure comprising the step of forming a second conductive layer on the intermediate insulating film so as to be connectable to the conductive layer.