JPS58197566A - Control system for program loading - Google Patents

Control system for program loading

Info

Publication number
JPS58197566A
JPS58197566A JP57079770A JP7977082A JPS58197566A JP S58197566 A JPS58197566 A JP S58197566A JP 57079770 A JP57079770 A JP 57079770A JP 7977082 A JP7977082 A JP 7977082A JP S58197566 A JPS58197566 A JP S58197566A
Authority
JP
Japan
Prior art keywords
program
svp
memory
host
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57079770A
Other languages
Japanese (ja)
Other versions
JPS6336547B2 (en
Inventor
Hiroki Shimada
嶋田　浩己
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57079770A priority Critical patent/JPS58197566A/en
Publication of JPS58197566A publication Critical patent/JPS58197566A/en
Publication of JPS6336547B2 publication Critical patent/JPS6336547B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

PURPOSE:To increase a processing speed, by loading an auxiliary test program from a host memory to an SVP memory directly. CONSTITUTION:In the IPL operation of a service processor (SVP), a dummy program 32 in an SVP file 31 is loaded to the SVP memory. This operation is carried out by an SVP monitor 33. When a testing system use the auxiliary test program 39, the execution part of the auxiliary test program 39 is loaded from a host-side memory onto the execution part A21 of the dummy program in the SVP memory.

Description

【発明の詳細な説明】 （１）発明の技術小野 本発明はホストとサービスプロセッサからなるシステム
におけるプログラムのローディング制御方式に係り、特
にプログラム全ホスト側のメ七りから直接サービスプロ
セッサのメモリにローディングする制御方式に−Ｔる。DETAILED DESCRIPTION OF THE INVENTION (1) Technology of the Invention OnoThe present invention relates to a program loading control method in a system consisting of a host and a service processor. -T to the control method.

（２）従来挟術と問題点 従来、ホスト（本体系）とサービスプロセッサ（ＳＶｋ
’）からなるシステムにンける、ｂＶＰｋ利用した本体
系の試験方式においては、テスト条件の設定、変更のた
めに、本体系からの制御＃ｖ′こより、ｓｖｐｔｇｇで
ノログラムｋｃより行なっＣいた、この場合ホスト圃メ
仁りの中Ｖこ・おる試験プログラムの中にＳＶＰ上ご動
作ｊるプログラム（試−補助プログラム）がりる場合、
該試験補助プログラムｔ−４ＳＶＰノアイｌし１つ中Ｖ
Ｃ格納し、Ｃｄ、ＳＶｋ’モニタの制御のもとりこＳＶ
Ｐのメモリにロードして実行すりため、ｉ１＃間が＃り
遇ざるという欠点が必った０ （３）発明の目的 本発明に前記欠截と解消して、速−？かにホストのメモ
リから直瀬Ｓ　Ｖ　Ｐメ・ｄリヘローディングする方式
′ｆｔ長供ｒる０と（目的とｒる。(2) Conventional techniques and problems Conventionally, host (main system) and service processor (SVk)
In the test method of the main system using bVPk in the system consisting of If there is a program (test-auxiliary program) that operates on SVP in the test program of the host farm,
The test auxiliary program t-4SVP Noah I and one V
SV that stores C and controls the Cd and SVk' monitors.
Since the process is loaded into the memory of P and executed, there is a disadvantage that there is no interaction between i1 and #. How to load Naose SVP mail from the host's memory?

（４）ｉｋ明の構成 該目的は５ｖｐ（サービスプロセラサラ上で動作するプ
ログラムがホストｌ１ｌ（本体系ンに６るシステムに２
いて、ａｓｖｐｓのファイルにダミープログラムを置き
、該ダミーグーグラムをＳＶＰで動作するｐ　ｍｔｌ記
プログラムが実行される前に、ＳＶＰメモリ上にローデ
ィングｒる手段−と、該Ｓ　’ｌ／Ｐ　、ｏｍ御の麺に
前記ＢＶＰ二で動作するグログツムをホスト−メモリか
らＳ’ｖ’Ｐ−メモリに直−ローディングするす段ｔ−
設けたことｔ″特愼する／Ｌ＋グラムの＋−Ｊ−ｆイン
グ制御方式ＶＣより達成６ルる。(4) Configuration of ik Ming The purpose of this is to install a program running on a 5vp (service processor) into a system that runs on a host l1l (the main body is 6).
means to place a dummy program in the asvps file, load the dummy program into the SVP memory before the program running in SVP is executed, and the S'l/P,om The next step is to directly load the Glogzum that operates on the BVP2 from the host memory to the S'v'P memory.
This is achieved by the VC control system of t''/L+gram +-J-f.

（５）発明の実ｍ列 以下本発＃４を図１ｉｆｔ用い°Ｃ詳細に説明する。第
１図りよ本発明の一実Ｓ例を示−ｒｓｖｐグログ之ムの
実行形式の４造を示す図である。(5) The actual m-column of the present invention #4 will be explained in detail using FIG. FIG. 1 is a diagram showing an example of the present invention; FIG.

図に２いて、１１＃″ｉ制御チーグル、１２は実行部で
ある。第２図は本発明の一実ＩＭ−を示すダミーグログ
ラムと試験補助プログラムの関係と示す図で６るり 図にＰい−（，２１は実行部Ａ、２２は実行部Ｂである
。第３図は本発明の一実施例を示す試験補助プログラム
のローディング過程を示す図である。In Figure 2, 11 is a control team, and 12 is an execution unit. , 21 is an execution unit A, and 22 is an execution unit B. FIG. 3 is a diagram showing a loading process of a test assistant program according to an embodiment of the present invention.

図にア・イテ、３１ｉｔＳＶＰ７ｙイに、３２はダミー
／ログラム、３３は８ＶＰモニ・メ、３４ｄｉ（験１１
１１１１１４Ｉプログラム、３５は制御テーブル部、３
６は実行部Ｃ１３７はホストメモリ、３８は試験プログ
ラム、３９は試験補助プログラムである。The figure shows A, 31itSVP7y, 32 dummy/program, 33 8VP monitor, 34di (Experiment 11
111114I program, 35 is control table section, 3
6 is an execution unit C137 which is a host memory, 38 is a test program, and 39 is a test auxiliary program.

ＳＶＰプログ２ムの実行形式、・ま＋ｔｉ制御テーブル
１１と央ｆＴ都」２から構成される。ここで制御テーブ
ル１．１は池のＳＶＰプログラムとのインターフェイス
部であり実行Ｍｌｌの内＃により異なりＳＶＰモニｐ３
３ＶＣエリ設定される。またダミー／ログラム３２と試
験グロノシム３８内のＳＶＰプログラムの＊［１１ｉ１
鄭１１の領域の大きさを等しくｒる。The execution format of the SVP program 2 consists of a control table 11 and a control table 2. Here, the control table 1.1 is the interface part with the Ike's SVP program, and differs depending on the number of execution Mlls.
3VC Eli is set. Also, the dummy/program 32 and the SVP program in the test gronosim 38 are
Let the size of the area of Zheng 11 be equal.

＠３ｇＫ−おいて、試験補助プログラムのローディング
につ＾てａｑすると？ Ｑ　　ＢＶＰのＩＰＬ時に、５ＶＰｙフイル３１上のダ
ミープａグラム３２ｔ−８ＶＰメモリにロードする０こ
の動作はｓＶＰ七ニタ３３が行プ。@3gK-, what do you do when loading the test assistance program? Q: Load the dummy program 32t-8VP memory on the 5VPy file 31 during IPL of the BVP. This operation is performed by the sVP seventh monitor 33.

この頗、制御テーブル廊３５は＋ｉ［実にロードする必
要かあるが実行部３６は、領域が確保してあれはよい。In this case, the control table 35 actually needs to be loaded, but the execution unit 36 is fine as long as the area is secured.

■　試験システムが、試験補助プａグツム３９ヲに用時
に、ＳｖＰメモリ上のダミープログラムの実行ｄ５Ａ２
１のヒにホスト圃メモリより試験補助プログラム３９の
実行−をロードする。■ When the test system uses the test assistant program 39, the dummy program on the SvP memory is executed d5A2.
1. Load the execution of the test auxiliary program 39 from the host field memory.

以上により、５ｖｒｙ）ｒイル３１よりローディングさ
れ／−場合と同しように、ｌｌ１１御テ一ブル部３５は
ＳＶ’ＰのＩＰＬ、時に作成され、かつ実行部は試験補
助プロゲラ−がホスト圃より直接ロードさｔＬる０ こ′」場合、試滅ノ゛ログツム３８運用甲のローディン
グは前記シのム虐のみとなる。As a result of the above, the ll11 control table part 35 is created during the IPL of SV'P, and the execution part is directly loaded from the host field by the test assistant programmer. In this case, the loading of the Extinction Log Tsum 38 Operation A will be limited to the system described above.

（６）発明の詳細 な説明Ｌ７たように本発明にこれば、ホストメモリから
ＳｖＰメモリに直接試験補助プログラムがローディング
され、処理速度が向上する効果かめる。(6) Detailed Description of the Invention As described in L7, according to the present invention, the test auxiliary program is directly loaded from the host memory to the SvP memory, and the processing speed is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一喪厖例を示すＳＶＰグログラムの実
行形式の構造を示す図である。 第２図は本発明の一実施例を示すダミーグログラムと試
ｆｊｉｉ４助グロダラムの１４床を示を図である。 ＃Ｉ３図は本発明の一実施列を示を試験補助プロゲラＡ
　Ｊ）　ＬＪ　−７’インク４４１Ｍｋ示ｒ図である。 記号の説明、３１はＳＶＰファイル、３２はダミーノロ
ゲノム、３３はＳＶＰ七ニメ、３４；ｊ＃Ｃ繊制呻プμ
ダラム、３５に劇イ叶ｊ−／ル部、３６は夾ｆＴ部Ｃ，
ｄ’／、ｉ・ｔ（ストメモリ、３８は＃Ｃ験グログｊム
、３９ｕ賦ｍ補助ノロノラム。FIG. 1 is a diagram showing the structure of an execution format of an SVP program illustrating an example of the present invention. FIG. 2 is a diagram showing a dummy grogram and 14 beds of a trial FJII 4-assist grodrum showing an embodiment of the present invention. #I3 Figure shows one implementation row of the present invention.
J) It is a diagram showing LJ-7' ink 441Mk. Explanation of symbols, 31 is SVP file, 32 is dummy genome, 33 is SVP seven animation, 34;
Durham, 35th is the play I Kano J-/Le part, 36 is the 5th part C,
d'/, i・t (stemory, 38 is #C test globulom, 39u m supplementary noronorum.

Claims (1)

【特許請求の範囲】[Claims] ５ＶＰ（サービスゾロセツナ」上ご動作ｊ−るノログラ
ムがホスト＠（本本糸ンにあるシステムにおいて、該Ｓ
Ｖｉ’＊リファイルにダミープログラムｉｌｌき、該ダ
ミープログラムｆＳＶＰで動作するｔ前記プログラムが
兼行される前に、ＳＶ’Ｐメモリ上にローディングｒる
手段と、該ＳＶＰの制御のｊＫｌ、前記ＳＶＰ上で動作
するプログラムをホスト側メモリから８ＶＰ側メモリに
直ｗｌ、ローディングする手′ＩＲｔ設けたことｔ％値
とするノログラムのローディング制御方式０5VP (Service Zoro Setsuna) The operating program is the host
A dummy program is written in the Vi'* refile, and a means for loading the dummy program fSVP into the SV'P memory before the program is concurrently executed, a control jKl for the SVP, and a means for loading the dummy program fSVP on the SVP. Directly loading a program running on the host side from the host side memory to the 8VP side memory.
JP57079770A 1982-05-12 1982-05-12 Control system for program loading Granted JPS58197566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57079770A JPS58197566A (en) 1982-05-12 1982-05-12 Control system for program loading

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57079770A JPS58197566A (en) 1982-05-12 1982-05-12 Control system for program loading

Publications (2)

Publication Number Publication Date
JPS58197566A true JPS58197566A (en) 1983-11-17
JPS6336547B2 JPS6336547B2 (en) 1988-07-20

Family

ID=13699436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57079770A Granted JPS58197566A (en) 1982-05-12 1982-05-12 Control system for program loading

Country Status (1)

Country Link
JP (1) JPS58197566A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114136A (en) * 1978-02-27 1979-09-06 Hitachi Ltd Microprogram loading system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114136A (en) * 1978-02-27 1979-09-06 Hitachi Ltd Microprogram loading system

Also Published As

Publication number Publication date
JPS6336547B2 (en) 1988-07-20

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