JPS58195268A - Electronic register - Google Patents

Abstract

PURPOSE:To correct a program without exchanging an ROM by assigning one bit of the 2nd storing means to plural types of the 1st storing means. CONSTITUTION:A mask ROM2 fixedly storing and holding a program processing various transactions, a program for setting up a correction program or the like and an RAM3 storing the existence of change of the programs in accordance with each address position of the ROM2 are connected to a CPU1 through a data bus 13 and an address bus 14. In addition, an RAM5 storing the address of the correction program, an RAM4 storing the correction program and an RAM6 storing respective data registered and processed are connected to the CPU1. Consequently, the program fixed and stored in the ROM2 can be easily corrected by assigning one bit of the RAM3 to the plural bytes of the ROM2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic equipment (hereinafter collectively referred to as electronic registers and abbreviated as ECR) such as electronic cash registers for registering and processing various transaction information or teller's machines used in banking operations, and particularly relates to ECR that is devised so that when it is necessary to change or modify a part of a program such as various transaction processing programs written in a fixed memory device, the program can be easily and easily changed or modified. It is.

Generally, when writing various ECR transaction processing programs into a fixed memory device, an inexpensive mask ROM (read only memory) is used. However, this R
By writing the -1 processing program into the OM, the processing program is fixed. However, after writing the processing program to the mask ROM in this way,
It often happens that you want to change or modify a part of the processing program, and in that case, since the program is fixedly stored, it is necessary to replace it with a mass ROM in which a new program has been written. Making changes or corrections is not only very expensive, but also requires a great deal of time and effort, making it difficult to make such changes or corrections.

The present invention was made with the purpose of providing an ECR that eliminates the above-mentioned problems, and to achieve this purpose, an ECR implementing the present invention is a processing program for processing ECR transaction registration or a registered Check the data
a first storage means (mask ROM) that permanently stores programs such as a processing program for payment processing;
a second storage means having an address associated with the address of the storage means and storing information indicating whether or not the processing program has been changed corresponding to each address position; A third storage means for storing a program change address and a storage address of the modification program; and a fourth storage means for storing a modification program having a different address from that of the first storage means. and is configured to allocate one bit of the second storage means to a plurality of bytes of the first storage means.With such a configuration, the present invention can be applied to the mask ROM. An ECR is provided in which a program can be modified without replacing the program, and the storage capacity of each of the storage means necessary for modifying the program is minimized.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an ECR embodying the present invention.

In FIG. 1, there is a lj central processing unit (CPU), and the CPU has a first central processing unit (CPU) that permanently stores various transaction processing programs, correction program setting programs, etc.
storage means (mask ROM) 2 and 'i.

A second storage means (11) which has an address related to the address of the mask ROM 2 and stores the existence or non-existence of a program change corresponding to each of the AT and S positions of the ROM 2.
Program change for RAM) 8 and mask ROM 2
A third storage means (RA
M) 5 and a fourth storage means (RAM
) 4, a storage means (RAM) 6 for storing various registered data, and an input means 7 for inputting various transaction information, turning on/off the power of the device, and selecting mode information such as registration, inspection, payment, etc. , a display means 8 for displaying input/output information, etc., a printing means 9 for similarly printing this input/output information, etc. on a receipt, etc., a drawer IO for storing cash etc. generated in each transaction registration, etc., and various data or programs. A magnetic tape device 11 and the like for reading data are connected via a data bus 13 and an address bus 14.

A decoder 15 is configured to decode address information on the address bus 14 and select each of the above components.

Reference numeral 12 is composed of a flip-flop, which is set by a "1" signal output from RAM 3, and interrupts the CPU by the set output of flip-flop 12, and responds to the final step of the modification program stored in RAM 4. 16 is a key interface (Key'/
F), 17 is a printer interface (PI/F),
18 is a display interface (DI/F), and 19 is an input/output interface (I101/F).

Further, the RAM 4 and RAM 5 are backed up by a backup battery power supply 20, and a part of the RAM 6 is also backed up by a backup battery power supply 13.

Note that the RO
Addressing of M2 and RAM 3 is accomplished. Furthermore, each of the storage means 3 to 6 is configured as a C-MOS random access memory (RAM).

Reference numeral 21 denotes a power supply circuit, and the power supply circuit 21 is activated in response to the ON operation (operation of selecting a desired mode from the OFF position) of the mode selection key M provided in the input means 7.
It is configured to supply power to each part of the device and to input a power-on signal (not shown) to the CPU 1.

Further, an initial program [FIG. 8(b)] which is addressed in response to power-on is fixedly stored in the mask ROM 2 in advance.

Next, the operation of changing the program of the ECR shown in FIG. 1 will be explained.

When it is necessary to partially change the fixed processing program written in the mask ROM 2, which is the first storage means, first the RAM 4 is used to store the modified program corresponding to the address position of the mask ROM 2 that requires the change. Set the memory address location to QAM5, the modification program to RAM4,
Each of them is loaded from the magnetic tape device 11, and each memory can be held and rewritten.

Specifically, the fourth storage means (RAM) 4 has the memory shown in FIG.
), the data in the mask ROM 2, which is the first storage means, is sequentially written after a predetermined address XXXA in the RAM 4, and in the final step of the modification program, a jump is made to the return address to the mask ROM 2. Instructions are written. Furthermore, if it is necessary to change the program at address B in the mask ROM 2, the modified program is written in the RAM 4 starting from address XXXB. Further, in the third storage means (RAM) 5, as shown in FIG. 2(b), a flag l'' is set in the first address area a, and the modification program at which address in the mask ROM 2 is stored at which address in the RAM 4. A table indicating what is stored is stored.

In this embodiment, address A of mask ROM2,
This shows a case where there is a program change in H.
1: Like this, RAM4.5. , write the modification position 1° of the program fixed in the mask ROM 2 from the magnetic tape device 11 and the modification program, and set the modification program.
Complete 1. At this time, a flag indicating that there is a change in the program of the mask ROM 2 of this device is written in the area aKFi of the RAM 5 as described above.

In this state, the operator operates the mode selection key M of the input means 7 to select a predetermined operation mode and starts the power supply circuit 21 in order to perform the registration process. By starting the power supply circuit 21, power is supplied to each part of the device and a power-on signal is input to the CPUI.

In response to this power-on, the CPU 1 specifies the initial operation program (IP) stored in the mask ROM 2, and executes this initial operation program (IP).

First, the execution operation of the initial operation program shown in FIG. 3(a), which was previously proposed by the applicant, will be explained.

First, the CPU detects the power-on state (step n
1) First, it is determined whether or not a flag is set in area a of RAM 5. Step n2). If the flag is set, the process moves to step n3 and sets flag 1" in the corresponding area of RAM 3. (Step n4). In this embodiment, 7 lag l" is set for A and B. 0 When this setting operation is completed, the CPU selects the mode selected by the mode selection key MK to execute the process of the selected mode. The mode information is read (step n6), the selected mode is determined (step n7), and a program corresponding to a predetermined operation mode stored in the mask ROM 2 is selected and designated.

On the other hand, if the flag is not set in area a of RAM5, the process moves from step n2 to step n6, and the CPU
I immediately selects the corresponding program in the mask ROM 2 to execute the process of the selected mode.

By executing such an initial operation program (IP), information is set in the RAM 8, which is the second storage means, based on the information stored in the RAM 5, which is the third storage means, in connection with turning on the power of the device. and the second storage means (RAMe
As shown in FIG. 2(c), a flag is stored at the same address as the program change address in the mask ROM 2, indicating that the program stored at that address in the ROM 2 requires a change.

By the way, according to the method previously proposed by the applicant, an area of 1 bit is allocated to 1 byte of mask ROM 2 for flag setting in RAM 3, so if the program capacity of mask ROM 2 increases, , this R
The capacity of AM3 is also required to correspond to the number of bytes of the program. This causes inconveniences such as increased costs.

Therefore, in the present invention, the capacity of RAM 3 is reduced by allocating l pits of RAM 3 to a plurality of bytes of mask ROM 2, as shown in FIG. 2(d).

Specifically, the initial operation program shown in FIG. 3(b) is executed. That is, after the CPU detects the power-on state (step n11), it first determines whether or not a flag is set in area a of the RAM 5 (step n1).
2 If the flag is set, step n13
, and reads out the program address that needs to be changed in the mask ROM 2 stored in the RAM 5 (step n
1 B) o The CPU determines which group of the addresses grouped into multiple bytes of the mask ROM 2 shown in FIG. A flag l'' indicating that there is a program change in a predetermined area of RAM 3 is set (step n15) 0 In this embodiment, since addresses A and B of mask ROM 2 have been changed, address A-1°A of mask ROM 2 is set. ,A+
A flag 1'' is set in the area of the RAM 8 corresponding to the group of multiple bytes of 1 and the area of the RAM 8 corresponding to the group of multiple bytes of addresses B-1°B and B+1 of the mask ROM 2. When this setting operation is completed, (Step n16) The CPU reads the mode information selected by the mode selection key ``M'' in order to execute the process of the selected operation mode (Step n17), and the CPUI reads the mode information selected by the mode selection key ``M'' in order to execute the process of the selected operation mode 8. O size O L, -c ("": 1 piece 7. 1
8), 7ゎ. . Ya.

'i:.

The program corresponding to the predetermined operation mode stored in
- Select and specify \Ram and proceed to any one of steps n19 to n21.

Next, the execution procedure of the program stored in the mask ROM 2 will be explained according to the operation flowchart shown in FIG.

In this execution, the mask ROM 2 is sequentially addressed from the CPU, the programs in the ROM 2 are sequentially accessed, and the programs are executed (step n3
1). At this time, since RAM3 has the same addressing as mask ROM2 and address information is transferred from the CPU, it is addressed in synchronization with mask ROM2, and data at that address position is read out (step n32). ) o As mentioned above, '°0' is stored in the RAM 3 for address groups that do not require modification, and "1" is stored in address groups that require modification, and there is an "O" output from RAM 8. In this case, the flip-flop 12 is in a reset state. Therefore, C
PUIU sequentially advances the program steps of the mask ROM 2 until an interrupt signal, which is the set output of the flip-flop 12, does not arrive.

When the address position of the mask ROM 2 reaches the address position A-1 that requires a program change, a flag l'' is output from the RAM 3 and the flip-flop 12 is set. In step n88), the presence of the CP is detected based on the flag storage contents stored in the RAM8.
An interrupt signal (set output) is supplied to the UI to generate an interrupt (step n36).

In response to the interrupt signal, the CPUI updates the current address value A.
-1 is temporarily stored, and the address information stored in the RAM 5 is referred to to confirm whether or not this address information A-1 is included in this address information (step n
37*n88). However, address information A-1 is R
CPUI step n34 because it is not stored in AM5
to execute the work specified by the program (step n34), pass through step n85, and return to step n82. Next, when address A is specified in step n82, an interrupt is sent to the CPU as described above. Since the address A is deleted, the CPU determines whether the address A is stored in the RAM 5 in the same way as described above (step n32.ni3.
n36 to r18) 0 In this case, address A is stored in RAM 5, so the CPU
RAM4 that stores the corresponding modification program from
The address position XXXA is searched, and the modified program is specified by jumping to this modified program position (step n39). Therefore, the modification program stored after address XXXA in RAM 4 will be executed (step n40).

Also, a jump instruction is stored at the end of this modification program, and when the execution of this modification program is finished,
The flip-flop 12 is reset and the mask R
Jump to OM2 Step n41) Mask RO again
Execute the M2 program.
1 1i1 [&C, address positions B-1 and B that need to be changed again after sequentially executing the programs in the mask ROM 2.

When it reaches B+1, it sets flip-flop 12, interrupts the CPUI, and executes the same operation as described above.
At address location B, a modification program corresponding to the address location in RAM 4 is executed.

In the above embodiment, the case where various information necessary for program modification is read from the magnetic tape device was explained.
Instead of this magnetic tape device, various information storage devices and similar ECRs currently in general use may be connected in-line or online to transfer the information.
It goes without saying that the program modification information may also be set and input using manual means. Furthermore, RAM
Although 4 and 5 are expressed as separate addresses for convenience of explanation, separate addresses of the same RAM may be used.

As described above, according to the present invention, there is an address associated with the address bar of the mask ROM which is the first storage means for fixedly storing various transaction processing programs, and the program stored in the mask ROM at that address is stored. A storage means for storing whether or not a modification is necessary; a storage means for storing information indicating at which address the modification program is stored when it is determined that the modification is necessary; and a storage means for storing the modification program. , a storage device for storing information indicating at which address the modification program is stored, and a storage device for storing information regarding the plurality of bytes of the first storage device as to whether or not a change is necessary to the program; □Ran 1
Because it is configured to allocate bits, the conventional
This is extremely useful because it is possible to modify the program fixedly stored in the mask ROM very easily without replacing the mask ROM, and the RAM capacity necessary for modifying the program can be minimized, reducing costs. can provide a practical electronic register.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of an ECR embodying the present invention, Figures 2 (a) to (c) are diagrams showing the storage states of RAMs 4. FIGS. 3(a) and 3(b) are diagrams showing the storage state of the RAM 3 according to the invention.
) are respectively operation flow diagrams for explaining the program modification according to the present invention and previously proposed by the present applicant. FIG. 4 is an operation flow diagram for explaining the execution operation of the modification program of the apparatus of the present invention. 1...Central processing unit (CPU), 2...1st memory means, 2...2nd memory means, 4...4th memory means, 5...3rd memory means . Agent Patent Attorney Aihiko Fukushi (and 2 others) Figure 2, Figure 4, 1. ,, (G) □ 3rd (b) -・. 1

Claims (1)

[Claims] 1. A first storage means for fixedly storing a program such as a processing program for registering transactions in the electronic register or a processing program for inspecting and settling registered data in an electronic register that registers various transaction information; , a second storage means having an address related to the address of the storage means and storing information indicating whether or not a program has been changed corresponding to each address position; and a program change of the first storage means. A third storage means for storing an address and a storage address of a modification program thereof, and a fourth storage stage which has a different address from the first storage means and stores a modification program, /, c. and one bit of the second storage means is allocated to a plurality of bytes of the first storage means.