JPS5819126B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device including a step of forming a pn junction by ion implantation.

As the degree of integration of semiconductor devices increases, it becomes necessary to form shallow impurity regions in semiconductor substrates, and Si (
As (arsenic), which has a slower diffusion rate than silicon, is increasingly used as an impurity.

Further, when an impurity region is formed by ion implantation, annealing is performed to compensate for crystal defects caused by the ion implantation.

Even when a pn junction is formed by ion-implanting As into a Si substrate, annealing is performed after ion implantation, but it is desirable to anneal at a high temperature in order to improve the characteristics of the pn junction.

However, there is a drawback that the high temperature treatment causes As to diffuse and deepen the region formed by ion implantation.

Therefore, it has been difficult to form shallow impurity regions with good reproducibility and good characteristics.

The present invention improves the conventional drawbacks as described above, and A.
The object of the present invention is to provide a method that can improve the characteristics by annealing at a low temperature after s ion implantation.

Examples will be explained in detail below.

As shown in FIG. 1, when a window 3 is formed in an insulating film 2 such as 5i02 on a Si substrate 1 and a region 4 is formed by ion implantation of As, P (phosphorus), which has the same conductivity type as As, is formed. ')
, Sb (antimony), and other impurities are ion-implanted at a dose smaller than that of As.

The dose amount of P or sb relative to As is 5 to 20 times.

; That is, if the coefficient is less than 5, the effect of ion implantation of P or sb will hardly appear, and if it is more than 20, the amount of diffusion of P or sb will be large during annealing (as a result, a shallow region will be formed by As). However, the area becomes deep due to annealing.

As an example, As is applied to a Si substrate at a depth d and a dose of 1×10
16 atoms cIrL-2 were ion-implanted, P was further ion-implanted, and the depth increased by heat treatment was d.

The relationship between d/dO and after heat treatment ('C) is shown in FIG.

In the same figure, curve A is a P dose of 1 x 1015 atoms cIrL-2, and curve B is a P(7) dose of 2 x 1015.
This is for the case of the atom CIrL'.

As can be seen from the figure, when the P dose is 2 x 1015 atoms f-2 and the heat treatment temperature is 1000°C, the junction depth becomes approximately 1.26 times, but the dose is 1 x 101
In the case of 5 atoms -2, it only increases by 1.06 times,
In this case, the accelerating voltage during ion implantation is 5 for As.
0Kv, P is 25Kv.

Also, the dose of As was changed to KIXIO atom cIIL as described above.
-2, the reverse current of the pn junction is
When ions are also implanted, the reverse current is assumed to be ■/
■The relationship between o and P's dose honor is shown in Figure 3.

That is, assuming that the reverse current in the case of As alone is I/Io = 1, the dose of P is 1 x 1015 atoms C111,-2
When this happens, the reverse current ■/Io was 0.12.

In other words, the reverse current in the pn junction was reduced to about 1/10 by the P ion implantation.

Further, when crystal defects were observed using micrographs, it was found that as the dose of P was gradually increased relative to As, the number of crystal defects decreased.

This is consistent with the fact that the reverse current in the pn junction shown in FIG. 3 decreases as the P dose increases.

Note that even if ions are implanted at a dose of 20% or more of As, only a slight improvement effect is observed, and the effect of increasing the junction depth due to heat treatment appears.

Also, when Mi-b was used, similar results to those described above were obtained.

As explained above, in the present invention, impurities forming the same conductivity type as As, such as p and sb, are ion-implanted at the same time or before or after As ion implantation, so crystal defects are more likely to occur than in the case of As alone. Since the characteristics of the pn junction can be improved by low-temperature annealing, the characteristics of the pn junction can be improved.

In addition, an impurity of the same conductivity type as As is added at a dose of 5-
Ion implantation is performed at a dose of 20%, and as mentioned above, there is almost no effect of ion implantation of impurities such as p and sb, which have the same conductivity type as As, when the dose is less than 5%, and when it is over 20%, annealing is performed. Sometimes, it becomes impossible to form a shallow region due to diffusion of p, sb, etc.

□Therefore, impurities such as p and sb, which have the same conductivity type as As,
The optimal dose range is between 5 and 20 of the As dose.

As described above, since a pn junction with a shallow junction depth can be easily formed, the practical effect is very large when applied to highly integrated semiconductor devices such as bipolar type and MOS type.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of an impurity region formed by ion implantation, Figure 2 is a curve diagram of the heat treatment temperature and junction depth using the P dose as a parameter, and Figure 3 is the relationship between the P dose and reverse current. It is a curve diagram. 1 is a Si substrate, 2 is an insulating film, 3 is a window, and 4 is an ion implantation region.

Claims (1)

[Claims] I In a method for manufacturing a semiconductor device in which an impurity region is formed by ion-implanting As into a Si substrate, an impurity having the same conductivity type as the As to be ion-implanted is added at a dose of 5 to 20 times the dose of As. A method for manufacturing a semiconductor device, characterized in that ions are implanted into the impurity region.