JPS58189540U - High-density packaging hybrid integrated circuit - Google Patents

High-density packaging hybrid integrated circuit

Info

Publication number
JPS58189540U
JPS58189540U JP8615682U JP8615682U JPS58189540U JP S58189540 U JPS58189540 U JP S58189540U JP 8615682 U JP8615682 U JP 8615682U JP 8615682 U JP8615682 U JP 8615682U JP S58189540 U JPS58189540 U JP S58189540U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
density packaging
packaging hybrid
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8615682U
Other languages
Japanese (ja)
Inventor
入川 理徳
利昭 平間
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP8615682U priority Critical patent/JPS58189540U/en
Publication of JPS58189540U publication Critical patent/JPS58189540U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は従来のフラット・パッケージ形あるい
はデュアルインライン形のハイブリッドICの構造を示
す断面図。第3図、第4図は本考案の実施例を示す断面
図及び斜視図。 1:ハイブリ・クドIC基板、2:搭載部品、3ニブリ
ント基板、4:ハイブリッドICのリード、5:モール
ド材、6:はんだ、7:接着剤。
1 and 2 are cross-sectional views showing the structure of a conventional flat package type or dual-inline type hybrid IC. 3 and 4 are a sectional view and a perspective view showing an embodiment of the present invention. 1: Hybrid IC board, 2: Mounting components, 3 Niblint board, 4: Hybrid IC lead, 5: Mold material, 6: Solder, 7: Adhesive.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板面の片面に部品を搭載する構造のハイブリッドIC
において、これを2個組合せ、部品を搭載しない面どう
しを張り合わせると共に、外部との接続のためのリード
を基板面と垂直方向に曲げることにより、フラットパッ
ケージ形構造としたことを特徴とする混成集積回路。
Hybrid IC with a structure in which components are mounted on one side of the board
, by combining two of these, pasting the surfaces on which no components are mounted, and bending the leads for connection with the outside in a direction perpendicular to the board surface, a flat package structure is created. integrated circuit.
JP8615682U 1982-06-11 1982-06-11 High-density packaging hybrid integrated circuit Pending JPS58189540U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8615682U JPS58189540U (en) 1982-06-11 1982-06-11 High-density packaging hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8615682U JPS58189540U (en) 1982-06-11 1982-06-11 High-density packaging hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS58189540U true JPS58189540U (en) 1983-12-16

Family

ID=30094986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8615682U Pending JPS58189540U (en) 1982-06-11 1982-06-11 High-density packaging hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS58189540U (en)

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