JPS58186957A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS58186957A
JPS58186957A JP57069758A JP6975882A JPS58186957A JP S58186957 A JPS58186957 A JP S58186957A JP 57069758 A JP57069758 A JP 57069758A JP 6975882 A JP6975882 A JP 6975882A JP S58186957 A JPS58186957 A JP S58186957A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
semiconductor integrated
bed
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57069758A
Other languages
Japanese (ja)
Inventor
Yoji Chokai
鳥海　洋二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57069758A priority Critical patent/JPS58186957A/en
Publication of JPS58186957A publication Critical patent/JPS58186957A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To facilitate the positioning to a head center of a semiconductor integrated circuit chip and to prevent the creeping up of excess mounting agent to the chip surface by providing a groove which has a pattern indicating the bead center on the semiconductor integrated circuit chip bonding surface of the bed 2 in a lead frame. CONSTITUTION:A pattern of a groove 7 is formed on a semiconductor integrated circuit chip bonding surface of a bed 2 to clearly indicate the center of the bed. When the thickness of the lead frame 1 is 0.3mm., the size of the groove suitably has 0.3-0.5mm. of width and 0.1-0.2mm. of depth. As descirbed above, when the integrated circuit chip is bonded to the bed, it is ready to position at the center of the head. Accordingly, the irregular length of the wire can be reduced. Even if the quantity of mounting agent is much, it is accumulated in the groove on the bed, and it prevents the agent from creeping on the surface of the integrated circuit chip, thereby preventing the corrosion of the aluminum wirings on the surface of the integrated circuit chip.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体集積回路組立用のリードフレームに関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a lead frame for assembling semiconductor integrated circuits.

〔発明の技術的背景〕[Technical background of the invention]

半導体集積回路の組立においては、第７図に示すように
、半導体集積回路チップ参を搭載するべ品名コバール（
ＫＯＶムＲ）と呼ばれる鉄−二ッケル系合金若しぐは鋼
合金の薄板金属板をプレス若しくは禰４ｉＩ国１叡会漬
　　　　　　　　　　　工、チング等で所定の形状に抜
いたものが用いられる。In the assembly of semiconductor integrated circuits, as shown in Figure 7, the product name Kovar (
A thin metal plate made of an iron-nickel alloy or steel alloy called KOV is used, which is cut into a predetermined shape by pressing, machining, ching, or the like.

半導体集積回路を組立てる際には、まずリードフレーム
ｌ中のべ、トコに半導体集積回路チップｌを接着剤を主
成分とするマウンド剤で固定するマウンティングと呼ば
れる工程と、第２図に示すように半導体集積回路チップ
弘の各電極をこれと対応するリードフレームｌ中の各リ
ードＪＫ金若しくはアルミニウムのＩＩａｌｌｌｉでで
きたワイヤｊにより接続するワイヤボンディングと呼ば
れる工程が採られるのが一般的である。このようなリー
ドフレームとしては上述のようにプレス若しくは工。When assembling a semiconductor integrated circuit, the first step is a process called mounting, in which the semiconductor integrated circuit chip l is fixed all over the lead frame l using a mounting agent whose main component is adhesive. A process called wire bonding is generally used in which each electrode of a semiconductor integrated circuit chip is connected to each lead in a corresponding lead frame 1 using a wire made of gold or aluminum. Such a lead frame can be pressed or machined as described above.

チングで抜いたものを通常そのまま用いており、べ、ト
コの上面は平坦である。It is usually used as is after it has been cut out, and the top surface of the top is flat.

〔背景技術の問題点〕[Problems with background technology]

立を行う場合、べ、ド上面には位置合せの目標がないた
め半導体集積回路チップ弘をぺ、ドλの中央部に位置決
めしにくく、中央部への位置決めが行われなかつた場合
には、リードと電極の距離が長くなり、長いワイヤを張
る必要が生じる。このため１ＭＳ工、Ｌ８１ｆｉどビン
数の多い素子ではワイヤｊどうし、あるいはワイヤ！と
べ、トコとの間でのショートを起しやすいという問題点
がある。When performing vertical alignment, it is difficult to position the semiconductor integrated circuit chip in the center of the flat surface because there is no alignment target on the top surface of the flat surface.If positioning to the center is not performed, The distance between the lead and the electrode becomes longer, requiring a longer wire. For this reason, in devices with a large number of bins such as 1MS and L81fi, the wires are connected to each other, or the wires! There is a problem in that short circuits are likely to occur between the top and bottom.

また、半導体集積回路チップ参をぺ、トコに装着する九
めに用いる接着剤等のマウント剤１は。Also, the mounting agent 1, such as adhesive, is used to attach the semiconductor integrated circuit chip to the top and bottom.

第３図に示すように、半導体集積回路チップ参の側面に
付着したときははい上り現象により半導体集積回路チッ
プ−の表面に到達し、マウント剤ぶて含まれる塩素イオ
ンや、半導体集積回路チップリ、半導体集積回路チップ
参の表面のアルミニウム配線が腐食することがある。As shown in Fig. 3, when it adheres to the side surface of a semiconductor integrated circuit chip, it reaches the surface of the semiconductor integrated circuit chip due to the crawling phenomenon, and the chlorine ions contained in the mounting agent and the semiconductor integrated circuit chip adhere to the surface of the semiconductor integrated circuit chip. Aluminum wiring on the surface of semiconductor integrated circuit chips may corrode.

〔発明の目的〕[Purpose of the invention]

そこで本発明は、チップの位置決め不良に伴うワイヤの
ショート及びマウント剤過多による半導体集積回路チッ
プ表面のアルミニウム配線の腐食をなくす仁とができる
リードフレームを提供する〔発明の概要〕 本発明は、リードフレームｌ中のベッド−〇半導体集積
回路チップ貼付は面にベッド中心を表示するパターンを
有するマウント剤逃げ用の溝を設けることにより半導体
集積回路チップのベッド中央部への位置決めの容易化と
、過剰なマウント剤の半導体集積回路チャ１面へのはい
上りを防止しようとするものである。SUMMARY OF THE INVENTION The present invention provides a lead frame that can eliminate corrosion of aluminum wiring on the surface of a semiconductor integrated circuit chip due to wire shorting due to poor positioning of the chip and excessive mounting agent. Bed-〇 Semiconductor integrated circuit chips are attached in the frame l by providing grooves for escape of the mounting agent with a pattern indicating the center of the bed on the surface to facilitate positioning of the semiconductor integrated circuit chips to the center of the bed and to avoid excess This is intended to prevent the mounting agent from creeping up onto the surface of the semiconductor integrated circuit.

〔発明の実施例〕[Embodiments of the invention]

本発明の実施例を第１図及び第１図により説明する。 An embodiment of the present invention will be described with reference to FIGS.

第弘図はべ、トコの半導体集積回路チップ貼付面上に設
けた線溝７のパターンの例のいくつかを示しており、第
ｖ図（ａｌのような十字状、第参図（１））のようなＸ
字状、第μ図（０）のような放射状、第参図（（１）の
ような格子状婢が表わされている。これらはいずれもべ
、ドの中心を明確に表示するパターンとなっている。Figures 1 and 2 show some examples of the patterns of the line grooves 7 provided on the semiconductor integrated circuit chip mounting surface. ) like
A radial pattern as shown in Figure μ (0), and a grid pattern as shown in Figure 1 (1). It has become.

第１図は本発明に係る溝を設けたべ、トコの断面図であ
って、溝の断面形状の例のいくつかを示している。第５
図（＆）のようなＶ字状、第１図（ｂ）のような矩形状
、第５図（ａ）のようなＵ字状のいずれも使用可能であ
る。溝の寸法はリードフレームｌの厚さが０．３ｍとす
れば、幅は０．１〜０．２■、深さはθ、ｌ〜０．コ■
程度が適当である・なお、溝のパターン及び断面形状は
これらの実施例に限られるものではなく、ぺ、ドの中心
を示すパターンであってマウント剤を溜めることのでき
るような断面形状を持つもので置き換えることができる
。FIG. 1 is a cross-sectional view of a piece provided with grooves according to the present invention, and shows some examples of the cross-sectional shapes of the grooves. Fifth
Any of a V-shape as shown in the figure (&), a rectangular shape as shown in FIG. 1(b), and a U-shape as shown in FIG. 5(a) can be used. If the thickness of the lead frame l is 0.3 m, the width of the groove is 0.1 to 0.2 mm, and the depth is θ, l to 0.3 m. Ko ■
The pattern and cross-sectional shape of the groove are not limited to these examples, but the pattern and cross-sectional shape of the groove should be such that it indicates the center of the pedestal and can store the mounting agent. It can be replaced with something.

〔発明の効果〕〔Effect of the invention〕

集積回路チップをぺ、ド部に貼り付ける際にぺ。 When attaching the integrated circuit chip to the front and rear parts.

ド部の中央に位置決めすることが容易であるためワイヤ
の長さのばらつきが少くなり、ワイヤどうしあるいはワ
イヤとべ、ドとの間のショートの発生が減少するという
効果がある。Since it is easy to position the wire in the center of the wire, there is less variation in the length of the wire, which has the effect of reducing the occurrence of short circuits between wires or between wires and wires.

また、集積回路チップをベッドに貼り付けるためのマウ
ント剤の量が多目であっても、４４１騙１１の ＃溝にｍまるため、マウント剤が集積回路チップの表面
にはい上ることを防止でき、集積回路チ。In addition, even if a large amount of mounting agent is used to attach the integrated circuit chip to the bed, it will fit into the # groove of 441-11, preventing the mounting agent from climbing onto the surface of the integrated circuit chip. , integrated circuits.

プ表面のアルミニウム配線の腐食を防止することかで龜
る。This is slowed down by preventing corrosion of the aluminum wiring on the surface of the board.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はリードフレームと半導体集積回路チ。 プを示す説明図、第２図はワイヤボンディングを示す説
明図、第３図はマウント剤の半導体集積回路チャ１表面
へのはい上りを示す説明図、第参図は本発明に係るリー
ドフレーム上に設けられた溝のパターンを示す図、第１
図は、本発明に係るリードフレーム上に設けられた溝の
断面形状を示す図である。 ／・・・リードフレーム、２・・・ぺ、ド、３・・・リ
ード、ダ・・・半導体集積回路チップ、！・・・ワイヤ
、６・・・マウント剤、７・・・溝。 出願人代理人　　猪　　股　　　　　清第１図 第２図 第９図 第４図 （ａ） （ｂ）Figure 1 shows a lead frame and a semiconductor integrated circuit. FIG. 2 is an explanatory diagram showing wire bonding, FIG. 3 is an explanatory diagram showing how the mounting agent crawls onto the surface of the semiconductor integrated circuit cha 1, and FIG. Figure 1 showing the pattern of grooves provided in
The figure is a diagram showing a cross-sectional shape of a groove provided on a lead frame according to the present invention. /...lead frame, 2...pe, de, 3...lead, da...semiconductor integrated circuit chip! ...Wire, 6...Mounting agent, 7...Groove. Applicant's agent Kiyoshi Inomata Figure 1 Figure 2 Figure 9 Figure 4 (a) (b)

Claims (1)

【特許請求の範囲】[Claims] 半導体チップを懺着するペデド面に、中心位置を表示す
る溝を設けえととを特徴とするリードフレーム。A lead frame characterized by having a groove to indicate the center position on the pedestal surface on which a semiconductor chip is attached.
JP57069758A 1982-04-26 1982-04-26 Lead frame Pending JPS58186957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57069758A JPS58186957A (en) 1982-04-26 1982-04-26 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57069758A JPS58186957A (en) 1982-04-26 1982-04-26 Lead frame

Publications (1)

Publication Number Publication Date
JPS58186957A true JPS58186957A (en) 1983-11-01

Family

ID=13412011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57069758A Pending JPS58186957A (en) 1982-04-26 1982-04-26 Lead frame

Country Status (1)

Country Link
JP (1) JPS58186957A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057129U (en) * 1983-09-28 1985-04-20 日本インター株式会社 semiconductor equipment
JPS60132332A (en) * 1983-12-20 1985-07-15 Fuji Xerox Co Ltd Wiring substrate for hybrid ic
US6127206A (en) * 1997-03-24 2000-10-03 Seiko Epson Corporation Semiconductor device substrate, lead frame, semiconductor device and method of making the same, circuit board, and electronic apparatus
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057129U (en) * 1983-09-28 1985-04-20 日本インター株式会社 semiconductor equipment
JPS60132332A (en) * 1983-12-20 1985-07-15 Fuji Xerox Co Ltd Wiring substrate for hybrid ic
US6127206A (en) * 1997-03-24 2000-10-03 Seiko Epson Corporation Semiconductor device substrate, lead frame, semiconductor device and method of making the same, circuit board, and electronic apparatus
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle

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