JPS58186830A - Data transferring device - Google Patents

Abstract

PURPOSE:To prevent a temporary holding state at a reception side, by writing data which is transferred between devices for data transmission and reception in a memory temporarily, and reading and transferring the data in the memory at the reception side after all data are written. CONSTITUTION:When data is transferred from a storage device SF by direct memory access, the transfer data is stored in a buffer register D REG temporarily. The stored data is written in an address of a memory MEM indicated by a memory controlling circuit M CONT. After all data are written, a switching device controlling part ESS CPU reads the written transfer data out of the memory MEM successively in response to a transfer end signal to transfer them to the switching control part ESS CPU through a signal line 3. Data transfer from the switching control part ESS CPU to the storage device SF is executed in the same manner.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device for transmitting and receiving data between a sending device and a receiving device in an electronic exchange system using direct memory access.

Conventionally, in electronic exchange systems where data transfer is performed by direct memory access, the control units on the sending and receiving sides temporarily enter a trade-protection state for this process, allowing them to perform other controls. , resulting in a decrease in processing capacity.

In particular, since real-time processing is required in the telephone switching line of an electronic switching system, it is necessary to provide a dedicated processor for data transfer, which inevitably increases equipment costs.

An object of the present invention is to temporarily write data transferred between devices that perform data transfer by direct memory access, for example, between a storage device and an electronic exchange control device, into a memory at a predetermined timing via a buffer register. After writing is completed, the receiving side reads the transfer data written in this memory and sends/receives the data, thereby preventing the receiving side control unit from going into a pending state during data transfer by direct memory access. The object of the present invention is to provide a data transfer device 1 that is capable of performing various functions.

The present invention provides a data transfer device disposed between a sending side device and a receiving side device in an electronic exchange system that transmits and receives data by direct memory access, after temporarily accumulating data from the sending side device in a buffer register.
A memory that accumulates data at a predetermined timing of its own device, a control circuit that controls writing and reading data to this memory, a register that displays the data transfer status on the sending and receiving devices, and data transmission and reception control. The data transfer state display causes the receiving side device to read the stored data in the memory 1m times.

Embodiments of the present invention will be described below with reference to the drawings.

The figure is a configuration diagram showing an embodiment of the present invention. In FIG. 1, ESS CPU is a control unit of an electronic switching device, SF is a storage device, MEM is a memory control circuit that temporarily stores transfer data, and C0NT is a memory control circuit that controls writing and reading of transfer data of flM. 8 R, EG are status registers that display the transmission/reception status of transfer data, C3lN'f
' is a control interface circuit that controls data transmission and reception, Sl and S are signal switching circuits included in MC0NT, C0UNT is a counter circuit in MCON T, and D
REGldM This is a data (buffer) register that temporarily holds transfer data in C0NT. Also, reference number 1 is the MEM transfer data read and write signal line from the ESSCPU side, and 2 is the MEM transfer data line from the ESSCPU side.
M transfer data indulgence and write address signal line;
3 is a data signal line, 4 is a control signal line of S REG, 5 is a data signal line that transfers the status of transfer data from S BEG to ESS CPU, and 6 is a setting for transmitting and receiving status of transfer data from C3lN'l'. 7 is the data signal on the 8F side for data transfer between the 8F and the ESS CPU! , 8.9 is a control signal line for transmitting and receiving transfer data to and from SF, 10 is a data signal line for writing and reading transfer data of MFiM, and 11 is M for C31NT.
12 is a control signal line for C0UN'r from C31NT; 13 is a control signal line for writing and reading from MEM; 14 is an address signal line for MEM; 15
is the address signal line from C0UNT, and 16 is the address signal line from 8
This is a control signal line from BEG to C0UNT.

In the data transfer device configured as described above, when data is transferred from 8F using the direct memory access method, a transfer request signal from SF is sent to C81N through signal line 8.
T receives. C3lN'l' sets a transfer request state for 8 RgG through the signal line 6 in response to the received transfer request signal. 8 1 (nG makes an interrupt request to the WSs CPU through signal line 3.5. ESS C
In response to this interrupt request, the PU executes a read command for the cause of the interrupt via the signal line 4.

8 When the BEG receives the read command, it returns a transfer request signal, which is the cause of the interrupt, to the ESS5-CPU through signal lines 3 and 5. In accordance with this transfer request signal, the EBB CPU executes an instruction to set a transfer ready signal for signal #4 all-through SLE EG. 8 Rh1U operates C3lN'r through signal line 6 in accordance with this command, and returns a control signal indicating completion of transfer preparation to 8F through signal line 9. When SF recognizes that transfer preparation is complete, it then sends a transmission start signal to C3lN'l' via signal ll118. C3lNT follows this transmission start signal and sends a signal &! to MC0NT. 11. MEM of data transferred through 12
Controls the 1-input address and the incorporation into the address. Next, when data is transferred from the SF through the signal line 7, the transferred data is temporarily stored in the DREG. Accumulated data is written to the MEM at an address indicated by the signal line 15 and the S2y tracing signal line 14 by a write signal transmitted via the signal line 13 via the signal line 11 and Sl.

C0UNT transfers data from SF through signal line 7 to D.
Each time the BEG receives data, it is counted up, the output is updated sequentially, and the transferred data is sequentially written to different addresses of the MEM. C3lNT through which the data transfer end signal from SF to 6- passes through signal line 8.
When input to ``,''C3IN'f'' sets transfer completion to S R and EG through signal line 6f as in the case of a transfer request, and also updates the address of C0UNT and signals line 11 through signal #12. Then, writing is stopped, and data writing to and from the MEM is stopped. Then, SILEG sends an interrupt request signal ffk! according to this transfer completion information. 3゜5
through the gss CPU. This allows ESSC
The PU executes a read command causing the interrupt via the signal line 4 in accordance with the interrupt command. When the S BEG receives this read command, it sends back a transfer completion signal, which is the cause of the interrupt, to the ESS CPU through signal lines 3 and 5.

In response to the transfer completion signal, the ESS CPU requests the S_EG via the signal line 4 to return the final address at which the transfer data was written to the MEM. S R,E(] controls C0UNT through the signal line 16 according to this return request, and C0UNT
ESSC the final address from T via signal lines 3 and 15
Return it to PU. Continuation e c', ESSCPU is MEM
The reading control is performed on signal line 1. The address is specified through signal line 2, S2, and signal line 14 through Sl and signal Iw13, and the transfer data written in the MBM is transferred to signal line 1 to the final address where the transfer data was written.
ESs CP through signal line 3.
'U transfers the transfer data sent from 8F to ESS. In addition, the above is ESS rather than SF.
I explained about data transfer to CPU, but ES
The same can be done for the SF rather than the SCPU.

As explained above, the present invention provides a memory for temporarily storing transferred data between devices of an electronic exchange system that transfers data by direct memory access via a buffer register at a predetermined timing of the device itself. By sequentially writing all the data to be transferred and having the receiving side read it and transfer the data, it is possible to prevent the receiving device from being temporarily put on hold even with direct memory access, and to meet real-time processing requirements. There is no mention of the decline in processing capacity of electronic switching equipment.

[Brief explanation of drawings]

The figure is a configuration diagram showing an embodiment of a data transfer device according to the present invention. ESS CPU・・・・Electronic switching power manufacturing control unit, S
F...Storage device, MWM...Memo IJ
, M CON'I'...Memory control circuit, S
IG...Status register, C3lNT...
・・Control interface circuit 1S1・S2・・・・
...Switching circuit, C0UNT...Counter circuit, DIG...Data register. 9-

Claims (1)

[Claims] In a data transfer device placed between a sending device and a receiving device in an electronic exchange system that transmits and receives data by direct memory access, data from the sending device is temporarily stored in a buffer register, and then transferred to a predetermined location of the own device. A memory that accumulates data based on timing, a control circuit that controls data writing and reading to this memory,
The apparatus includes a register for displaying a data transfer state on the transmitter and receiver devices, and an interface circuit that controls data transmission and reception, and causes the receiver device to sequentially read stored data in the memory according to the data transfer state display. A data transfer device with all the following characteristics.