JPS62108345A - Data communication circuit - Google Patents

Abstract

PURPOSE:To decrease the number of parts of an equipment, and to reduce the burden of a CPU by coupling plural CPUs through a first-in first-out FIFO memory, and providing a means for initializing the FIFO memory in accordance with a command of one CPU. CONSTITUTION:A CPU selects an FIFO memory 3 having necessary and sufficient capacity in accordance with the quantity of data to be delivered, and buffering of the data is executed in the FIFO memory 3. Accordingly, each CPU can execute access to the FIFO memory 3 without having a waiting time. Also, an internal state of the FIFO memory 3 is varied automatically, and its internal state can be known by a full signal F and an empty signal E, therefore, a command register becomes unnecessary. Moreover, in order to initialize the FIFO memory 3, a reset input R which is supplied to an address pointer is supplied to the FIFO memory 3 through a register 4 from the second CPU side.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention enables data transfer between CPUs in a control system configured using a plurality of CPUs at low cost and reduces the burden on the CPU as much as possible. The present invention also relates to a data communication circuit that achieves high data reliability.

[Prior Art] As a communication circuit between CPUs, a communication circuit as shown in FIG. 3, for example, is conventionally known. Here, 11 is the first (:PII) on the sending side, 12 is the sending side command register that notifies that data has been sent, 13 is the sending side output data register that latches the data, and 14 is the checking state of the receiving side. A transmitting side status register, 21 is the second C'PU on the receiving side, 22 is a receiving side status register that checks whether there is transmission data, 23 is a receiving side input data register that latches data, 24 is whether reception is possible. This is a receiving side command register that notifies whether or not there is an error.

However, in such a communication circuit, the first and second CPf
Output data register 13 on each side of Ill and 21
and an input data register 23, and also requires a combination of the transmitting side command register 12, the receiving side command register 24, the receiving side status register 22, and the transmitting side status register 14 in order to set the timing of data transfer. This increases the number of points, leading to increased costs and decreased reliability, which is also unfavorable from the standpoint of miniaturizing equipment.

Furthermore, each (:PIll and 21 must judge whether or not the output data register 13 and the input data register 23 can be accessed while checking the states of the transmitting side status register 14 and the receiving side status register 22, so the communication This has disadvantages in that it requires a large amount of CPU time, increases software overhead, and reduces communication speed.

[Problems to be Solved by the Invention] Therefore, the purpose of the present invention is to reduce the number of parts in data exchange between CPUs in order to downsize the device, and to eliminate the need to provide a dedicated communication processor. To,
An object of the present invention is to provide a data communication circuit that can reduce the burden on a CPU for data communication.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a data communication circuit that transmits and receives data between a plurality of CPUs. The first-in/first-out memory is connected via a first-in/first-out memory that can be temporarily stored, and includes a reset means for initializing the first-in/first-out memory in response to a command from any one of the plurality of CPUs. Features.

[Function] In the present invention, a first-in/first-out memory, that is, a FIFO memory, which can be read/written asynchronously, is used as a data transfer register, and both CPUs
By simplifying the status register and command register to prevent access conflicts from U, the number of parts used is reduced, and each CPt1 can be used at a convenient timing regardless of the state of the other CPU. Data can be accessed.

According to the present invention, since the generation of command signals and status signals necessary for communication can be left to the FIFO memory, the number of components in the communication circuit can be significantly reduced, and costs can also be reduced.

Effects such as miniaturization of the device and improvement in device reliability can be obtained.

[Example code] The present invention will be described in detail below with reference to the drawings.

An embodiment of the present invention is shown in FIG. Here, the t cp
As a data register between u it and the second CPt 121, there is a first-in/first-out memory that can temporarily store data, that is, a FIFO.
Place memory 3. The t-th CPU 11 transfers data to the FIFO at any time unless the FIFO memory 3 is full.
It can be written to memory 3. 2nd CPII21 is F
If the IFO memory 3 is not empty, data can be read out continuously until it becomes empty.

By selecting a FIFO memory 3 with a necessary and sufficient capacity according to the amount of data to be transferred, data is buffered within the FIFO memory 3, and each CPU can access the FIFO memory 3 with almost no waiting time. can. Further, the internal state of the FIFO memory 3 automatically changes by reading/writing to the FIFO memory 3, and the internal state can be known from the full signal F and the empty signal E, so a command register is not required.

Furthermore, in order to initialize the internal state of the FIFO memory 3, the reset human power R supplied to the address pointer is transmitted from the second CPLI 21 side to the FIFO memory 3 via the control register 4.
Supplied to FO memory 3. Thereby, the address pointer in the FIFO memory 3 can be initialized when the power is turned on and when a communication error occurs.

FIG. 2 shows another embodiment of the present invention, in which:
Unlike FIG. 1, the data width (number of bits) is increased by providing a plurality of FIFO memories, for example, a first FIFO memory 31 and a second FIFO memory 32 in parallel. As a result, the size of data that can be handled by one instruction can be increased, and it can be easily connected to a 16-bit or 32-bit CPU. Moreover, in this example, data is sent with a check code attached, an error check is performed on the receiving side, and the result is sent from the control register 4 to the status register 5 to the first
By notifying the CPt 111, more reliable data communication and detailed error handling become possible.

[Effects of the Invention] As is clear from the above, according to the present invention, command signals and status signals necessary for communication are generated using FIFO.
Since the communication circuit can be left to the memory, the number of components in the communication circuit can be significantly reduced, and effects such as cost reduction, miniaturization of the device, and improvement in device reliability can be obtained.

Furthermore, by using the buffering function of FIFO memory, each CPU can write or read multiple words of data all at once at a convenient timing, so it rarely interferes with the operation of the other CPU. It disappears. This has the advantage that the overhead for communication processing by each CPU can be suppressed, and each CPU can spend more time on its original control processing.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing another embodiment of the invention, and Fig. 3 is a block diagram showing a conventional inter-CPU data communication circuit. be. 3...FIFO memory, 4...FIFO control register, 5...Status register, 11...1st CPII. 12... Sending side command register, 13... Sending side data register, 14... Sending side status register, 21... Second
C.P.II. 22...Receiving side status register, 23...Receiving side data register, 24...Receiving side command register. A\zu%'s month is mostly drawn 11 figures 8
The moon has a lot of filth, 2nd latitude, 5th figure, 2nd figure.

Claims (1)

[Claims] In a data communication circuit that sends and receives data between a plurality of CPUs, the plurality of CPUs are coupled via a first-in/first-out memory that can temporarily store data, and the plurality of CPUs are connected via a first-in/first-out memory that can temporarily store data. A data communication circuit comprising a reset means for initializing the first-in/first-out memory in response to a command from one of the CPUs.