JPH0642233B2 - Data transfer control method - Google Patents

Description

The present invention relates to a data transfer control method, and more particularly to a data transfer control method in a data transfer system for transferring between a plurality of microprocessor systems using a data bus.

[Conventional technology]

Conventionally, in this type of data transfer system, the bus controller has the first method in which there is only one transmission register (hereinafter, SR) and one reception register (hereinafter, RR), or a plurality of transmission / reception buffers for data transfer. The second method is generally used in which the bus controller is dedicated and is provided separately from the memory of the microprocessor.

[Problems to be Solved by the Invention]

The first method of the above-mentioned conventional methods is that, even if transmission requests to the bus are issued from the microprocessor one after another at short time intervals, if the SR does not become empty (that is, until the transmission of data to the bus is completed). ) Since SR cannot be set,
It is necessary to form the transmission request queue for the bus control device by software, which has the drawback that the transmission processing amount of software increases and the transmission processing capability decreases, and regarding reception, there is a data reception request from the bus. Even if they occur one after another at short time intervals, since there is only one RR, the microprocessor recognizes the received data from the bus,
Until the next data is received, the next data cannot be received until RR is set again, which has the disadvantage that the ability to receive data from the bus is effectively reduced. Since it is necessary to form the reception buffer queue by software, there is a drawback that the reception processing amount of software increases and the reception processing capacity decreases.

Further, the second conventional method has a possibility of eliminating the drawback of the first method because a plurality of transmission / reception buffers are prepared on the bus controller side, but since an external memory is required as hardware, This has the drawback of increasing the amount of hardware in the controller and also reducing the processing power as software also requires copying data from the microprocessor memory to the external memory and vice versa.

An object of the present invention is to eliminate the above drawbacks and provide a data transfer control system that does not impose a processing load on software and has a small amount of hardware.

[Means for Solving the Problems]

The data transfer control method of the present invention is a data transfer system having a plurality of data transfer circuits on a bus, wherein each of the data transfer circuits is a microprocessor, a memory, and a data transfer connected to the bus, the microprocessor and the memory. And a control circuit, wherein the data transfer control circuit has a plurality of first-in / first-out types configured to store a start address of the memory in which data to be transmitted is stored, the number of transfer bytes, and an agent address of a transmission partner. A transmission register, and a transmission control circuit that transmits data on the bus according to a set order when the microprocessor sets a value in at least one of the transmission registers and sends a transmission completion report to the microprocessor upon completion of the transmission. The memory area where the received data should be stored A plurality of receiving registers configured as a first-in / first-out type for storing the start address on the memory and the maximum number of receiving bytes; and when the microprocessor sets a value in at least one of the receiving registers, A reception control circuit for storing the data received from the bus in a designated memory area of the memory and for reporting the reception completion to the microprocessor upon completion of the reception.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 (a) is a system block diagram of a data transfer system showing an embodiment of a data transfer control system of the present invention.
FIG. 1B is a detailed block diagram of the data transfer control circuit in FIG. 1A.

As shown in FIG. 1 (a), the data transfer system of this embodiment includes a plurality of agents (hereinafter, AGT) 1 to n connected to a data bus (hereinafter, DB) 30 and each AGT.
(Eg AGT1) is a data transfer control circuit (hereinafter CT
L) 11, a microprocessor (hereinafter referred to as μP) 12 connected to the CTL 11 via a microprocessor bus (hereinafter referred to as μPB) 14, and a surface (hereinafter referred to as MEM) 13 that stores transmission / reception data, and the CTL 11 is connected to the DB 30. Has been done.

As shown in FIG. 1B, the CTL 11 includes a transmission register FIFO memory (hereinafter, SFIFO) 111, a reception register FIFO memory (hereinafter, RFIFO) 112, a transmission control circuit (hereinafter, SCTL) 113, a reception control circuit (hereinafter, RC).
The SFIFO 111 includes a TL) 114, m transmission registers (hereinafter, SR _{1 to} SR _m ) form a FIFO (first in / first out), and the RFIFO.
Reference numeral 112 denotes m reception registers (hereinafter, RR _{1 to} RR _m ).
Constitutes the FIFO. Although not shown in the figure, a transmission memory address register (hereinafter referred to as SMAR) and a transmission word number register (hereinafter referred to as SBR) which respectively store the start address of the MEM 13 storing the data to be transmitted, the number of transfer bytes, and the agent address of the transmission partner are described. And the transmission destination agent address register (hereinafter referred to as SAAR) are generically referred to as SR, and although not shown, the head address on the MEM 13 of the memory area to be received and the maximum number of received bytes are stored respectively. The reception address register (hereinafter referred to as RAR) and the reception buffer length register (hereinafter referred to as RBR) are collectively referred to as RR.

Here, the connection and operation between the μP 12 side and the CTL 11 will be described.

In FIG. 1, 10 write signal lines (IOW) 22 are connected to write instruction terminals of SFIFO 111 and RFIFO 112, and μP12 is IO through μPB14.
The data on the memory data signal line (hereinafter MDAT) 26 by activating the W22 _SR 1, ~SR _m or R
Write to R ₁ and RR _m .

First, the bus data transmission operation will be described.

SR ₁ , to SR _{m form} a FIFO, and are sequentially written to SR 1 that has not been used, such as SR ₁ immediately after reset and SR ₂ next. Suppose now that SR ₁ to SR ₅ are written, SFIFO11
1 is SR using the read signal line 111a of SCTL113
Read the contents of ₁ . SR ₁ is SMA as described above.
It is composed of R, SBR and SAAR. SCTL
113 determines that there is a transmission request when at least one of SR ₁ to SR _m is written, and activates the bus use right request line (hereinafter referred to as BRQ) 31 to DB 30 to activate DB 30.
Request to obtain the right to use. When the right to use DB30 is acquired, the bus use permission line (hereinafter referred to as BAK) 3 from DB30 itself
2 is activated, and the SCTL 113 recognizes that it has acquired the bus use right. SCTL1 when you get the right to use the bus
13 activates the μPB usage right request line (hereinafter referred to as HRQ) 24 to acquire the usage right of μPB 14, and when the usage right of μPB 14 is granted from μPB 14 itself or μP 12
The use permission line (HAK) 25 is activated to activate SCTL.
113 recognizes that it has acquired the right to use the μPB 14. In this state, the SCTL 113 is the SR ₁ SAA.
The value of R is sent to the partner agent address signal line (hereinafter DA) 33 on the DB 30, the value of SMAR is sent to the memory address signal line (hereinafter MADR) 23, and the memory read signal line (hereinafter MAD) 21 is activated. By doing
One byte of data is read from the MEM 13 via the MDAT 26 and is read as a bus data signal line (hereinafter referred to as DAT).
A) to the bus data write signal line (hereinafter DW)
R) 35 is activated to transmit data to the DB 30. When one byte of the transmission data has been transmitted, the SCTL 13 next sends the value obtained by adding 1 to the value currently held in the MADR 23 to the MADR 23 to perform the above operation. This operation is repeated the number of times indicated by SBR. When this series of operations is completed, the SCTL 113 becomes HR.
Q24 and BRQ31 are inactivated, SFIFO111
The pulse is transmitted to the shift clock signal line 111b.
Then, since the SFIFO 111 has a FIFO structure, the contents of SR ₂ up to now are SR ₁ , the contents of SR ₃ are SR ₂ , the contents of SR ₄ are SR ₃ , and the contents of SR ₅ are SR.
Shifted to ₄ .

Next, the bus data receiving operation will be described.

RR _{1 to} RR _{m form} a FIFO, and are written to RR ₁ immediately after reset, and to RR ₂ next, so that they are sequentially written like SFIFO 111. When data is now received from the DB 30, that is, the value on the DA 33 matches the predetermined own agent address, the bus data read signal line (DRD) 3
When 6 is activated, RCTL114 is DB30
It is determined that the data has been received from the device, and the HRQ 24 is activated to acquire the used line of the μPB 14. The use right of μPB14 is permitted from μPB14 itself or μP12 to HA
When K25 is activated, RCTL114 causes μPB14
Recognize that you have acquired the right to use. In this state, RCTL 114 is RR ₁ (as described above, RAR and RB
The contents of R) are read, the value of RAR is sent to MADR23, and the memory write signal line (hereinafter referred to as M
By activating (WR) 27, the data of DATA 34 is transferred to the memory area designated by RAR of MEM 13. Then, a value obtained by adding 1 to the value of MADR 23 is transmitted to perform the above operation. This operation is continued for the number of times indicated by RBR or until the data transfer from the DB 30 is completed (until the DRD 36 is not activated for a certain time), and after the transfer is completed, the RCTL 114 deactivates the HRQ 24, and the RFIF
A pulse is sent to the shift clock signal line 112b of O112 to shift the RFIFO 112 by one.

When the transmission operation is completed, the SCTL 113 activates the transmission completion signal (hereinafter referred to as SEND) 20, and when the reception operation is completed, the RCTL 114 is connected to the reception completion signal line (hereinafter referred to as REN).
D) 28 is activated, and the μP 12 is notified of the completion of the operation via the μPB 14.

〔The invention's effect〕

As described above, according to the present invention, by using the register having the FIFO mechanism for the control of the bus transmission operation and the bus reception operation, the software waits the software controlled queue outside the bus transfer control circuit for the bus control. There is an effect that it is not necessary, and since there is no memory dedicated to the data buffer, there is an effect that the data copy with the microprocessor is unnecessary.

[Brief description of drawings]

FIG. 1 (a) is a system block diagram of a data transfer system showing an embodiment of a data transfer control system of the present invention.
FIG. 1B is a detailed block diagram of the data transfer control circuit in FIG. 1A. 1, to n ... Agent (AGT), 11 ... Data transfer control circuit (CTL), 12 ... Microprocessor (μP), 13 ... Memory (MEM), 14 ... Microprocessor bus (μPB), 20 ... … Transmission completion signal line (SEND), 21 …… Memory read signal line, (MR
D), 22 ... IO write signal line (IOW), 23 ... Memory address signal line (MADR), 24 ... μPB usage right request line (HRQ), 25 ... μPB usage permission line (HA)
K), 26 ... Memory data signal line (MDAT), 27
...... Memory write signal line (MWR), 28 …… Reception completion signal line (REND), 30 …… Data bus (DB), 3
1 ... Bus usage right request line (BRQ), 32 ... Bus usage permission line (BAK), 33 ... Partner agent address signal line (DA), 36 ... Bus data signal line (DAT)
A), 35 ... Bus data write signal line (DWR), 3
6 ... Bus data read signal line (DRD), 111 ...
Transmission register FIFO memory (SFIFO), 111
a, 112a ... Read signal line, 111b, 112b ...
Shift clock signal line, 112 ... Reception register FIF
O memory (RFIFO), 113 ... Transmission control circuit (S
CTL), 114 ... Reception control circuit (RCTL), RR
₁ , ~ RR _m ... reception register, SR ₁ , ~ SR _m ...
Transmit register.

Claims (1)

[Claims] 1. A data transfer system having a plurality of data transfer circuits on a bus, wherein each of the data transfer circuits includes a microprocessor, a memory, and a data transfer control circuit connected to the bus, the microprocessor and the memory. The data transfer control circuit comprises a plurality of transmission registers configured as a first-in / first-out type for storing a start address of the memory in which data to be transmitted is stored, the number of transfer bytes, and a transmission partner agent address, A transmission control circuit for transmitting data on the bus according to a set order when the microprocessor sets a value in at least one of the transmission registers, and transmitting completion report to the microprocessor upon completion of the transmission, and storing received data The top add on the memory of the memory area to be And a plurality of receive registers configured as a first-in first-out type for storing a maximum number of received bytes, and receiving from the bus according to an order set when the microprocessor sets a value in at least one of the receive registers. A data transfer control method, comprising: a reception control circuit that stores data in a designated memory area of the memory and reports reception completion to the microprocessor upon completion of reception thereof.