JPS58182902A - Frequency modulator under frequency synchronization control - Google Patents

Frequency modulator under frequency synchronization control

Info

Publication number
JPS58182902A
JPS58182902A JP6593982A JP6593982A JPS58182902A JP S58182902 A JPS58182902 A JP S58182902A JP 6593982 A JP6593982 A JP 6593982A JP 6593982 A JP6593982 A JP 6593982A JP S58182902 A JPS58182902 A JP S58182902A
Authority
JP
Japan
Prior art keywords
frequency
oscillator
difference
converter
synchronization control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6593982A
Other languages
Japanese (ja)
Inventor
Toshiyuki Sakai
俊行 酒井
Susumu Hanaoka
花岡 進
Akihiko Ichikawa
明彦 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6593982A priority Critical patent/JPS58182902A/en
Publication of JPS58182902A publication Critical patent/JPS58182902A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03CMODULATION
    • H03C3/00Angle modulation
    • H03C3/02Details
    • H03C3/09Modifications of modulator for regulating the mean frequency

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain a modulator of small-scale circuit constitution by detecting the polarity of a difference frequency between a reference frequency and the mean frequency of a frequency-modulated wave, and performing frequency synchronization. CONSTITUTION:A frequency difference polarity detector 7 detects whether the difference of the frequency of a voltage-controlled oscillator 6 from the frequency of a reference frequency oscillator 1 is positive or negative by making a comparison between both. Binary pulses from this detector 7 are sent to a up/ down counter 8 to output binary pulses based upon whether the shift in the mean frequency of the oscillator 6 from the reference frequency and they are converted into an analog value by a D/A converter 9. The output of this converter 9 is converted almost into a direct current by a loop filter 4' to obtain a control voltage, which is fed back to the oscillator 6 to synchronize the mean frequency with the reference frequency of the oscillator 1. Thus, the need for a frequency divided of large-scale circuit constitution is eliminated to reduce the circuit constitution.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は被周波数変調波の平均周波数を基準周波数に同
期さす周波数変調器(周波数同期制御周波数変調器)に
係り、特に音声の広帯域伝送に使用する場合、小規模な
回路で実現出来る周波数同期制御周波数変調器に関する
[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a frequency modulator (frequency synchronization control frequency modulator) that synchronizes the average frequency of a frequency-modulated wave with a reference frequency, and is particularly applicable to broadband audio transmission. This invention relates to a frequency synchronization control frequency modulator that can be realized with a small-scale circuit when used.

(b)  従来技術と間魅点 第1図は従来例の周波数同期制御周波数変vj4益のブ
ロック図である。
(b) Prior Art and Attractive Points FIG. 1 is a block diagram of a conventional frequency synchronization control frequency variation vj4 gain.

図中1は基準周波数発振器、2. 2’は1/N分局カ
ウンタ、3は位相比較器、4はループフィルタ、5は加
算回路、6は電圧制御発振器、Vは変a14個号の振巾
を示す。
In the figure, 1 is a reference frequency oscillator, 2. 2' is a 1/N branch counter, 3 is a phase comparator, 4 is a loop filter, 5 is an adder circuit, 6 is a voltage controlled oscillator, and V is the amplitude of the variable a14.

動作としては、一定の周波数で発振して込る電圧制御発
振器6及び基準周波数発振器1の出力周波数を1/N分
周カウンタ2’、2’にて1/Nとし、変調指数金工げ
、位相比較器3にて位相比較する?l!lI舛範囲全2
πラジアン以内とし、位相差による1差電圧をループフ
ィルタ4を介し殆んど1u流成分とし、加算回路5を介
し電圧制御発振器6に帰還して、電圧制御発ti器6の
平均周波数を基準発振器1の周波数に同期さしている。
In operation, the output frequencies of the voltage-controlled oscillator 6 and the reference frequency oscillator 1, which oscillate at a constant frequency, are set to 1/N by the 1/N frequency division counters 2', 2', and the modulation index, metal processing, and phase are adjusted. Compare the phase with comparator 3? l! lI masu range all 2
Within π radians, the 1 difference voltage due to the phase difference is passed through the loop filter 4 to become almost a 1u current component, and is fed back to the voltage controlled oscillator 6 via the adder circuit 5, and the average frequency of the voltage controlled oscillator 6 is used as a reference. It is synchronized with the frequency of oscillator 1.

周波数変調を竹う場合は変調信号の振巾Vを加算回路5
に加え、振巾の大きさにより電圧制御発振器6の中心脚
仮数(平均周波数)から周波数を増減さして周波数変調
を行っている0しかし音声の広帯域伝送の場合は最低周
数数が30Hz程嵐であシ又被周V畝笈調波の一位は一
般的に75kHzであるので巌―指数は75000 /
 30 = 2500ラジアンとなり、これt2πラジ
アンにするためには、1/N分周カウンタ2,2′のN
t−400にする必簀があシ、1/N分周カウンタ2,
2′の回路規模が非常に大きくなり、周波数同期制御周
波数変調器の回路規模が大きくなる欠点がある。
When frequency modulation is used, the amplitude V of the modulation signal is added to the adder circuit 5.
In addition to this, frequency modulation is performed by increasing or decreasing the frequency from the center leg mantissa (average frequency) of the voltage controlled oscillator 6 depending on the magnitude of the amplitude.However, in the case of broadband audio transmission, the minimum frequency is about 30Hz. Since the first harmonic of the reed-shaped V-furrow harmonic is generally 75 kHz, the rock index is 75000/
30 = 2500 radians, and in order to make this t2π radians, N of the 1/N frequency division counters 2 and 2' must be
There is a need to set it to t-400, 1/N frequency division counter 2,
There is a drawback that the circuit scale of 2' becomes very large, and the circuit scale of the frequency synchronization control frequency modulator becomes large.

(c)  発明の目的 本発明の目的は、音声の広帯域伝送に使用する場合、小
規模な回路で実現出来る周波数同期制御周波数変調器の
提供にある。
(c) Object of the Invention An object of the present invention is to provide a frequency synchronization control frequency modulator that can be realized with a small-scale circuit when used for broadband audio transmission.

(d)  発明の構成 本発明は上記の目的を構成するために1基準周波数と被
周波数変調波の平均周波数との走周波数の極性を検出し
、2周波の位相差が2πラジアン以上i化した時、lI
+14御パルス全パルス、被Ml波数変plvを出力す
る電圧制御発振−の中心矯波数を制御するもので、回路
規模の大きくなる分周器を不賛にし、小規模な回路構成
で周波数同期側御周改数変w4書が実現出来るようにし
たことを特徴とする。
(d) Structure of the Invention In order to achieve the above object, the present invention detects the polarity of the running frequency between one reference frequency and the average frequency of the frequency-modulated wave, and the phase difference between the two frequencies is 2π radian or more. time, lI
It controls the center wave number of the voltage controlled oscillation which outputs all +14 control pulses and the Ml wave number variable PLV, which eliminates the need for a frequency divider which increases the circuit scale, and allows the frequency synchronization side to be achieved with a small circuit configuration. It is characterized by making it possible to realize the Goshu Kaikai Hen W4 book.

(cl  発明の実施例 以下本発明のl実施例につき図に従って説明する0第2
図は本発明の実施例の周波数量ルj制御周波数賞調器の
ブロック図である。
(cl Embodiments of the Invention Below, embodiments of the present invention will be explained according to the drawings.
The figure is a block diagram of a frequency control frequency adjuster according to an embodiment of the present invention.

図中第1図と同一機能のものFi陣]−配量で示す。In the figure, those having the same functions as those in FIG.

7は周波数差極性検出器、8はアップダウンカウンタ、
9はディジタル・アナログ変換器(以下D・Aコンバー
タと称す)、4′はループフィルタ′(11−ボす。
7 is a frequency difference polarity detector, 8 is an up/down counter,
9 is a digital-to-analog converter (hereinafter referred to as a D/A converter), and 4' is a loop filter' (11-bore).

動作としては基準周波数発振器1の周波数を基準とし、
電圧制御発振器6のM1波数との差が正か負であるかを
、周波数差極性検出器7で比較検出し、JI!Ll波数
差に応じた2値のパルス(周波数差が止か負かを表す)
をアップダウンカウンタ8に送り、電圧111#発m器
6の平均周波数と基準周波数とのずれの正負によシ2値
のパルスを出力させ、D@Aコンバータ9によりアナロ
グ値に変換する。
The operation is based on the frequency of the reference frequency oscillator 1,
The frequency difference polarity detector 7 compares and detects whether the difference with the M1 wave number of the voltage controlled oscillator 6 is positive or negative, and JI! Binary pulse according to Ll wave number difference (represents whether the frequency difference is stopped or negative)
is sent to the up/down counter 8 to output a binary pulse depending on the positive or negative difference between the average frequency of the voltage 111# oscillator 6 and the reference frequency, which is converted into an analog value by the D@A converter 9.

この場合電圧Ill 111発振器6の平均周波数が基
準周改数に等しい1合り@Aコンバータ9の出刃を12
値(lと0)の中心値に設定しておく。D−Aコンバー
タ9の出力を、ループヒイルタ4′により間周叔成分及
び不*波を抑圧して、殆んど11流とし、変調信号の振
巾Vに影響を与えないようKし、制御電圧として電圧制
御発振器6に帰還して、平均周波数が基準周波数発振器
1の基準周波数に同期するようにしている。勿論周波数
変調を行う場合は、変脚信号の振巾マを加算仲」路5に
加え、珈巾の大きさによす電圧制御発振器6の中心周波
数(平均周波数)から周波数を増減さして周波数渡肖を
行う。この−合、周波数差極性検出器7は、本出願人が
昭和56年12月25日出願の周波数比較191路bu
ち、周波数n−fI(n=自然数)の信号をカウントす
るカウンタ、該カウンタの少なくとも2ビツトヲ胸鼓欽
f0の信号によってラッチするラッチ回路、該ラッチ回
路のラッチ出力信号の遷移を識別して前記周波数f・と
周波数f、との周1&数差の極性を検出する遷移識別回
路と全備えた回路、又をゴ従米用いられているアナログ
的な2胸波のビートを検出して正負を判定する方法奄あ
るがいずれも回路規模は第1図の位相比較器3biであ
シ、アップダウンカウンタ8及びD−Aコンバータ9の
回kr規模は1 / 400分周カウンタよりかなシ少
さい。従って本発明の周波数同期制御周波数変調器は従
来の1/Nの分周カウンタを用いるものよシー路規模は
かなり少さい。
In this case, if the voltage Ill 111 is equal to the average frequency of the oscillator 6 and the reference frequency number, the output of the A converter 9 is 12
Set it to the center value of the values (l and 0). The output of the D-A converter 9 is reduced to almost 11 currents by suppressing interfrequency components and inactive waves by the loop filter 4', and is set to 11 so as not to affect the amplitude V of the modulation signal, and the control voltage is The average frequency is fed back to the voltage controlled oscillator 6 so that the average frequency is synchronized with the reference frequency of the reference frequency oscillator 1. Of course, when frequency modulation is performed, in addition to adding the amplitude modulation of the variable leg signal to the frequency modulation path 5, the frequency is increased or decreased from the center frequency (average frequency) of the voltage controlled oscillator 6 depending on the width of the amplitude. perform a portrait. In this case, the frequency difference polarity detector 7 is the frequency difference polarity detector 7 of Frequency Comparison No.
A counter that counts signals with a frequency n-fI (n = natural number), a latch circuit that latches at least 2 bits of the counter according to the pulse f0 signal, and a transition of the latch output signal of the latch circuit that is identified as described above. A transition identification circuit that detects the polarity of the frequency difference between frequency f and frequency f, and a complete circuit that detects the beat of the analog 2-chest wave that is used to determine whether it is positive or negative. There are many ways to do this, but in either case, the circuit scale is the phase comparator 3bi shown in FIG. 1, and the circuit scale of the up/down counter 8 and the DA converter 9 is much smaller than that of a 1/400 frequency division counter. Therefore, the frequency synchronous control frequency modulator of the present invention has a considerably smaller sea path scale than the conventional frequency modulator using a 1/N frequency division counter.

(f)  発明の効果 以上許細に説明した如く、本発明によれば、埼波数同期
制御胸波数ip器を音声の広帯域伝送に使用する場合、
回路規模を少さく出来る効果がある0
(f) Effects of the Invention As explained in detail above, according to the present invention, when a high frequency frequency synchronous control chest frequency IP device is used for wideband audio transmission,
Has the effect of reducing the circuit scale0

【図面の簡単な説明】[Brief explanation of drawings]

第1図#′i促米例の周波数同期制御周波数変調器のブ
ロック図、第2図は本発明の実施例の周波数IWJ期制
仙j周波数変調器のブロック図である。 図中1は基準周波数発振器、2,2′は1/N分周カウ
ンタ、3は位相比較器、4. 4’はループヒイルタ、
5F′i加算回路、6fi電圧馴@発振器、7は周波数
差極性検出器、8はアップダウンカウンタ、9にD−A
コンバータ、■は賞詞イ6ちの振巾tボす。
FIG. 1 is a block diagram of a frequency synchronization control frequency modulator according to the example #'i, and FIG. 2 is a block diagram of a frequency IWJ synchronization frequency modulator according to an embodiment of the present invention. In the figure, 1 is a reference frequency oscillator, 2 and 2' are 1/N frequency division counters, 3 is a phase comparator, and 4. 4' is loop hilta,
5F'i addition circuit, 6fi voltage adjustment @ oscillator, 7 is frequency difference polarity detector, 8 is up/down counter, 9 is D-A
Converter, ■ is the award word I6, the width of the t-boss.

Claims (1)

【特許請求の範囲】[Claims] 被周波数変調波の平均周波数を基準8仮数に同期させる
周波数置IA器において、咳基準周波数と該被周波数変
調波の平均周波数との差周波数の極性を検出し、周波数
を同期させることを替像とする周波数同期制御周波数変
調器。
In a frequency positioner that synchronizes the average frequency of a frequency-modulated wave with a reference 8 mantissa, an alternative method is to detect the polarity of the difference frequency between the cough reference frequency and the average frequency of the frequency-modulated wave and synchronize the frequencies. Frequency synchronous control frequency modulator.
JP6593982A 1982-04-20 1982-04-20 Frequency modulator under frequency synchronization control Pending JPS58182902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6593982A JPS58182902A (en) 1982-04-20 1982-04-20 Frequency modulator under frequency synchronization control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6593982A JPS58182902A (en) 1982-04-20 1982-04-20 Frequency modulator under frequency synchronization control

Publications (1)

Publication Number Publication Date
JPS58182902A true JPS58182902A (en) 1983-10-26

Family

ID=13301429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6593982A Pending JPS58182902A (en) 1982-04-20 1982-04-20 Frequency modulator under frequency synchronization control

Country Status (1)

Country Link
JP (1) JPS58182902A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399998A (en) * 1991-11-18 1995-03-21 Nec Corporation Digital FM modulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399998A (en) * 1991-11-18 1995-03-21 Nec Corporation Digital FM modulator

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