JP2825290B2 - Phase-locked oscillation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillation circuit for obtaining a stable oscillation frequency in a microwave band.

[Conventional technology]

A phase-locked oscillation circuit using a sampling phase detector is widely known as a highly stable oscillation circuit in a microwave band.

FIG. 3 is a block diagram showing a configuration of a phase-locked oscillation circuit using a conventional sampling phase detector.

In the figure, the reference signal input from the input terminal 31 is
The signal is input to one input terminal of a sampling phase detector (SPD) 32, and the output is input to a voltage controlled oscillator (VCO) 34 via a loop filter 33. The output of the voltage controlled oscillator 34 is taken out from the output terminal 35 as a microwave output, and is fed back to the other input terminal of the sampling phase detector 32 to form a phase locked loop.

With this phase locked loop, a highly stable microwave output synchronized with the reference signal can be obtained at the output terminal 35.

Here, the sampling phase detector 32 directly compares the phase of the harmonic component of the low-frequency signal with the phase of the ultra-high-frequency signal by sampling the ultra-high-frequency signal (microwave output) with the low-frequency signal (reference signal). This is a phase comparator.

In the phase-locked oscillation circuit using the sampling phase detector 32, when the frequency of the reference signal and the oscillation frequency of the voltage-controlled oscillator 34 become an integer ratio, the output of the sampling phase detector 32 becomes constant, and the phase-locked loop enters the locked state. Become. If it is different from the integer ratio, use the sampling phase detector.
32 controls the oscillation frequency of the voltage controlled oscillator 34 by generating a beat signal.

In such a conventional phase-locked oscillation circuit, the pull-in of the frequency is performed by the average DC voltage resulting from the asymmetry of the positive half cycle of the beat signal and the negative half cycle, but when the beat frequency increases, the average DC voltage increases. When the voltage decreases and falls below the noise level, the phase locked loop does not enter the locked state. Therefore, it can be said that the phase locked oscillation circuit using the sampling phase detector has a narrow lock-in frequency range.

Literature (IEEE Trans Aerosp Electron Syst vol.16 No.
3, pp. 410-414, 1980) has two sampling phase detectors (sample and hold circuit in the literature) to address this problem, and as a frequency controller when the phase locked loop is not synchronized. It describes a configuration of a phase-locked oscillation circuit that operates as a phase controller when the phase-locked loop is almost in a synchronized state, and expands the lock-in frequency range.

FIG. 4 is a block diagram showing a main configuration of the phase-locked oscillation circuit described in this document.

In the figure, a reference signal output from a reference signal generator (Ref) 41 is input to a 1/2 frequency divider 42, and one output () of the reference signal together with the output of a voltage controlled oscillator (VCO) 43 is is input to the sample-and-hold circuit (SH1) 44 _1. The output signal u ₁ of the first sample and hold circuit 44 ₁ is supplied to a low-pass filter (LPF) 45, an integrator 46, and a hard limiter 47.
Is input to

The other output (Q) of the 1/2 frequency divider 42 is connected to a delay line (T ₀ /
4, T ₀ is input together with the output of the voltage controlled oscillator 43 through the oscillation cycle) 48 of the voltage controlled oscillator to the second sample-and-hold circuit (SH2) 44 _2. Second sample and hold circuit
The output signal u ₂ 43 ₂ is input to the hard limiter 49, the output signal u ₂ 'are the output signals u ₁ of the control signal u ₃ and hard limiter 47 via the one-shot multivibrator 50',
_{1 ',} a logical product is taken respectively AND gates 51 _1, 51 _2, the output signal, is input to the integrator 46. Integrator
The output of 46 is input to the voltage controlled oscillator 43 via the low-pass filter 45, and the oscillation frequency is controlled.

Here, the reference signal frequency f _s, the oscillation frequency f ₀ of the voltage controlled oscillator 43, in the case that is a relation of _{2Nf s <f 0 <(2N} + 1) f s, as shown in FIG. 5, hard limiter 47 Output signal u ₁ ′ (dotted line), hard limiter 49
The output signal u ₂ '(solid line) and the one-shot multivibrator 50 is the control signal u ₂ the phase of the output. Therefore, the output signal of the AND gate 51 _1, the output signal u ₁ '
Is a logical product of the control signal u ₃ and the logical signal “0”,
The output signal of the AND gate 51 ₂ is a control signal u ₃ because it is the logical product of the output signal _{1 'and} the control signal u _3. The same applies if the have a relationship of _{(2N-1) f s <} f 0 <2Nf s.

With such a configuration, it is possible to operate as a frequency controller when the phase-locked loop is not synchronized, and to operate as a phase controller when the phase-locked loop is almost synchronized, thereby expanding the lock-in frequency range. However, the sampling frequency in this circuit is as low as 100 kHz.

[Problems to be solved by the invention]

By the way, when the voltage-controlled oscillator forms a phase-locked oscillation circuit that oscillates in the microwave band, the sampling frequency must be set to about 100 MHz. However, for such a high sampling frequency, the circuit shown in FIG. 4 has a problem that a digital IC such as a hard limiter or a one-shot multivibrator constituting a frequency control system does not operate.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase-locked oscillation circuit that can operate a frequency control system even at a high sampling frequency and can expand a lock-in frequency range.

[Means for solving the problem]

The present invention provides a first and a second sampling phase detector in which a reference signal is input to each one of the input terminals, and an output of the oscillator according to each output signal of the first and the second sampling phase detector. Frequency control signal generating means for outputting a frequency control signal, an adding circuit for adding the output signal of the first sampling phase detector and the frequency control signal, and a loop filter for removing high-frequency components from the added signal,
An oscillation frequency is set in accordance with the addition signal through the loop filter, and a voltage-controlled oscillator whose oscillator output is connected back to each sampling phase detector is provided.The first and second sampling phase detectors have A phase-locked oscillation, in which a reference signal is input with a phase shift of 90 degrees with respect to the oscillator output phase, or an oscillator output is input with a phase shift of 90 degrees with respect to each other to generate the oscillator output synchronized with the reference signal. In the circuit, the frequency control signal generating means includes a differentiating circuit for differentiating the output signal of the second sampling phase detector, and a mixer for multiplying the output signal of the first sampling phase detector by the differential circuit output signal. And a smoothing filter for smoothing the mixer output signal and outputting the smoothed signal as a frequency control signal.

(Operation)

When the phase-locked loop is not synchronized, the phase-locked oscillation circuit of the present invention operates as a frequency controller by the second sampling phase detector and the frequency control signal generating means. Further, when the phase locked loop is substantially in a synchronized state, the output (frequency control signal) of the frequency control generating means becomes 0 and its operation is stopped, so that it is constituted by the first sampling phase detector and the loop filter. And the phase controller performs phase acquisition.

In the present invention, since the frequency control signal generating means capable of performing such an operation is constituted only by an analog circuit including a differentiating circuit, a mixer and a smoothing filter, synchronization can be performed even at a high sampling frequency, and synchronization can be achieved. The pull-in frequency range can be expanded.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, the reference signal input from the input terminal 11 is
Is input to the first sampling phase detector (SPD) 12 ₁ and a second sampling phase detector (SPD) 12 each one input terminal of _2. First output signal of the sampling phase detector 12 ₁ is input to the one input terminal of the mixer 13 and the adding circuit 14. Second sampling phase detector 12 ₂
Is input to the other input terminal of the mixer 13 via the differentiating circuit 15. The output signal of the mixer 13 is input to the other input terminal of the addition circuit 14 via the smoothing filter 16. The output signal of the adding circuit 14 is input to a control terminal of a voltage controlled oscillator (VCO) 18 via a loop filter 17. The output of the voltage controlled oscillator 18, together with the taken out from the output terminal 19 as a microwave output, each via a first sampling phase detector 12 ₁ and 90 degree phase shifter 20 of the second sampling phase detector 12 ₂ A feedback connection is made to the other input terminal to form a phase locked loop.

The sampling phase detectors 12 ₁ , 12 ₂ shown here
Is a sample-and-hold circuit shown in the conventional configuration of FIG.
44 _1, 44 ₂ and those equivalent.

FIG. 2 is a time chart showing the waveform of each signal according to the embodiment of the present invention. ,... Correspond to the numbers of the respective signals shown in FIG.

Hereinafter, the operation of each part of the embodiment of the present invention will be described with reference to FIG. 1 and FIG.

A reference signal frequency is f _r, when the free-running oscillation frequency of the voltage controlled oscillator 18 and f _0, f ₀ <when Nf _r of (N is integer closest to f ₀ / f _r), the first sampling phase detector Container 12 ₁
The output signal of the second output signal of the sampling phase detector 12 ₂ is a phase relationship respectively by the solid line and dotted line in FIG. 2 (a). Also, when f _0> Nf _r is the output signal, is a phase relationship shown respectively Figure 2 (b).

That is, when f ₀ <Nf _r, the output signal -sinω
t and the output signal is cosωt (ω = | f ₀ −Nf
_r |). In addition, at the time of the f _0> Nf _r, the output signal is sinωt
And the output signal is cosωt.

As described above, the first sampling phase detector 12 depends on whether the free-running oscillation frequency (f ₀ ) of the voltage-controlled oscillator 18 is detuned up or down with respect to the harmonic (Nf _r ) of the reference signal frequency. _first output signal and the second sampling phase detector 12 _{and second} output signal of the phase delay will determine whether advances 90 degrees from each other.

Such output signal of the sampling phase detector 12 ₁ is input to one input terminal of the mixer 13, the output signal of the sampling phase detector 12 ₂ to the other input terminal via the differentiation circuit 15, 90 Since the signals are inputted out of phase, the output signal of the mixer 13 has the waveform shown in FIG. 2 (c).

That, <ωsin ^{2 ωt} next when the Nf _r (solid line), f _0> f ₀ becomes -ωsin ² ωt when the Nf _r (dotted line).

Therefore, if the output signal of mixer 13 is output via the smoothing filter 16, <a positive DC voltage at the time of Nf _r, f _0> f ₀ becomes a negative DC voltage at the time of Nf _r. This DC voltage is summed with the first output signal of the sampling phase detector 12 ₁ in the addition circuit 14, a loop filter 1
The free-running oscillation frequency f ₀ is fed back to the voltage controlled oscillator 18 via the
Frequency control is applied so as to approach the Nf _r.

On the other hand, the free-running oscillation frequency f ₀ of the reference signal frequency harmonics Nf
When the value approaches _r , the output of the differentiating circuit 15 approaches 0, so that the output signal of the mixer 13 also becomes 0 and the frequency control automatically stops, and the first sampling phase detector input to the adding circuit 14 12 retraction phase is performed by only _one of the output signal.

Thus, in the present invention circuit, when the phase locked loop out of sync, a second sampling phase detector 12 ₂
The frequency control of the voltage-controlled oscillator 18 is performed by a frequency control system configured by an analog circuit from to the smoothing filter 16.

Further, when the phase-locked loop becomes substantially synchronous conditions, the operation of the frequency control system is stopped, the phase pull the oscillation frequency by the configured phase control system in the first sampling phase detector 12 ₁ and a loop filter 17 Then, the microwave output synchronized with the reference signal can be taken out.

In this embodiment, the output of the voltage controlled oscillator 18 is
The configuration in which the 90-degree phase shifter 20 shifts the phase by 90 degrees to each sampling phase detectors 12 ₁ and 12 ₂ has been described. However, as in the conventional configuration shown in FIG. vessel
12 _1, 12 ₂ reference signal input to, may take a structure to each other by 90 degree phase shift of the phase with respect to the oscillator output (microwave).

〔The invention's effect〕

As described above, the present invention includes a frequency control system including only analog circuit elements, and thus can operate even at a high sampling frequency. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a time chart showing the waveform of each signal of the embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a phase-locked oscillation circuit using a conventional sampling phase detector. FIG. 4 is a block diagram showing a main configuration of a phase-locked oscillation circuit having two sampling phase detectors. FIG. 5 is a diagram for explaining the operation of a phase-locked oscillation circuit having two sampling phase detectors. 11 Input terminal, 12 Sampling phase detector (SP
D), 13 mixer, 14 addition circuit, 15 differentiation circuit, 16 smoothing filter, 17 loop filter, 18
... voltage controlled oscillator (VCO), 19 ... output terminal, 20 ... 90
Degree phase shifter, 31 Input terminal, 32 Sampling phase detector (SPD), 33 Loop filter, 34 Voltage controlled oscillator (VCO), 35 Output terminal, 41 Reference signal generation (Ref), 42: 1/2 frequency divider, 43: Voltage controlled oscillator (VCO), 44: Sample and hold circuit (SH1, SH2), 4
5 ... Low-pass filter (LPF), 46 ... Integrator, 47, 49
…… Hard limiter, 48 …… Delay line, 50 …… One-shot multivibrator, 51 …… And gate.

Claims (1)

(57) [Claims] A first and a second sampling phase detector for inputting a reference signal to one input terminal thereof, and an oscillator output corresponding to each output signal of the first and second sampling phase detectors. Frequency control signal generating means for outputting a frequency control signal, an addition circuit for adding the output signal of the first sampling phase detector and the frequency control signal, and a loop filter for removing a high frequency component from the addition signal. A voltage-controlled oscillator whose oscillation frequency is set according to the addition signal via the loop filter and whose oscillator output is connected back to each of the sampling phase detectors, wherein the first and second sampling phases are The reference signal is input to the detector after being shifted by 90 degrees with respect to the oscillator output phase, or the oscillator outputs are mutually In a phase-locked oscillation circuit which is input after being shifted by 90 degrees and generates the oscillator output synchronized with the reference signal, the frequency control signal generating means includes a differential for differentiating an output signal of the second sampling phase detector. A mixer that multiplies the output signal of the first sampling phase detector with the output signal of the differentiating circuit, and a smoothing filter that smoothes the output signal of the mixer and outputs the signal as the frequency control signal. A phase-locked oscillation circuit, characterized in that: