JPS58108833A - Phase-locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of a phase-locked loop circuit by varying the output data of an up/down-counter with time, and thus reduce output impure waves due to a phase comparison through relatively simple circuit constitution. CONSTITUTION:A fundamental wave fO is inputted to an up/down-clock generating circuit 21 to generate an up-clock and a feedback wave fO' from the output of a frequency divider 26 is used to generate a down-clock. The up-or down- clock 7 appearing at the output side of the clock generating circuit 21 is inputted to the up/down-counter 22, whose count value is increased or decreased by one. The value of the up/down-counter 22 is inputted as an (n)-bit digital signal to a D/A converter 23, wherein it is converted into an analog voltage (or current). The output of the D/A converter is inputted to a voltage-controlled oscillator 25 through a low-pass filter 24. The output frequency NXf0' of the voltage- controlled oscillator 25 is divided to fO', which is fed back to a phase comparator 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical aspects of the invention The present invention relates to a phase-locked Loog circuit mK, and particularly relates to a phase-locked Loog circuit mK.
The present invention relates to a phase-locked loop 1 circuit configured to reduce the generation of output impurity waves caused by K.

(2) Background of the technology In recent years, in the circuit configurations of communication equipment, measurement equipment, automatic control equipment, etc., the phase ratio we, 'low-pass FIIE! )~A phase-locked loop (PLL) circuit consisting of a voltage controlled oscillator and a frequency divider is often used.

In a complex phase-locked loop circuit, it is generally important to minimize the generation of output impurity waves caused by the phase comparator.

(3) Prior Art and Problem 1 A conventional phase-locked circuit is shown in FIG. 1, which is configured to reduce the output impurity wave.

The circuit of FIG. 1 consists of a phase comparator 11 consisting of a logic r-gate or a free-lag frog, a low-pass P-wave device 12,
Analog voltage adder 13, voltage side gas 114, beat (Una9) detector 1''5, ah! - Consists of an I run counter 16, a dinotal to analog CD/A) converter 17, and an IA frequency divider 18.

In the circuit shown in Fig. 111, a phase comparator 11, a low-pass P wave generator 12, a voltage controlled oscillator 14, and a frequency divided +51
A bifurcated phase-locked loop consisting of 8! Apart from the configuration, beat detector 15, a!・Down counter 6-D/A converter 17, voltage controlled oscillator 14 and branch! A beat detecting digital control loop consisting of 118 is constructed and is coupled to the phase locked looper in analog voltage adder 13.

Therefore, in the phase-locked router circuit of FIG. 1, the output frequency N
The beat at X/' can be removed and 11Il
It is possible to generate clock pulses with constant clock pulse distances. Incidentally, a phase-locked loop 1 circuit as shown in FIG. 1 is disclosed in, for example, Japanese Patent Application No. 52-96527.

By the way, in the circuit shown in Figure J11, digital control by beat detection and analog control by general phase ratio # are performed by separate control routers.
The scale of the road has increased and the price has increased □ A! There is a problem with doing so.

(4) Purpose of the Invention The main purpose of the present invention is to solve the problems of the conventional type described above. Based on the idea of switching the output digital amount of the down counter in analog time using phase comparison, one loop! The object of the present invention is to provide a single phase-locked loop circuit having a simple circuit configuration, which can perform general phase comparison control and beat detection control, and can remove output impurity waves caused by phase comparison.

(5) Structure of the Invention In the present invention, one phase synchronization loop consisting of a phase ratio aS, a low-pass P-wave device, a voltage control circuit 4, and a divider is provided. In the circuit, #X phase comparator is a,! Clocks and clocks down,! It includes a generation circuit, an output down counter, and a digital-to-analog converter.・
By changing the output data of the down counter over time, the voltage 919 having an average value corresponding to the phase difference at the time of phase comparison is outputted as the output analog quantity of the electric Rt-f4 notal to analog converter. A phase-locked loop 1 circuit is provided, which features:

(6) Embodiment of the Invention A phase-locked loop 1 circuit as an embodiment of the present invention is shown in FIG. The circuit shown in FIG. 2 has a phase ratio 41! which is composed of an A, G/〆KUNKRO, RI generation circuit, 211 A/DOWN KAK/RI 22, and a RHE conversion 623. Vessel 20. It is composed of a low-pass P wave generator 24, a voltage controlled oscillator 25, and an IA frequency divider 26.

A more detailed circuit configuration of the phase comparator 20 in FIG.
As shown in the figure. As shown in the figure s3, the Ag/Dakunkro/Ri generation circuit 21 is a flip f709f circuit 211.
．． 212 and NAND r-) circuits 213 and 214. In the circuit shown in Figure 11s2, the fundamental wave f0 is manually input to the Ag/Meun clock generation 1gl step 21 to generate the 4I11 wave at the output of the branch station 26. /,
/ generates a down counter. Kurozuku generation circuit 2
1's output side A, G/Down force 9, N, and D are manually inputted to A, G/DOWN force 9 and E22, and each count value is set to A,! and bring down. The count value of the input 22 is input as an n-bit digital signal to the D/A converter #2-3, thereby converting it into an analog voltage (or 1tvi).

The output of the D/A converter is input to the voltage controlled oscillator 25 through a low-pass P wave a24. 'Output frequency l1lNxfc of Narita control oscillation a25, / is lA frequency division di26
Ru.

The characteristics of the circuit shown in Figures 2 and 3 are shown in Figure 4.
, (13)K is shown. Figure 4 ■ shows the fundamental wave 9 and 4 R.
The phase difference between fi /, /, that is, Ama! 1 shows the correspondence of the control voltage vc of the LF1BIIg4 oscillator 25 to the count of the DOW7 counter 22. No. 4110
1) shows a change in the control voltage vc, that is, the output of the 1-converter 23, corresponding to the phase shift between the fundamental wave f0 and the feedback wave fJo. As shown in Figure 4 (0), the fluctuations during the phase comparison of the K D/A fi loss device 25 are averaged to the fundamental wave f0.
Since the phase difference between the feedback wave fJ and the output frequency Nx1. ; B) O generation can be suppressed.

Another configuration example of the phase ratio plate 20 in the circuit of FIG. 2 is shown in FIG. The circuit shown in FIG. 5 differs from the circuit shown in FIG. 3 in that it stops the 7th clock or down clock when the a, g/down counter overflows or underflows. The correspondence relationship of the control voltage vc to the phase difference between the fundamental wave f0 and the sliding wave /,7 in the circuit of FIG. 5 is shown in FIG. Compared to the circuit shown in FIG. 3, the circuit shown in FIG. 5 can eliminate erroneous control of the voltage controlled oscillator at the time of loss of synchronization (in the circuit shown in FIG. 5, the output frequency loses its beat).

(7) Effects of the Invention According to the present invention, it is possible to reduce output impurity waves caused by phase comparison with a relatively simple circuit configuration using a phase synchronization loop, thereby reducing the circuit scale. It's difficult. Therefore, the number of parts can be reduced, and effects such as improved reliability, power saving, and reduced parts cost can be obtained.

[Brief explanation of the drawing]

The first diagram shows the conventional phase synchronization system! Figure 3 is a circuit diagram showing an example of the configuration of the phase comparator in the circuit of Figure 2. Figure 4 (translated), @) is a diagram showing the operating characteristics of the circuit in Figure 3; Figure 5 is a circuit diagram showing another configuration sequence of the phase comparator in the circuit in Figure 2; The figure is a diagram showing the operating percentage of the circuit of FIG. 5. (Explanation of symbols) 11: Phase ratio R6, 12: Low range AAFliml, 13
: Analog voltage generator, 14: Voltage controlled oscillator, 15
: Beat Detector, 16: A, Gu・〆Unkakunta, 17
: D/A converter, 18 bifurcater, 20: Phase comparator: 21, 21': Ag/Uncro, ri occurs! <22
．． 22': Agg/〆Uncounter, 23.23': D
/Am converter, 24: Low frequency pass 11 Excess P wave converter, 25: Voltage controlled oscillator, 26 Bifurcater, 21
1, 211', 212, 212': Frigg 70! Circuit, 213.213', 214,214':
Nando r-) circuit. 1PJ1 Figure 2 η Figure 3, 21 511I Figure 4 (A) Figure 4 (B) 1 in m 1 m age 1 m+4,
m-1m-1-2” (2π)02°゛(2π)
(Phase difference) 1

Claims (1)

[Claims] In a phase-locked loop f circuit consisting of a phase north wall device, a low-pass P wave device, a voltage controlled oscillator, and a divider, the phase comparator is configured to generate A, G, R, and down clocks. Circuit, a!・Equipped with a down counter and dinotal to analog converter, cough up!・By temporally changing the output data of the down counter, a voltage or current t- having an average value that coincides with the phase difference at the north wall of the first phase is generated.
The phase-synchronized loop is characterized in that it is output as an output analog quantity of the digital-to-analog converter. circuit.