JPS58182436U - IC package for 3D mounting - Google Patents

IC package for 3D mounting

Info

Publication number
JPS58182436U
JPS58182436U JP7963782U JP7963782U JPS58182436U JP S58182436 U JPS58182436 U JP S58182436U JP 7963782 U JP7963782 U JP 7963782U JP 7963782 U JP7963782 U JP 7963782U JP S58182436 U JPS58182436 U JP S58182436U
Authority
JP
Japan
Prior art keywords
package
mounting
recorded
dimensional mounting
dimensionally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7963782U
Other languages
Japanese (ja)
Inventor
角田 眞治
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to JP7963782U priority Critical patent/JPS58182436U/en
Publication of JPS58182436U publication Critical patent/JPS58182436U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a、 b、 cは従来のICパッケージの平面図
、正面図、側面図、第2図a、  b、  cは本考案
のICパッケージの平面図、正面図、側面図、−第3図
は本考案による立体実装の一実施例、第4図は本考案に
よる基板積層の立体実装の実施例、第5図は本考案の接
続用ピンの一実施例である。 1・・・ICパッケージ、2.3・・・接続用ピン、4
・・・ソケット、5・・・基板。
Figures 1 a, b, and c are a plan view, front view, and side view of a conventional IC package; Figures 2 a, b, and c are a plan view, front view, and side view of an IC package of the present invention; The figure shows an example of three-dimensional mounting according to the present invention, FIG. 4 shows an example of three-dimensional mounting of board stacking according to the present invention, and FIG. 5 shows an example of a connecting pin according to the present invention. 1...IC package, 2.3...Connection pin, 4
... Socket, 5... Board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一 、 ICパッケージの上下2方向に接続用ピンをと
り出すことにより複数のICパッケージを立体的に実装
できることを特徴とする3次元実装用ICパッケージ。
1. An IC package for three-dimensional mounting, characterized in that a plurality of IC packages can be mounted three-dimensionally by taking out connection pins in two directions, top and bottom of the IC package.
JP7963782U 1982-05-29 1982-05-29 IC package for 3D mounting Pending JPS58182436U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7963782U JPS58182436U (en) 1982-05-29 1982-05-29 IC package for 3D mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7963782U JPS58182436U (en) 1982-05-29 1982-05-29 IC package for 3D mounting

Publications (1)

Publication Number Publication Date
JPS58182436U true JPS58182436U (en) 1983-12-05

Family

ID=30088815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7963782U Pending JPS58182436U (en) 1982-05-29 1982-05-29 IC package for 3D mounting

Country Status (1)

Country Link
JP (1) JPS58182436U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60200559A (en) * 1984-03-26 1985-10-11 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60200559A (en) * 1984-03-26 1985-10-11 Hitachi Ltd Semiconductor device

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