JPS58182113A - Signal correcting device - Google Patents

Abstract

PURPOSE:To reduce noise generation when an error can not be detected by controlling selective switching between a flag or a muting command signal for allowing a correcting circuit to make an adequate correction according to the length of a detected burst. CONSTITUTION:When a burst error having length greater than preset length is detected by a burst length detecting circuit 21, a control circuit 23 outputs a flag 25 of every code block while corresponding data is inputted to the correcting circuit 12; when the burst length is greater than it, the detecting circuit performs the same operation that it performs when no burst error is contained. Further, when the burst length detecting circuit 21 detects a burst error exceeding the other length preset to a greater value, a control circuit 23 outputs a muting command signal 26 while the corresponding data is inputted to the correcting circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal correction device, and includes PCM (Pu1s
eCode Modulation-Pulse code modulation)
The present invention relates to a signal correction device for decoding digital signals such as audio signals.

In general, the one shown in FIG. 1 is known as a conventional signal correction device of this type for correcting data whose errors cannot be corrected in a decoding circuit of a PCM recording/reproducing device or the like. Figure #41 is a block configuration diagram showing a conventional signal correction device. In FIG. 1, reference numeral 2 denotes a decoding circuit (t
), 5 is a dinterleave circuit that inputs the output of the decoding circuit (■) 2, performs dinterleaving, and outputs decoded first data 6 and flag 7; 8 inputs the output of the dinterleave circuit 5 and a decoding circuit (II) 12 which outputs decoded data 9, a flag 10, and a muting command signal 11.
inputs the output of decoding circuit (It) 8 and corrects data 1
This is a correction circuit that outputs 3.

Next, the operation shown in FIG. 1 will be explained. The reproduced data 1 containing an error is decoded by a decoding circuit (i) 2, the error is corrected and detected, and a flag 4 is added to the decoded data 3 and the data in which the error has been detected and output.

The dinterleaving circuit 5 performs dinterleaving on the output of the decoding circuit (I) 2, and outputs decoded data 6 and a flag 7. The output of the dinterleave circuit 5 is sent to a decoding circuit (
1) 8 is decoded, errors are corrected and detected, and the decoded data 9, the flag 10 added to the data in which an error that could not be corrected was detected, and the data in which an error that could not be corrected was detected are set in advance. A muting command signal 11 is output when the value exceeds the value set. Correction circuit 12
Then, if the immediately preceding decoded data and the immediately following decoded data do not have flags attached, the decoded data 9 to which flag 10 has been added is corrected by replacing it with the average value of the preceding and succeeding decoded data, and the immediately following decoded data is flagged. is added, a correction is made to replace the previous correction data, and when a muting command signal 11 is input, a correction is made to replace the decoded data with 0.

Examples of the above kyphosis data and correction data are shown in FIGS. 2 and 3. Figure 2 (a) shows whether the decoded data is all correct; Figure 2 (bl) contains flagged decoded data; i2 (C) shows flagged decoded data and errors cannot be detected. It is a viscosity diagram showing the relationship between each level and time T in the case of including decoded data.In this characteristic diagram, 0...correct data, ×...
・Display detected error data, Δ...missed error data, respectively.

As mentioned above, when the error rate of reproduced data is high, burst errors that are longer than the delayed arrival of dinterleaving can easily occur.

In addition, FIG. 3(a) is a signal waveform diagram of correct correction data,
Figure 3(b) shows a signal waveform diagram of correction data when the error rate of reproduced data is high, and Figure 3(C) shows a signal waveform diagram of correction data when muting is applied to reproduced data. .

Conventional signal correction devices are configured as described above, so when a long burst error occurs, there is a large amount of decoded data in which the error cannot be detected, and when an error cannot be detected or there is little correct decoded data. As shown in FIG. 3 (bl) above, this has the disadvantage that it generates a lot of pulse-like noise with a relatively high frequency, and that the noise is easily perceived by the auditory sense.

The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and is a signal correction device for correcting data whose errors cannot be corrected by the reproduced data decoding circuit.
A burst length detection circuit that detects the burst length of the reproduced data; and selective switching control of a flag or a muting command signal that provides appropriate correction to the correction circuit according to the burst length detected by the burst length detection circuit. It is an object of the present invention to provide a signal correction device which has a configuration including a control circuit capable of detecting an error, reduces noise generation when an error cannot be detected, and makes noise less perceptible to the auditory sense.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a block configuration diagram showing a signal correction device which is a simple embodiment of the present invention, and the same parts as in FIG. 1 are indicated using the same symbols. In addition to the decoding circuit (1) in the figure, the decoding circuit (1) outputs a flag 20 for all detected errors. In addition to the decoding circuit (■) 8 in FIG. 5 is a circuit similar to the dinterleave circuit 5 in FIG. 1, and 12 is a circuit similar to the correction circuit 12 in FIG. 1 except that the output of the control circuit 23 is input. It is. 21 is a burst length detection circuit which inputs the flag 20 and outputs burst length data 22; 23 inputs the 7 lag 10, the muting command signal 11 and the block clock 24, and outputs the flag 25 and the muting command signal 26; This is a control circuit that outputs.

FIG. 5 is a block configuration diagram showing a specific example of the internal configuration of the burst length detection circuit 21 and control circuit 23 shown in FIG. 4 above. In FIG. 5, 27 is a flag presence detection circuit which takes the flag 20 as an input and outputs a flag presence pulse 29, 28 a flag absence detection circuit which takes the flag 20 as an input and outputs a flag absence pulse 30, and 31 a flag presence detection circuit. Pulse 29 with flag is used as count clock input, pulse 30 without flag is used as reset input, and burst length data 2
2 is a counter circuit with output, 32 is a delay circuit with burst length data 22 as input and burst length data 33 as output, 34 is a latch circuit with block clock 24 as latch clock input, burst length data 33 as data input, A latch circuit outputs burst length data 35 as an output, 38 is a constant 3fi, 37 is a constant generation circuit as an output, 39 is a burst length data 3 as a latch output
5 and a constant 36 as inputs, and outputs a comparator output 41. 40 is a digital comparator circuit that receives burst length data 35 as a latch output and a constant 37 and outputs a comparator output 42. 43 is a flag. 10 and a comparator output 41 as inputs, and outputs a flag 25 as an output; 44 is a gate circuit that receives the muting command signal 11 and a comparator output 42 as inputs, and outputs a muting command signal 26 as an output. .

Next, the operations shown in FIGS. 4 and 5 in section -h will be explained. First, in the signal correction device shown in FIG. 4, if the reproduced data l does not include a burst error, the control circuit 23 directly uses the input flag 10 and muting command signal 11 as a flag 25 and muting command signal 26. Output. Therefore, when the conservative length detection circuit 21 detects a burst error with a length longer than a preset length,
During the period when the corresponding data enters the correction circuit 12, the control circuit 2
3 outputs 7 lags 25 in code block units, and when the burst length is less than that, the same operation as when no burst error is included is performed. Then, another burst error longer than the above length, which is preset to a longer value,
When the burst length detection circuit 21 detects this, the control circuit 23 outputs the muting command signal 26 while the corresponding data enters the correction circuit 12. Next, in FIG. 5, if there is an error-detected flag 20, flag presence pulses 29 are counted by a counter circuit 31,
If there is no flag 20, the counter circuit 31 is reset by the flagless pulse 30, and the counter output of the counter circuit 31 becomes the burst length data 22. Delay circuit 3
2 is a circuit for synchronizing the data delay caused by the dinterleave circuit 5 and the consistency circuit (■) 8 shown in FIG. 4, and synchronized burst length data 3.
Outputs 3. This burst length data 33 is latched by a latch circuit 34 for each block period, and burst length data 35 for each code block is output.

The constant generating circuit 38 sets the noise east length for switching the above-mentioned correction, and has a threshold value 36 for switching between correction in units of one data and correction in units of blocks, and correction in units of blocks and correction by muting. A threshold value 37 for switching is generated. The controller output 41 is output from the digital comparator circuit 39 when the burst length data 35 is greater than the threshold value 36, and at this time, the flag 25 in code block units is output from the gate circuit 43. Comparator output 42 outputs burst length data 3 from 1 subvalue 37.
When 5 is large, the digital comparator circuit 40 outputs, and at this time, the gate circuit 44 outputs the muting command signal 26.

FIG. 6 is a signal waveform diagram comparing the present invention and a conventional example with respect to an example of the correction data 13 from the correction circuit 12. Fig. 6(a) shows the correct correction data, Fig. 6(d) shows the signal waveform of the corrected data by the signal correction device of the present invention shown in Fig. 4, and Fig. 6(C) shows the corrected data subjected to muting. FIG. 4 is a signal waveform diagram of correction data in the case of FIG. Figure 6 above (
In b), there are many pulse-like noises with relatively high frequency components that are easy to perceive as noise in the auditory room due to undetected errors and small amount of correct data, but in Fig. 6(d), , there is almost no noise generated due to undetected errors, and the frequency component of the noise is relatively low.
It has been shown that auditory room noise is less perceptible.

In addition, although the case with 21 decoding circuits was explained in the said Example, the number of decoding circuits may be one etc., and the same effect as the said Example is produced. Further, in the above embodiment, the burst length is detected using a flag of the decoding circuit, but this may be directly detected from the level of the reproduced signal, etc., and the same effect as in the above embodiment can be obtained.

As described above, the signal correction device according to the present invention includes a burst length detection circuit that detects the burst length of reproduced data, and an appropriate correction circuit that controls the correction circuit according to the burst length detected by the burst length detection circuit. Since the configuration is equipped with a control circuit that can selectively switch and control the correction flag or the muting command signal, it is possible to minimize the noise caused by missed errors in response to burst errors, and to reduce noise in the auditory room. This provides the excellent effect of easily and reliably performing corrections that are less perceptible to noise.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing a conventional signal correction device; FIG. 2 is a diagram showing various characteristics showing the relationship between level and time in decoded data of the signal correction device shown in FIG. 1; Figure 3 (al = (b), (c)
are various signal waveform diagrams showing the correction data of the signal correction device shown in FIG. 1, FIG. 4 is a block diagram showing the signal correction device which is an embodiment of the present invention, and FIG. Block configuration diagram showing a specific example of internal configuration of a detection circuit and a control circuit, FIG. 6(a) = (b) v (d)
-(c) is 2...Decoding circuit (1), 5...
・・・・・・−・Dinterleave circuit, 8−, −, −・
Decoding circuit (II), 12...- Correction circuit, 2
1...--Burst length detection circuit, 23--Control circuit, 27 ・=--7 Lag detection circuit, 28...
--- No flag detection circuit, 31 --- Counter circuit, 32 --- Delay circuit, 34--
- Latch circuit, 38...- Constant generation circuit, 39.
40...--Digital comparator circuit, 43,
44--Gate circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3 Figure 4 Continued from page 10 Inventor Masayuki Ishida0 Inventor Naruyuki Kawarabayashi 325 Kamimachiya, Kamakura City Mitsubishi Electric Corporation Information and Electronics Research Laboratory 0 inventors: Toru Inoue, Mitsubishi Electric Corporation Information and Electronics Research Laboratories, 325 Kamimachiya, Kamakura City 0 inventors: Yasuo Sugiyama, Mitsubishi Electric Corporation Information and Electronics Research Laboratories, 325 Kamimachiya, Kamakura City

Claims (1)

[Claims] In a signal correction device for correcting data whose error cannot be corrected by a reproduction data decoding circuit, a burst length detection circuit detects a burst length of the reproduction data, and a burst length detection circuit detects a burst length of the reproduction data; , and a control circuit capable of selectively switching and controlling a flag or a muting command signal that provides appropriate correction to the correction circuit.