JPS58178633A - Programmable counter - Google Patents

Abstract

PURPOSE:To prevent malfunction by suppressing the operation of a means to generate a preset signal obtained by decoding an output from a counter during the presetting of the counter. CONSTITUTION:A ripple carrier type programmable counter consisting of FF f1-f8 executes its counting operation by an input signal fIN, and when the counted value reaches a prescribed value, sends a signal X2 to a shift register F9. The shift register F9 delays the signal X2 by a prescribed time, sends a signal Y2 to a Prn among the Pr terminals of the FF f1-f8 and sets up the data of terminals D1-D8. Since the signal X2 is obtained by connecting OR circuits G6, G7, G8 and an NOR circuit G9 as shown in the figure in this invention, the signal X2 is not outputted during the output of the signal Y2, preventing the malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmer counter whose frequency division ratio can be arbitrarily set by an external program.

There are two types of programmer counters: one is a synchronous type in which all flip-flops that make up the counter operate with the same clock pulse, and the other is a ripple-type counter in which the latter stage operates using the output of the previous stage as a clock. .

When comparing the two, the latter has a smaller number of elements, and the former requires all free-lag flops to operate at the input frequency, whereas the latter requires only the first stage to operate at the highest frequency. , the operating frequency of subsequent stages will be reduced, so in order to carry out an effective design, taking into account the required performance of the element,
The latter is used in LSI (large scale integrated circuit).

Figure 1 shows the Ripple Car one-loaf type programmer that is currently commonly used! It is a block diagram of Lucau/R. In this FIG. 1, fl-f8 is a flip flora which constitutes a binary counter! (hereinafter referred to as FF), D
I to D8 are data input terminals for presetting Ffl-rB. Data input terminals D1 to D8, respectively.
4, which is preset according to the given data.

Next, an outline of the operation of this circuit will be explained. Input signal IN
is counted down (divided), and the output of FP becomes O1.
= “O”, 02-r OJ, 03-rlJ, 04=05
=06-08-rOJ, that is, [4] in decimal, the output of ff-)G4 becomes rHJ level.

This detection signal is delayed by 3 bits by a 7-ftreno star F9 that operates in synchronization with the input signal, and is applied to the h terminals of #'Ffl to f8 as preset signals. This moment ffck? F
El-f 8 Presets the data signal input to the data input terminal DI-DB.

After the preset is completed, the 09 output of the shift register F9 is inverted to the "o" level, and the counter continues counting again with the input signal fIN.

g l Figure OF'F In the [4] detection circuit of f1 to f8, the four f-) Gl to G40 are used.
This is due to the following reasons. Multistage input f-) cannot be used because it increases the propagation delay time from the input to the output, resulting in a decrease in the frequency of the input signal fIN.

9, the output of Unkakunta;-do is the top pick) (O
S) Rounding that changes sequentially to "o" level, [4]
It is necessary to configure the circuit so that the detection delay of FF is determined not by the 08 signal of FF f8, but only by the lower pitch (01 signal of 1'f'fl) K.

For this reason, the detection circuit [4] passes through G2, G3, and G4, but the upper pitch (08) passes through G2, G3, and G4, but the lower pitch)
When (01) is configured through only r-)G4, it becomes .

Note that Vl in FIG. 1 is the output signal of r-G2, and Wl is the output signal of R-G3.

FIG. 2 is a timing chart showing the operation of this program counter in the case of the program value [132]. Fig. 2 (- indicates the input signal flN, Fig. 2(b) to Fig. 2(i) show the output signals of the output terminals 01 to 08 of FF fl to f8, respectively, and Fig. 2(j) r
- Output signal Xi of gate G4, ■ in Figure 2 is shift register F
9 shows the output signal Y1.

Note that Pr in FIG. 2 (roll) is a grisset section.

In a ripple carry one-way programmable counter, the i? Since F operates, when the input frequency of the input signal flN is high, it is affected by the input/output transmission delay time of each 11'F, and the timing chart of FIG. 2 becomes as shown in FIG. 3. Figure 3 (tortoise) is input signal fIN.
1) is each i? Output terminals 01 to 08 of Ffl-f8
is the output signal of 30) is the output signal V1. of f-) G2. What about figure 3 (goods)? -) G3 output signal Wl, Figure 3 (1) shows r-IO2 output signal X11.
Figure (c) shows the output signal Y1 of the shift register F9.

When detecting [4], the data signals of data input terminals Di to D8 are [:132] (01=rOJ, 02=rO
J, 03=rl J, 04=05=06-07-rOJ
, os-rxJ), output signal Y1 (grisset signal)
Immediately after the rHJ level and Natsu9, f-)G2. Due to delays due to wiring capacitance between G3 and upper bits], the third
A signal indicated by 2 on the output signal XI (4 detection signals) in FIG. A will be generated.

When the input signal flN rises while these two signals are at the "H" level, the output signal Yl of the shift register F9, that is, the preset signal Yl, is output to the preset/mother system in addition to the normal preseraton system h. Pr' will be generated. Therefore, the count value is also (132
), I ended up counting 3 counts too many times and ended up with a miscount (135).

This phenomenon occurs when the number of bits of the programmable counter increases, or in the case of FIG. 1, it occurs at (36) and (68) as well as at (132).

This invention eliminates the above-mentioned drawbacks of the Ripple Charging type, and provides a Glogrammer that can achieve a maximum operating frequency that is almost the same as that of the synchronous type at any program value! The purpose is to obtain a counter.

Hereinafter, embodiments of the programmable counter of the present invention will be explained based on the drawings. This invention employs a method of prohibiting the four detection circuits during the period in which the preset signal is generated.

Although this invention can be used in the same way whether the programmable counter performs a down-count operation or an up-count operation, only the case of a down-count operation will be described here.
For the detection value in the case of up-counting operation, the three bits from the least significant bit should be (110)).

FIG. 4 shows a block diagram of a first embodiment of the present invention. In this FIG. 4, the signal input terminal fINijFF
It is connected to the CP1 input terminal of fl and the CP input terminal of shift register F9. The 01 output terminal of P'Ffl is E
f' to 'f2's CP2 input terminal and 3-man power N0Rr-)G
The 02 output terminal of F'F f2 is connected to the CP3 input terminal of FF f3, and the 0Rf-
) is connected to the first input terminal of G8, and the 03 output terminal of FFf3 is connected to the second input terminal of OR gate 08 through the CP4 input terminal of FFf4 and the inverter G5.

)"The 04 output layer of Ff4 is connected to the CP5 input terminal of FFf5 and the first input terminal of 0Rf-)G7.
F'fl)05 output terminal FiM'P' f6(DCP6
It is connected to the input terminal and the second input terminal of 0Rr-toG7.

06 output terminal of FFf6 iiE' is connected to the CP7 input terminal of Ff7 and the first input terminal of the three-man OR gate G6,
The 07 output terminal of FFf7 is connected to the CP8 input terminal of FF8 and the second input terminal of OR gate G6, and the 08 output terminal of FFf8 is connected to the third input terminal of 0Re-to G6.

Also,! The data input terminal DI-D8 that inputs the reset data signal is the preset data input terminal KIi! of FFfl to FFf8, respectively. I have been threaded.

The output terminal of the above OR goo) G6 is connected to the third input terminal of OR goo) G7, and the output terminal of OR goo) G7 is O
The output terminal of N0In''-)G9 is connected to the third input terminal of G9, and the output terminal of N0Rr-)G9 is the input terminal of 3-bit shift register F9. IN, and the output terminal 09 of the shift register F9 is connected to the preset input terminals Prl to Pr8 of pFfl-FFf8 and N0Rff-G.
9 is connected to the first input terminal. In addition, U2 is OR
2 is the output signal of 0Rr-)G7, X2 is the output signal of N0Rf-)G9, Y2 is the output signal of shift register F9, and W2 is the output signal of 0Rr-)G8.

In addition, FIG. 5 is a timing chart showing operation waveforms of each part of the block diagram in FIG.
8 indicates the same part as the symbol in FIG. Fig. 5(h)) shows the input signal fINs Fig. 5(g)) to 5(0) show the output signals of the O1 output terminal to 08 output terminal of FFfl to FF f8, respectively, and Fig. 5(0) shows the output signal of 0Rr- The output signal of G6 (5th fixed rotation) is 0Rr - the output signal of G7, Figure 5 (1) is the output signal of ORG8, Figure 5 - is N
The fifth drawing shows the output signals of the shift register l'9, respectively.

The timing chart in FIG. 5 is for the case where the Grogkum data in FIG. 4 is (132).

FF fi to FF f8 are sicated down by the error signal input to the input terminal to which the input signal fIN is input, and the inverter G5. OR gate 06~G8,
The output of NOROR gate G9J) FFfl~f8 is [4
] is detected and *oRrOR gate G9d
rHJ level.

This [4] detection signal is delayed by 3 bits by shift register F9, and its output signal Y2 is, ! Reset signal Y2 and J) When presetting the code signal set to the data input terminals D1 to D8 to FF fl - FF f8, the KNOR Dart G90 input terminal is input at the same time, so the output of the NOR Dart 9 is forced. The signal is set to rLJ level.

Therefore, even if the reset data is (132), the detection error of 4 due to the transmission delay (OR delay) of the rHJ level of the most significant bit (due to G6 to G8) will not occur.
The preset data (132) is normally preset to FFfl to f8, and after the preset signal is released, the countdown operation starts.

Therefore, as is clear from FIGS. 4 and 5, even if the preset counters are connected in multiple stages and whatever program value is set, malfunctions due to the transmission delay of the detection circuit 4 from the upper bits will not occur. without input signal fI
The maximum operating frequency of N can be improved.

In addition to [4], there are also (2) and (8) as detected values.

[12], . . . etc. are also conceivable, but it is sufficient to prohibit the detection circuit by using a reset signal in the same way as described above.

In the above explanation, the delay between the preset signal and the detection circuit section [4] has been described, but when the number of stages of the grammatical pull counter increases, the following points also need to be taken into consideration.

Reduction in total current consumption, reduction in middle turn area, and
Due to reasons such as the low input frequency of the upper bits, when the circuit shown in Figure 4 is actually integrated into an IC, the lower bits (FFf)
1) to the upper bit (FF f8), the arm turn becomes smaller.

Konoto! When the frequency of the human input signal fIN is high, the upper pitch (FFf8)K is sufficient because the input signal fIN has only the middle interval of the input signal fIN. There is no time to reset.

Further, even if preset is performed, one phase of the detection circuit [4] will be delayed, and there may be cases where the detection circuit [4] is not inhibited sufficiently.

Therefore, the rHJ section of the preset pulse is changed to the input signal f.
iN12) The maximum operating frequency does not change even if the current consumption and lC/4 tandem area are reduced, as the current consumption increases and the current consumption and lC/4 tandem area decrease (IC (The rate of non-defective products will be improved if this is done.) A program 2 mapple counter can be configured.

FIG. 6 shows a partial block diagram of this as a second embodiment. This FIG. 6 is a circuit diagram in the case where the aforementioned brisset noisys is set for 2 geneross intervals of the input signal fIN.

In Fig. 4, a simple 3-bit shift register F9 is used, but in Fig. 6, a 3-bit shift register and a two-man QRf are used.
-) will be configured by GIO. That is, X
2 is the output signal line of N0Rf-G9 in FIG.
This is connected to the D1 input terminal of the first shift register 81, the Ql output terminal of the first shift register S1 is connected to the D2 input terminal of the second shift register S2 in the next stage, and the Q2 output terminal of the second shift register S2. is the D3 input terminal of the third shift resistor S3 in the next stage and the OR gate) GIO
The Q3 output terminal of the third shift resistor S3 is connected to the second input terminal of 0Rf-)GIO. First to third shift reno stars 81 to S
3 clock input terminal CP9. CPIO and CPII all receive the input signal flN, and the output terminal of GI (OR) is connected to the Pn to Pnjll children of FFf1 to FFf8 and the first input terminal of NOI''-G9. The output signal of O is assumed to be Y3.)

FIG. 7 shows a timing chart of a programmable color system in which the preset signal generating circuit configured as described above is used in place of the shift resolution F9 shown in FIG. FIG. 7(1) shows the input signal fIN, and FIG. 7(b)
~Figure 7 (L) is I? The output signals from the O1 output terminal to the 08 output terminal of F fl-FF f8 are shown, and O) in Fig. 7 is O.
R) The output signal of G6, Fig. 7 (k) is OFt? '−
G7c) Output signal, Figure 7 (1) is 0Rff-G8
FIG. 7) shows the output signal of the OR gate G7, and FIG. 7 (b) shows the output signal of the OR gate GIO.

The rHJ interval of the output signal Y3 (grid reset signal) in FIG. 7(n) of the timing chart is twice the rHJ interval of the output signal Y2 (the reset signal). It is easy to preset the FF f8), and the effective time t due to the set-up time delay for the preset and 4 pulses of the upper FF f8 and the f7) delay time of the detection circuit 4 is doubled. I can see that it will be improved.

This is because the number of pulses of the input signal fIN is taken as 2 pulses of the input signal fIN.
It is clear that this is a two-fold improvement.

In addition, in addition to [4], the detection value of the down counter may be (2], (8), (12), etc.
As is clear from the above explanation, widening the preset pulse width improves the effective time t due to the reset up time of the FF in the detection circuit. ), 7 stages (when detecting 8), and 11 stages (when detecting 12), the input signal fIN
Due to the increase in FFs that must operate at the frequency of
[4] or [2] is suitable as the detection value, and [4] is optimal because of the increase in the IC's rotational product, the increase in current consumption, and the limitation on the minimum number of programs that can be divided. .

As explained above, according to the programmable counter of the invention No. 1, an input signal is counted by a plurality of stages of preset counters, and when the combination code of the output of this preset counter becomes a predetermined code, a preset signal is generated, This preset signal is delayed by a predetermined number of bits to preset all preset counters, and the generation of a combination code of the output of the preset counter is prohibited while the preset signal is output from the delay means, thereby reducing power consumption. It is possible to construct a high-speed counter that enables electric power generation, miniaturization of the area, and high product yield, so it can be used in PLL circuits for televisions, laptops, etc.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional programmable counter, Figures 2 (a) to 2 (goods) and Figure 3 (&
) to 3(b) are operation waveform diagrams of each part of the programmable counter shown in FIG. 1, FIG. 4 is a block diagram showing an embodiment of the programmable counter of the present invention, and FIGS. Figure (6) is an operation waveform diagram of each part of the programmable counter of Figure 4, Figure 6 is a diagram of the delay means in the second embodiment of the programmable counter of the present invention, and Figure 7 (a). 7) are operation waveform diagrams of each part of the block in FIG. 6. D1-D8...Data input terminal, f1-f8...Flitno flop, F9...Shift register, G5...
・Inverter, 06~G8. GIO...OR dirt,
G9-N ORf-to, S1-...first shift register, S2...second shift register, S3...third
shift register. Patent Applicant Oki Electric Industry Co., Ltd. Figure 5 P "Figure 7 Procedural Amendment September-3, 1980 Mr. Kazuo Chikusugi, Commissioner of the Japan Patent Office, Indication of Case 1982 Patent Application No. 608752 Invention Name Programmer's Counter 3, Relationship with the case of the person making the amendment Patent Applicant (02G) Oki Electric Industry Co., Ltd. 4 Agent 5 Date of amendment order Showa Year Month Day (Spontaneous) 6 Subject of amendment @ Specifications As per the appendix for the scope of claims and detailed description of the invention, as well as part 7 of the content of the amendment, 1) 12% permitted scope of the specification is to be corrected in the appendix. 2) Ming 111thI413 Sada 15th line fINJtffIN
Correct it with J. 3) Delete all lines 7 and 18 of the same 3 Jijl [O-base number]. 4) Same page 10, line 12 rFFf-FFf8Jt” [FFf
Correct it to l-FFf8J. 5) Delete all of page 15, line 12, 1f. 86) Page 16a.
Correct line 13, 1^, to read ``Good quality'' 1c, ``High quality item.'' 7) Correct the drawings as shown in the attached sheets of Figures 3, 8g5, and 7. 2 Special IF! F Claims (1) Preset counters from the first stage to the nth stage connected in series for counting human input signals, and when the combination code of the output of this preset counter becomes a predetermined code, the preset signal is output. the preset signal generating means to generate, and the preset number b delayed by a predetermined number of pits and input to all stages of the preset counter to preset the preset counter to a predetermined code, and to preset the preset counter. and a delay circuit that completely inhibits the operation of the preset signal generating means during the preset signal generation means. (2) The preset signal generating means is Jigl or jg.
The output code of the 3-stage grisset counter is [001
) or [OIO], the programmable counter is characterized in that it generates a preset signal as a t% signal. (3) The output code of the first to third preset counters is [001] or [001] or [
:110] t- When detected, the delay circuit causes the first stage grise counter to detect 1 to 3 of the input signal period.
The programmable counter according to claim 1, wherein the programmable counter outputs a preset signal having twice the pulse width. Figure 5 Figure 7

Claims (1)

[Claims] (1) When the combination code of the first to nth stages of preset counters connected in series for rounding that counts input signals and the output of this preset counter becomes a predetermined code, the preset A preset signal generating means for generating a signal, and a preset signal generating means for delaying the reset signal by a predetermined number of bits and inputting the delayed signal to all stages of the preset counter to preset the preset counter to a predetermined code. A programmer no counter comprising a delay circuit for inhibiting the operation of the reset signal generating means while the preset counter is being preset. (21f IJ upper set number generation means are the first to third
The output code of the above-mentioned reset counter of the stage is (0011
2. The programmer sol counter according to claim 1, wherein the programmer sol counter enters a prohibited state when the value becomes 010 or (010). (3) 7"!J upper set number generation means is the first to jlI
The output code of the above preset counter in 3 is [001]
or (11G), the delay circuit outputs a grisset signal having a pulse width of 1 to 3 times the period of the input signal at the first stage preset counter. The programmer sol counter described in item 1.