JPH11308281A - Digital signal transmitter and its method, digital signal transmitter and digital signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal transmitter capable of reducing power consumption in sending a digital signal. SOLUTION: An encoder 39 generates a digital signal T1 whose lever is switched between 1st and 2nd levels in a timing when a toggle produced in digital signals D1, D4 is detected at the same time. The encoder generates digital signals D7, D11 with the same initial state level as that of the signals D1, D4 and whose levels are switched in a timing except the detected toggle timing among toggle timings produced in the digital signals D1, D4 and gives them to a destination decoder 60 via signal transmission lines 61, 62, 63.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission device and method, a digital signal transmission device and a digital signal reception device.

[0002]

2. Description of the Related Art Generally, when a serial digital signal is transmitted, the power consumption increases if the total number of signal toggles (the number of times the digital signal level changes from 0 to 1 or from 1 to 0) is large. Noise is increased, and various adverse effects are generated from the noise. That is, when transmitting necessary information as a digital signal, it is often useful to reduce the number of toggles as much as possible. Particularly recently, CMOS (Complementary Metal-Oxide S
Semiconductor devices called semiconductors (complementary metal oxide semiconductor integrated circuits) are widely used. CM
The OS circuit has a feature that when the digital signal is in a steady state (when the signal level is stable at 0 or 1), almost no power is consumed. In other words, power is consumed when the signal toggles (the digital signal level changes from 0 to 1 or 1 to 0). Generally, power consumption increases in proportion to the number of toggles and electrostatic capacity.

Usually, when transmitting a plurality of digital signals, given signal information (signal level is 0 or 1) is continuously transmitted. Here, FIGS. 7A and 7B
Consider two digital signals “D1” and “D4” shown in FIG. Signals “D1” and “D4” shown in FIGS. 7A and 7B are 0, 1, and 0 in x, y, s, and z, respectively.
When 0 and 1 are assigned, they are represented as shown in FIGS. 8A and 8B. Note that y is an inverted value of x, and z is an inverted value of s. In FIG. 8A, the time when the level changes from x to y and the time when the level changes from y to x are each “toggle”.
Becomes In FIG. 8B, the time when the level changes from s to z and the time when the level changes from z to s are each “toggle”.
Becomes

[0004] Digital signals "D1" and "D4" as shown in FIG. 8 are transmitted using, for example, a digital signal transmission circuit 1 as shown in FIG. In FIG. 9, 1
Reference numerals 1, 12, 13, and 14 denote CMOS buffers which output the same digital signals as the digital signals input from the left side in the figure from the right side. Reference numerals 15 and 17 denote electrostatic capacities.
Reference numerals 6 and 18 denote ground potentials. Here, the electrostatic capacitance 15,
Numeral 17 is always present in the electric circuit, and its amount and size are determined by the electrostatic capacity of the CMOS buffers 11, 12, 13, and 14 themselves, between the CMOS buffers 11, 12 and between the CMOS buffers 13, 14. Is determined by the physical distance and material of the

When transmitting the digital signal “1” “1”, the CMOS buffer 11 and the electrostatic capacitance 15
Is charged, the level of the digital signal “D2” being transmitted is set to “1”, whereby the level of the output terminal of the CMOS buffer 12 of the transmission destination is set to “1”. As a result, the level of the digital signal “D3” output from the output terminal of the CMOS buffer 12 changes to the level of the digital signal “D1”.
Becomes “1” in response to

When transmitting the digital signal “D1” “0”, the CMOS buffer 11 and the electrostatic capacitance 15
Is discharged from the side of the ground potential 16 of the electrostatic capacitance 17 to set the level of the digital signal “D2” during transmission to “0”, whereby the level of the output terminal of the CMOS buffer 12 of the transmission destination is set. To “0”. As a result, the level of the digital signal “D3” output from the output terminal of the CMOS buffer 12 changes to the level of the digital signal “D1”.
It becomes "0" according to.

The digital signal transmission circuit 1 changes the level of the digital signal "D1" by repeating the charging and discharging of the CMOS buffer 11 and the electrostatic capacitance 15 according to the level of the digital signal "D1". This is reflected on the level of “D2” and the digital signal “D3”. On the other hand, as for the digital signal “D4”, similarly to the digital signal “D1”, the digital signal “D4” is generated by the CMOS buffer 13 and the electrostatic capacitance 17.
The digital signal “D6” corresponding to the digital signal “D4” is finally output from the output terminal of the CMOS buffer 14 by reflecting the level “4” on the digital signal “D5”.

In the digital signal transmission circuit 1 shown in FIG. 9 as described above, while the levels of the digital signals "D1" and "D4" are "0" or "1" and are in a steady state, Consumes little power. That is,
The digital signal transmission circuit 1 consumes power when a toggle occurs, and the power consumption is proportional to the number of toggles per unit time and the size of the electrostatic capacitances 15 and 17. In other words, the greater the number of toggles per unit time, the more the electrostatic capacity 15,1
The larger the electrostatic capacity of No. 7, the higher the power consumption.

[0009]

However, in the above-mentioned conventional digital signal transmission circuit 1, the digital signals "D1" and "D4" are transmitted as they are from the transmission source to the transmission destination via the signal transmission line. Therefore, there is a problem that the total number of toggles per unit time increases and power consumption increases.

The present invention has been made in view of the above-mentioned problems of the prior art, and provides a digital signal transmitting apparatus and method, a digital signal transmitting apparatus, and a digital signal receiving apparatus capable of reducing power consumption when transmitting a digital signal. The purpose is to:

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, a digital signal transmission apparatus according to the present invention comprises a digital signal transmission apparatus for transmitting a plurality of digital signals in parallel. An apparatus, comprising: a toggle detecting means for detecting a toggle generated simultaneously among a plurality of first digital signals; and a switch between a first level and a second level at a timing of the toggle detected by the toggle detecting means. For each of the plurality of first digital signals,
A second digital signal having the same initial state level as the first digital signal, and switching the level at a timing excluding the toggle timing detected by the toggle detection means among the toggle timings generated in the first digital signal; Encoding means for generating a digital signal, a signal transmission line for transmitting the inversion determination signal, and the plurality of second digital signals corresponding to the plurality of first digital signals in parallel, and the signal transmission Decoding means for decoding the plurality of second digital signals received via a line based on the inversion determination signal received via the signal transmission line.

In the digital signal transmission device of the present invention, the first
Of the toggle timing that occurs in the digital signal of
At the timing of the toggle detected by the toggle detecting means, that is, the timing of the toggle occurring simultaneously among the plurality of first digital signals, the level of the inversion determination signal is switched without switching the level of the second digital signal. Therefore, the number of toggles corresponding to the number of the first digital signals is replaced with one toggle.

[0013] The digital signal transmission device of the present invention comprises:
Preferably, the inversion discrimination signal generating means sets an initial state of the inversion discrimination signal to a first level, and the decoding means, while the received inversion discrimination signal is at the first level, While the level of the second digital signal is held, and while the inversion determination signal is at the second level, a third digital signal is generated by inverting the level of the received second digital signal.

Further, the digital signal transmitting apparatus of the present invention comprises:
A digital signal transmitting apparatus for transmitting a plurality of digital signals in parallel via a signal transmission line, wherein the toggle detecting means detects a toggle generated simultaneously among a plurality of first digital signals, and the toggle detecting means comprises: An inversion determination signal generating means for generating an inversion determination signal that switches between the first level and the second level at the timing of the detected toggle;
Each of the plurality of first digital signals has the same initial state level as that of the first digital signal, and a toggle detected by the toggle detection means among the toggle timings generated in the first digital signal. Encoding means for generating a second digital signal whose level has been switched at a timing other than the timing of (i), the inversion discrimination signal, and a plurality of second digital signals corresponding to the plurality of first digital signals.
And an output unit for outputting the digital signal in parallel to the signal transmission line.

Further, a digital signal receiving apparatus of the present invention
A digital signal receiving apparatus for receiving a plurality of digital signals transmitted in parallel via a signal transmission line, wherein a first level and a second level are generated at a timing of a toggle generated simultaneously among the plurality of first digital signals. And an inverted discrimination signal that switches between the first and second digital signals, and has the same initial state level as that of the corresponding first digital signal. Receiving means for receiving, via the signal transmission line, a plurality of second digital signals whose levels have been switched at timings other than the timing of the above, and receiving the plurality of received second digital signals, Decoding means for decoding based on the inversion discrimination signal.

Further, the digital signal transmission method of the present invention comprises:
A digital signal transmission method for transmitting a plurality of digital signals in parallel, comprising detecting a toggle generated simultaneously among a plurality of first digital signals, and setting a first level and a second level at a timing of the detected toggle. And an inversion discrimination signal that switches between the first digital signal and the first digital signal. Each of the plurality of first digital signals has the same initial state level as the first digital signal, and a toggle generated in the first digital signal is generated. A second digital signal whose level is switched at a timing excluding the timing of the detected toggle among the timings of the above, and generates the inversion determination signal and the plurality of second digital signals corresponding to the plurality of first digital signals. Are transmitted in parallel via a signal transmission line, and the plurality of second digital signals received via the signal transmission line are transmitted through the signal transmission line. Decoding based on the inversion discrimination signal received via.

Further, in the digital signal transmission method according to the present invention, preferably, the initial state of the inversion discrimination signal is set to a first level, and the received inversion discrimination signal is received during the first level. The level of the second digital signal is held, and while the inversion determination signal is at the second level, the decoding is performed by inverting the level of the received second digital signal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital signal transmission circuit according to an embodiment of the present invention will be described below. First, the concept of the signal transmission method adopted by the digital signal transmission circuit of the present embodiment will be described. In the digital signal transmission circuit of the present embodiment, when transmitting two or more digital signals, these digital signals are code-converted according to a certain rule. FIG. 1 is a diagram for explaining a signal transmission method adopted by the digital signal transmission circuit of the present embodiment. In the present embodiment, a case where two digital signals “D1” and “D4” are transmitted will be described as an example. In the present embodiment, “x” and “s” are “0” or “1”, respectively.
Where “y” is the inverted value of “x” and “z” is the inverted value of “s”. In the digital signal transmission circuit of the present embodiment, the transmission source encoder performs code conversion on the digital signals “D1” and “D4” to be transmitted to generate digital signals “D7”, “D11” and “T1”, These are transmitted to a transmission destination via a signal transmission line.

Here, basically, the digital signal "D
"7" and "D11" are signals corresponding to the digital signals "D1" and "D4", respectively. At the start of transmission, the levels of digital signals "D7" and "D11" are equal to the levels of digital signals "D1" and "D4", respectively. The digital signal “T1” is the digital signal “D
7 ”and“ D11 ”indicate whether the corresponding timing levels are correct. The level of the digital signal "T1" at the start of normal transmission may be either "0" or "1" as long as it means that it is correct.

At the transmission destination, the received digital signal "D
7, "D11" and "T1" are decoded and converted by a decoder to obtain digital signals "D10" and "D14" corresponding to "D1" and "D4", respectively. In the present embodiment, the number of digital signals to be transmitted is three, but the total number of toggles of all signals per unit time can be smaller than the total number of toggles of all signals before conversion.

Hereinafter, a code conversion method in the transmission source encoder will be specifically described. In the code conversion method, the digital signal “D” is used in the following manner (1) to (3).
1 and D4 to digital signals D7, D1
1 "and" T1 ". (1) Generation of digital signal "D7": Digital signal "D7"
The digital signal "D7" is generated by preventing the level of "1" from changing at the position of the toggle that occurs at the same timing as the digital signal "D4" among the toggles present in the digital signal "D1". That is, the level of the digital signal "D7" is inverted only at the timing when the toggle occurs only in the digital signal "D1" and when the toggle does not occur in the digital signal "D4".

More specifically, as shown in FIG. 1, the digital signal "D1" has a digital signal "D1" and a digital signal "D4". D7 "level is not changed. Therefore, the digital signals “D7” and “D
1 ", the digital signals" D7 "and" D1 "match up to the first (first) timing C;
During the period from the first timing C to the second timing C, the digital signal “D7” is a signal obtained by inverting “D1”. Thereafter, the digital signals “D7” and “D1” match from the nth (n is an even number of 2 or more) timing C to the (n + 1) th timing C, and the (n + 1) th timing C to the (n + 2) th timing C Up to this point, the digital signal “D7” is a signal obtained by inverting “D1”.

(2) Generation of digital signal "D11": The digital signal "D11" is also generated using the digital signal "D4" in the same manner as in the above (1).

(3) Generation of digital signal "T1": Until the first (first) timing C, the digital signal "D1"
“0” indicating that “7” and “D11” are normal values
And between the first timing C and the second timing C, the digital signals “D7” and “D11”
Becomes “1” indicating that it is an inverted value of the normal value, and thereafter, from the n-th (n is an even number of 2 or more) timing C to n
It becomes "0" until the + 1st timing C, and n
From the (+1) th timing C to the (n + 2) th timing C
During this period, a digital signal “T1” that becomes “1” is generated.

That is, in the encoder at the transmission source, while the digital signal “T1” is “0”, the digital signals “D7” and “D11” correctly indicate the digital signals “D1” and “D4”, respectively. Means that the digital signals "D1" and "D11" indicate values obtained by inverting the digital signals "D1" and "D4", respectively, while the digital signal "T1" is "1". Means

Therefore, the decoder at the transmission destination refers to the digital signal “T1” and while the digital signal “T1” is “0”, the digital signals “D7” and “D1”
1 ”is used as it is, and the digital signal“ T
While “1” is “1”, a digital signal corresponding to the digital signals “D1” and “D4” can be decoded by using a level obtained by inverting the level indicated by the digital signals “D7” and “D11”.

Here, the digital signal "D1" shown in FIG.
And “D4” include nine torques included in the digital signal “D1” and ten torques included in the digital signal “D4”.
There are 19 toggles in combination with these toggles. On the other hand, the digital signals “D7” and “D1” shown in FIG.
“1” and “T1” include five toggles included in the digital signal “D7”, six toggles included in the digital signal “D11”, and 4 included in the digital signal “T1”.
There are 15 toggles in combination with these toggles. That is, according to the digital signal transmission circuit of the present embodiment,
In the case shown in FIG. 1, the total number of toggles of digital signals transmitted through the transmission path can be reduced from 19 to 15.

This is because the above-described conversion rule replaces the toggles that occur simultaneously in the digital signals “D1” and “D4”, that is, two toggles, with one toggle of the digital signal “T1”. is there. Therefore, as shown in FIG. 1, when the number of times that the toggle occurs simultaneously in the digital signals “D1” and “D4” is 4, the total number of toggles of the digital signal to be transmitted is smaller than that of the conventional digital signal transmission circuit. Can be reduced by 4. That is, the digital signal transmission circuit according to the present embodiment includes the digital signals “D1” and “D
The effect is exhibited as the number of toggles simultaneously generated in "4" increases.

Hereinafter, a specific configuration of the digital signal transmission circuit of the present embodiment will be described. FIG. 2 is a configuration diagram of the digital signal transmission circuit 30 of the present embodiment. As shown in FIG. 2, the digital signal transmission circuit 30 includes the encoder 3
9, CMOS buffers 31, 32, 33, 34, 35,
36, decoder 60 and signal transmission lines 61, 62, 63
Having. Further, between the signal transmission lines 61, 62, 63 and the ground potentials 45, 46, 47, the electrostatic capacitance 4
1, 42 and 43 have occurred. At the transmission source, the encoder 39 code-converts the digital signals "D1" and "D4" to generate digital signals "D7", "D11" and "T1", which are converted into CMOS buffers 31, 33 and 35 and a signal. Transmission is performed via transmission lines 61, 62, and 63.

In FIG. 2, digital signals "D7" and "D11" transmitted via signal transmission lines 61, 62 and 63 are shown.
And "T1" are converted to digital signals "D8",
It is represented by “D12” and “T2”. At the destination,
The digital signals "D8", "D12" and "T2" are
The digital signals are received as digital signals “D9”, “D13”, and “T3” via the OS buffers 32, 34, and 36, and are decoded and converted by the decoder 60 to correspond to the digital signals “D1” and “D4”, respectively. Digital signal “D1
0 "and" D14 ". In the present embodiment, the number of digital signals to be transmitted is three, but the total number of toggles of all signals per unit time can be smaller than the total number of toggles of all signals before conversion.

[0031] The encoder 39 FIG. 3 is a block diagram of an encoder 39. As shown in FIG. 3, the encoder 39 includes a simultaneous toggle detection module 100, a D7 and D11 generation module 101, and a T
1 generation module 102.

The coincidence toggle detection module 100 includes:
D-FFs (D-type flip-flops) 110, 111,
XOR (Exclusive OR) circuits 112 and 113 and AND
A circuit 114; A digital signal “D1” to be transmitted is applied to one input terminal of the XOR circuit 112 and the D terminal of the D-FF 110. A digital signal “D4” to be transmitted is applied to one input terminal of the XOR circuit 113 and the D terminal of the D-FF 111.

The Q terminal of the D-FF 110 is connected to the XOR circuit 1
12 is connected to the other input terminal. Also, DF
The Q terminal of F110 is connected to the D7 / D11 generation module 10
One input terminal of the AND circuit 130 is connected to one input terminal of the AND circuit 131 via the NOT circuit 134. The Q terminal of the D-FF 111 is connected to the other input terminal of the XOR circuit 113. Also, D
The Q terminal of the FF 111 is connected to one input terminal of the AND circuit 140 of the D7 and D11 generation module 101 and the NOT terminal.
The circuit 144 is connected to one input terminal of the AND circuit 141 via the circuit 144. The output terminal of the XOR circuit 112 is
It is connected to one input terminal of the AND circuit 114.
The output terminal of the XOR circuit 113 is connected to the other input terminal of the AND circuit 114. The output terminal of the AND circuit 114 is connected to the AND circuit 12 of the T1 generation module 102.
0 and one input terminal of the
It is connected to one input terminal of the D circuit 121.

In the coincidence toggle detection module 100, the level of the digital signal “D 1” and the D-FF 110 are set at the timing when the toggle occurs in the digital signal “D 1”.
And the level of the output terminal of the XOR circuit 112 becomes “1”. The digital signal “D
At the timing when the toggle occurs at “4”, the level of the digital signal “D4” and the level of the Q terminal of the D-FF 111 are different, and the level of the output terminal of the XOR circuit 113 becomes “1”. Therefore, as shown in FIGS. 4A, 4B, and 4E, at the timing when the digital signals “D1” and “D4” simultaneously toggle, the digital signal output from the output terminal of the AND circuit 114 is output. The level of the signal “K3” becomes “1”. Further, as shown in FIGS. 4A and 4C, the digital signal “K1” output from the Q terminal of the D-FF 110 is a signal obtained by delaying the digital signal “D1” by one clock cycle. FIG. 4B,
As shown in (D), the digital signal “K2” output from the Q terminal of the D-FF 110 is the digital signal “D4”
Is delayed by one clock cycle.

The T1 generation module 102 includes AND circuits 120 and 121, an OR circuit 122, a NOT circuit 124,
125 and a D-FF circuit 123. D-FF1
The Q terminal 23 is connected to the other input terminal of the AND circuit 121 and the other input terminal of the AND circuit 120 via the NOT circuit 124. One input terminal of the OR circuit 122 is connected to the output terminal of the AND circuit 120,
The other input terminal is connected to the output terminal of the AND circuit 121. The output terminal of the OR circuit 122 is connected to the D terminal of the D-FF circuit 123. Here, the level of the digital signal “K4” is determined by the levels of the digital signal “K3” and the digital signal “T1”. Specifically, as shown in FIGS. 4E, 4F, and 4I, when the digital signal “K3” is “0”, the level of the digital signal “K4” is changed to the digital signal “T1”. Level. On the other hand, when the digital signal “K3” is “1”, the level of the digital signal “K4” is obtained by inverting the level of the digital signal “T1”. The digital signal “T1” is a signal obtained by delaying the digital signal “K4” by one clock cycle.

The D7, D11 generation module 101
ND circuits 130, 131, 140, 141, OR circuit 1
32, 142 and NOT circuits 133, 134, 14
3,144. The other input terminal of the AND circuit 130 is connected to the Q-terminal of the D-FF 123 via the NOT circuit 133.
Connected to terminal. The other input terminal of the AND circuit 131 is connected to the Q terminal of the D-FF 123. A
The other input terminal of the ND circuit 140 is a NOT circuit 143
, Is connected to the Q terminal of the D-FF 123.
The other input terminal of the AND circuit 141 is a D-FF 123
Is connected to the Q terminal.

In the D7 and D11 generation module 101,
As shown in FIGS. 4C, 4G, and 4I, when the digital signal “T1” is “0”, the digital signal “D7” having the same level as the digital signal “K1” is output from the OR circuit 132. 4 (D), (H),
As shown in (I), a digital signal “D11” having the same level as the digital signal “K2” is output from the output terminal of the OR circuit 142. On the other hand, as shown in FIGS. 4C, 4G, and 4I, the D7 and D11 generation module 101 inverts the level of the digital signal “K1” when the digital signal “T1” is “1”. Digital signal “D
7 "is output from the output terminal of the OR circuit 132 and the digital signal" D2 "obtained by inverting the level of the digital signal" K2 "as shown in FIGS.
"11" is output from the output terminal of the OR circuit 142.

[0038] Decoder 60 Fig. 5 is a configuration diagram of a decoder 60 shown in FIG. The decoder 60 includes AND circuits 230, 231, 240, 24
1, OR circuits 232, 242 and NOT circuit 233,
234, 243 and 244. The signal transmission line 61
One input terminal of the AND circuit 230 and the NOT circuit 23
4 and one input terminal of the AND circuit 231. The signal transmission line 62 is connected to the AND circuit 24.
0 through one of the input terminals and a NOT circuit 244.
It is connected to one input terminal of the D circuit 241. Further, the signal transmission line 63 is connected to the
The other input terminal of the D circuit 230, the other input terminal of the AND circuit 231, the other input terminal of the AND circuit 240 via the NOT circuit 243, and the other input terminal of the AND circuit 241 are connected. .

One input terminal of the OR circuit 232 is connected to the output terminal of the AND circuit 230, and the other input terminal is connected to the output terminal of the AND circuit 231. One input terminal of the OR circuit 242 is connected to the AND circuit 24.
0 and the other input terminal is connected to the output terminal of the AND circuit 241. Here, a digital signal “D10” corresponding to the digital signal “D1” is output from the output terminal of the OR circuit 232. Further, a digital signal “D14” corresponding to the digital signal “D4” is output from the output terminal of the OR circuit 242.

In the decoder 60, FIGS. 6 (A), (C),
As shown in (D), when the digital signal “T3” is “0”, the digital signal “D10” having the same level as the digital signal “D9” is output from the output terminal of the OR circuit 232, and FIG. As shown in (B), (C), and (E), a digital signal “D14” having the same level as the digital signal “D13” is output from the output terminal of the OR circuit 242. On the other hand, in the decoder 60, FIGS.
As shown in (D), when the digital signal “T3” is “1”, the digital signal “D10” obtained by inverting the level of the digital signal “D9” is output from the output terminal of the OR circuit 132, and As shown in FIGS. 6B, 6C, and 6E, a digital signal “D14” obtained by inverting the level of the digital signal “D13” is output from the output terminal of the OR circuit 142.

Here, the digital signals "D10" and "14" shown in FIGS. 6D and 6E and the digital signals "D1" and "D4" shown in FIGS. Become the same,
It can be seen that decoding is properly performed in the decoder 60.

The digital signal transmission circuit 3 shown in FIG.
The operation of 0 will be described. For example, FIG.
The digital signals “D1” and “D4” shown in FIG.
4 (G), (H), and (I), the digital signals "D7", "D11", and "T1" are generated through the above-described processing.
Next, the digital signals “D7”, “D11”, “T1”
Are CMOS buffers 31, 33, 35, signal transmission lines 61, 62, 63 and CMOS buffer 32, respectively.
The digital signals "D9" and "D1"
3 ”and“ T3 ”are input to the decoder 60. Then, the digital signals "D9", "D13", and "T3" shown in FIGS. 6A, 6B, and 6C are respectively decoded by the decoder 60 shown in FIG. The digital signal “D1” shown in (D) and (E)
0 and D14.

As described above, according to the digital signal transmission circuit 30, the total number of toggles of the digital signal transmitted from the transmission source to the transmission destination can be reduced, and the power consumption can be reduced.
In addition, there is a corresponding increase in power consumption with the addition of the signal transmission line, but a decrease in power consumption with a reduction in the total number of toggles is larger. Normally, there is a signal transmission line which is in an unused state in time, and if it is used, it is not necessary to newly add a signal transmission line wiring. Further, according to the digital signal transmission circuit 30, as the number of toggles decreases, the influence of noise also decreases. Therefore, the operation margin is increased.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, a case where two digital signals “D1” and “D4” are transmitted has been illustrated.
The present invention is applicable when transmitting more than one digital signal. For example, n original digital signals A _{1 to} A _n
From when generating n digital signals B ₁ .about.B _n and contemporaneous toggle signal C for the transmission of the simultaneous occurrence toggle signal C at the timing when all of the digital signals A ₁ to A _n generates a toggle at the same time Switch the level of
Generating a digital signal B ₁ .about.B _n does not change the level of the digital signal A ₁ to A _n in the timing.

As described above, when the number of digital signals is large, the frequency at which toggles occur simultaneously decreases, but the number of toggles reduced when toggles occur simultaneously increases. Note that an expected value is calculated by mathematical probability theory for a completely random (irregular) digital signal. However, before performing the conversion process in the encoder 39, a synergistic effect can be obtained by combining another sign process. There is expected. For example, when a toggle occurs, it is preferable to perform processing such as simultaneous generation as much as possible before the encoder 39.

The present invention can be applied to a digital electronic circuit or a large-scale electronic / electric device communicating with a digital signal, as long as the digital signal is transmitted.

[0047]

According to the digital signal transmission apparatus and method of the present invention, the digital signal transmission apparatus and the digital signal reception apparatus, power consumption for transmitting a digital signal can be reduced. Further, according to the digital signal transmission device and method, the digital signal transmission device and the digital signal reception device of the present invention, the influence of noise is reduced with a decrease in the number of toggles. Therefore, the operation margin is increased.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a signal transmission method adopted by a digital signal transmission circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a digital signal transmission circuit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of the encoder shown in FIG. 2;

FIG. 4 is a diagram for explaining signals in the encoder shown in FIG. 2;

FIG. 5 is a configuration diagram of a decoder shown in FIG. 2;

FIG. 6 is a diagram for explaining each signal in the decoder shown in FIG. 2;

FIG. 7 is a diagram for explaining a digital signal transmitted via a signal transmission line.

FIG. 8 is a diagram mathematically expressing a digital signal transmitted via a signal transmission line.

FIG. 9 is a configuration diagram of a conventional digital signal transmission circuit.

[Explanation of symbols]

30 ... Digital signal transmission circuit, 31, 32, 33, 3
4, 35, 36 CMOS buffer, 39 encoder, 41, 42, 43 electrostatic capacity, 45, 46, 47
... ground potential, 60 ... decoder

Claims (13)

[Claims] 1. A digital signal transmitting apparatus for transmitting a plurality of digital signals in parallel, comprising: a toggle detecting means for detecting a toggle generated simultaneously among a plurality of first digital signals; and the toggle detected by the toggle detecting means. An inversion discrimination signal generating means for generating an inversion discrimination signal that switches between a first level and a second level at the timing of: a first digital signal for each of the plurality of first digital signals; A code for generating a second digital signal having the same initial state level and having its level switched at a timing other than the toggle timing detected by the toggle detection means among the toggle timings generated in the first digital signal. Means for converting the inversion discrimination signal and the plurality of second digital signals corresponding to the plurality of first digital signals. A signal transmission line to be transmitted to a column, and decoding means for decoding the plurality of second digital signals received via the signal transmission line based on the inversion determination signal received via the signal transmission line. Digital signal transmission device having. 2. A semiconductor integrated circuit having a complementary metal-insulating film between said encoding means and said signal transmission line.
3. The digital signal transmission device according to claim 1. 3. The digital signal transmission device according to claim 1, wherein a complementary metal insulating film semiconductor integrated circuit is provided between said signal transmission line and said decoding means. 4. The inversion discrimination signal generation means sets an initial state of the inversion discrimination signal to a first level, and the decoding means performs reception while the inversion discrimination signal is received at the first level. The level of the second digital signal thus obtained is held, and while the inversion determination signal is at the second level, the third level obtained by inverting the level of the received second digital signal is held.
2. The digital signal transmission device according to claim 1, wherein the digital signal transmission device generates: 5. The digital signal transmission device according to claim 1, wherein said encoding means generates said second digital signal based on said inversion discrimination signal. 6. A digital signal transmitting apparatus for transmitting a plurality of digital signals in parallel via a signal transmission line, wherein: a toggle detecting means for detecting a toggle generated simultaneously among a plurality of first digital signals; Means for generating an inversion determination signal that switches between a first level and a second level at the timing of the toggle detected by the means; and for each of the plurality of first digital signals, A second digital signal having the same initial state level as the first digital signal and having its level switched at a timing other than the toggle timing detected by the toggle detection means among the toggle timings generated in the first digital signal; Encoding means for generating a digital signal; the inversion discrimination signal; and the plurality of second signals corresponding to the plurality of first digital signals. Output means for outputting a digital signal to the signal transmission line in parallel. 7. The digital signal transmitting device according to claim 6, wherein a complementary metal insulating film semiconductor integrated circuit is provided between said output means and said signal transmission line. 8. The digital signal transmission device according to claim 6, wherein said encoding means generates said second digital signal based on said inversion discrimination signal. 9. A digital signal receiving apparatus for receiving a plurality of digital signals transmitted in parallel via a signal transmission line, wherein the first level is set at the timing of a toggle generated simultaneously among the plurality of first digital signals. It has the same initial state level as the corresponding first digital signal and the inversion discrimination signal that switches between the second level and the inversion timing signal. A plurality of second digital signals whose levels are switched at timings other than the timing of the generated toggle,
A digital signal receiving device, comprising: receiving means for receiving via the signal transmission line; and decoding means for decoding the received plurality of second digital signals based on the received inverted discrimination signal. 10. A semiconductor integrated circuit having a complementary metal insulating film is provided between said signal transmission line and said decoding means.
3. The digital signal receiving device according to claim 1. 11. The inversion discrimination signal is at a first level as an initial state, and the decoding means receives the second digital signal while the received inversion discrimination signal is at the first level. Signal level, and while the inversion determination signal is at the second level, a third level obtained by inverting the level of the received second digital signal.
The digital signal receiving device according to claim 9, wherein the digital signal is generated. 12. A digital signal transmission method for transmitting a plurality of digital signals in parallel, wherein a toggle generated simultaneously among a plurality of first digital signals is detected, and a first level and a first level are detected at the timing of the detected toggle. 2
Generating an inversion discrimination signal that switches between the first digital signal and the first digital signal, wherein each of the plurality of first digital signals has the same initial state level as the first digital signal. Generating a second digital signal whose level is switched at a timing excluding the detected toggle timing among the toggle timings to perform the inversion determination signal and the plurality of first digital signals corresponding to the plurality of first digital signals. A second digital signal transmitted in parallel via a signal transmission line; and the plurality of second digital signals received via the signal transmission line, the inversion determination signal received via the signal transmission line. Digital signal transmission method for decoding based on 13. An initial state of the inverted discrimination signal is set to a first level, and while the received inverted discrimination signal is at the first level, the level of the received second digital signal is held. The digital signal transmission method according to claim 12, wherein the decoding is performed by inverting the level of the received second digital signal while the inversion determination signal is at the second level.