JPS5817658A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain sufficient breaking strength even when a junction area is reduced by deepening a section, to which high voltage is applied, in a semiconductor region as a protective resistor to comparatively deep value and expanding the junction area. CONSTITUTION:When a comparatively deep well region 3 is formed integrally to the input section of the protective resistor R, the junction area in region falling to a diffusion region 2 from a pad for input is enlarged, and dielectric resistance can sharply be elevated. A diode D2 is directed in the forward direction and currents flow through a substrate 1 when positive abnormal input is applied to the diffusion resistance R, and the diode D2 can resist sufficiently against negative abnormal input by the large junction area while currents can be made escape through a clamping diode D1. Accordingly, an input protective circuit indicates sufficient breaking strength even when either abnormal voltage is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and a semiconductor device having an input protection circuit.

OM OB (Oomp'lementary M O
8) In the type Ls construction, input gy is required for gate protection.
c input protection circuit 1lI81ft is provided. Various types of protection circuits can be considered, but one that the inventor has considered is the following:
It was found that neither of these methods gave satisfactory results.

In other words, 1, for example, the input pad and the M 8 for 0MO8 (Met
al engineering n8u14tor 8emiconauCtor
) When a diffusion, a resistor, and a clamp diode are connected to the gate of the P IRT, the junction breakdown voltage of 7 becomes low because the diffusion resistance becomes shallower with finer patterning. When an abnormal voltage is applied, the space between the diffusion region and the semiconductor substrate is likely to be destroyed.

In addition, when a polysilicon film formed on a semiconductor substrate is used as a holding resistor instead of the above-mentioned diffused resistor, the area of the clamp diode is reduced by that amount because the polysilicon resistor cannot conduct current to the semiconductor substrate. 4F must be increased to increase the breakdown voltage t, and thin Li patterning (Al
1) This is disadvantageous for K.

Therefore, the present invention is based on the above-mentioned recognition, and provides a semiconductor device incorporating a protection function or an optical protection circuit even though it occupies a small area, such as a 0MO8 type L8 type metal 8 type device. t purpose.

To achieve this purpose, according to the present invention, the part of the semiconductor region serving as the S resistor to which high voltage is applied (the region connected to the input pad) is made relatively deep to increase the junction area. This increases the junction breakdown voltage there. Therefore, sufficient breaking strength can be obtained even if the protective resistor itself is made shallow and has a small area for fine patterning.

Hereinafter, an embodiment in which the present invention is applied to a '9tOMOa type L8 machine will be described in detail with reference to the drawings.

Figures 1 to 3 show the first stage 0M of eMosWL Day I.
The figure shows the O8 inverter and the input protection circuit section.

That is, cM
oa1r constitutes P channel MIgFICτqI and N
A channel M 81FICTQ, a clamp diode D, and a diffusion resistor R, which constitute these 11 gate retention circuits, are provided, respectively. The diffused resistance R is connected to a shallow, small-area P-type region 2, and is connected to a relatively deep P-type region 2.
- type well region 3. The depth of the P+ type region 2 is 0.5μ, and the width of the degree 1 is 6μ? ) The well region 3 has an area of 24p × 24μ with a quarry of about 4μ.Therefore, the aluminum wiring number extending from the input pad is the region where it is connected to the diffused resistor R. Due to the presence of the well region 3, the area of the junction with the substrate 1 is considerably expanded.

In other words, the PM junction diode D! formed by that junction! It is extremely important that the junction area is large, and that it is integrated with the protective resistor R and is provided at a location* where high voltage is most likely to be applied (easily destroyed). The resistor R is connected to the clamp diode DI (DI
There is a connection leakage to the mold diffusion region 6, and this diffusion region is also FK.
It is commonly connected to the gate electrodes 7 and 8 of TQ and Qm. The well region 3 of the resistor R, the P-type well region 9 of the clamp diode DI, and the P-type well region 10 of the FKTQ layer are formed at the same time in the same diffusion process, and the P-type well region of the resistor R is formed at the same time. Region 2 and FITQI P type diffusion regions 11 and 12. N of clamp diode D1
Type area 5 to Fk! ? N+ type diffusion regions 13 and 1 of Ls in
4 are also books formed by the same royal power. Naka, 15
．． 16 and 17 are each aluminum wiring or electrode of 0M0B, and 18 expanded field 810! 19 is a gate oxide film.

20 shows the growth on the surface of the polysilicon gate electrode81
03 film and 21 are phosphosilicate glass films.

If a relatively deep well @jJI3 is formed integrally with the input side portion of the holding resistor R as described above, as can be understood from FIG. Large area and large pressure resistance! It can be stirred up. This region is the weakest part and is easily destroyed by Joule heat when a high abnormal voltage is applied, but such an I# state can be effectively prevented by forming a diode Dl with a large junction area (junction withstand voltage). It becomes possible to achieve sufficient gate protection (electrostatic breakdown strength).

As mentioned above, this is the input of the diode Dst - just a resistor -
There are many things that will become possible by integrating the - s4. To be specific, when a positive abnormal input enters the diffused resistor R, the diode DI becomes forward and the substrate IVC11flt flows, and for a negative abnormal input, the diode D has a large junction area. In addition to being able to withstand the current, it is possible to escape the current through the clamp diode DIk. Therefore, no matter which abnormal voltage is applied, the input membrane protection circuit according to this example exhibits sufficient breaking strength.

On the other hand, if the diode D was placed at a location away from the diffusion region 2, the input side junction of the 4M protection resistor would be shallow and the area would remain small, so it would be less susceptible to the effects of abnormal input. It is inevitable that it will be damaged and destroyed.

Next, a method for creating the structure shown in FIG. 1 will be explained with reference to FIG.

First, as shown in FIG. A relatively deep P-type well is formed by the diffusion technique.

After removing the mask 22Q, as shown in FIG. 4B, fields 810. Film 1st - Grows in a predetermined pattern and separates each element region.

Next, after removing the silicon nitride film 23 and the underlying SIO film 24 by etching, as shown in FIG.
Furthermore, polysilicon is deposited over the entire surface by chemical vapor deposition (OVD). This polysilicon film is subjected to a known phosphorus treatment and then subjected to a known photoetching process to form a polysilicon AlI7.8 in the shape of a gate electrode.

Then, after thermally oxidizing the surface of the polysilicon 1s7.80 to form wide 8103 lines 20, as shown in FIG. 4D, well regions 9 and ! A t-mask 24, for example, a photoresist, is set only on θ, and in this state, the entire surface is irradiated with an ion beam 2511 of boron or the like. This allows the mask 24
．． Polysilicon film7. Impurities are implanted into the substrate 1 through the entire gate oxide film 19 in the region where the field region 101 and the gland 18 are not present, and through annealing, each P type region 2, 11 .
12'i are formed respectively. Of these, the P type region 2 is formed to overlap with the well region 3, and both constitute the above-mentioned protective resistor R and diode Ihk.

Next, as shown in Fig. 1141, P+ type region 2 and F
Only the area of mTQ is covered with a mask 26, for example photoresist, and the entire surface is covered with a phosphorus or arsenic ion beam 27.
One ion implantation is performed through the mask 26, the polysilicon 1s, 8, and the gate oxide film 19 in the area where the field 510m film 18 does not exist, and after annealing, an N+ type region is formed in each well region 9.10. 613.14
' to form respectively.

Next, as shown in Figure @4p, only the gate-forming film in the protection circuit area was removed by T-etching, and then the entire (Fig. phosphosilicate glass J [211 cm1] was removed by OVD.

This was photo-etched to form contact holes 28, 29, 30, 31, J2゜33.34t at predetermined locations.
- form respectively. Next, aluminum is deposited on the entire surface using, for example, a vacuum evaporation technique, and patterned by photo-etching to form each aluminum wiring or electrode number 5,15°, 16,1711- as shown in FIG. Contact hole 28 is a contact)? In order to ensure sufficient coverage, VC formation is missed at four locations on region 3 (see FIG. 2). Although not shown, a layer of insulation, a second layer of aluminum, a final passivation film, etc. were also applied.

IC1-Complete name ◇ The present invention has been illustrated above, but the above-described embodiments can be further modified based on the technical idea of the present invention.

For example, the shape of the well region 3 described above may be modified in various ways. Further, the conductivity type of each of the above-mentioned conductor regions may be converted to an opposite conductivity type. Note that the present invention can also be applied to protection circuits of next-stage circuits other than 0M0B.

[Brief explanation of the drawing]

The drawings show an example applied to the Ijll:0M0BfliLB construction of this invention, and Figure 1 shows its OMo8 and gate protection! 1 is a cross-sectional view of the circuit section, FIG. 2 is a plan view of the gate protection circuit section (the cross section taken along line X-X corresponds to FIG. 1),
Fig. 3 is an equivalent circuit diagram of Fig. 1, and Figs. In addition, in the symbols used in the drawings, 3 is a P-type well region, 4 and 5#i aluminum wiring, R1-j
Input protection resistors, DI is a clamp diode, D is a junction diode, Ql and Q! (Each M that makes up all jMOB
It is 871c.

Claims (1)

[Claims] 1. A semiconductor region of a second conductivity type formed as a protective resistor for the next stage circuit on the whole surface of a semiconductor substrate of a first conductivity type, and a semiconductor region of the second conductivity type formed on the whole surface of the semiconductor substrate of the first conductivity type, and the above-mentioned main surface in a state of being tightly connected to one end side of this semiconductor region. In a semiconductor device in which a protection circuit is constituted by a protection diode of a next-stage circuit formed in the semiconductor region, a portion of the semiconductor region on the other end side to which a high voltage is applied is formed relatively deep. A semiconductor device characterized in that a bonding area between the W portion and the semiconductor substrate is expanded.