JPS58175869A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to attain high integration of the integrated circuit by a method wherein a gate electrode and contact holes are formed in the self-aligning positional relation interposing an inside silicon oxide film between them. CONSTITUTION:The gate electrode 15 consisting of a high melting point metal layer is provided on a substrate 11 interposing an insulating film 14 between them. The contact holes 17 are provided at the self-aligning positions in relation to the electrode 15 interposing the inside silicon oxide film 16 positioning at the neighborhood of the edge part of the electrode 15 between them. A source electrode 18 and a drain electrode 19 consisting of silicon layers are provided through the holes 17 as to come in contact respectively to a source region 12 and a drain region 13. Accordingly, size of the element can be reduced, and the device is made suitable for formation in high density. Moreover, because the distance (y) between the electrode 15 and the holes 17 can be shortened, the operating speed of the semiconductor device can be precipitated much more.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a semiconductor device, and particularly to a semiconductor device using a high melting point metal as an electrode or the like, and a method for manufacturing the same.

(Prior art and its drawbacks) Conventionally, in semiconductor devices, materials for electrodes, wiring, etc. are low melting point metals such as aluminum (hereinafter referred to as rAtj), molybdenum (hereinafter referred to as ``MO''), and tungsten (hereinafter referred to as ``W''). ), I & melting point metals such as Menkl (hereinafter referred to as [Taj)], titanium (hereinafter referred to as ``Taj''),
or polycrystalline silicon (hereinafter referred to as l poly8iJ)
Semiconductor materials such as Each of these materials had advantages and disadvantages. That is, among these, although kl has the advantage of low resistivity, its melting point is as low as bto°C, so it has various restrictions when introduced into the manufacturing process of semiconductor devices, which usually requires a heat treatment process of about 1000 times. Ta. On the other hand, poly81 i! It has the advantage of allowing greater freedom in the manufacturing process of semiconductor i7I and semiconductors, since it can withstand heat treatment of about 1,000 kg and has a high affinity with silicon used as a substrate. More po! A saponified silicon film (hereinafter referred to as 8i01 J) with good insulation can be easily formed on the surface of polysI by simply heat-treating it in a concave atmosphere.
Since it can withstand acid cleaning (hereinafter simply referred to as "acid cleaning") with an appropriate mixture of various solutions such as HOllHNO, +)ltO, etc., the element surface can be easily cleaned, so electrodes, wiring, etc. When used for K poly 811, there was an advantage that the manufacturing yield of semiconductor devices was high.

However, the specific resistance of PO1781 is two to three orders of magnitude higher than that of metal, so in semiconductor devices that use POLY81 for electrodes and wiring, the propagation delay due to wiring resistance increases, making it difficult to achieve high integration and high speed. was difficult.

On the other hand, melting point metals such as MoFi have a high melting point of about 24oo"c, and 1ooo"CI! Since Mo can be used in high-temperature heat treatment, the use of Mo in electrodes, wiring, etc. can greatly increase the degree of freedom in the manufacturing process of semiconductor devices, and high-melting point metals have low specific resistance, making them suitable for speeding up semiconductor devices. ing. Because of this, nine semiconductor devices equipped with high melting point metals have been in the spotlight.

However, in the case of high-melting point metals compared to poly81, semiconductor devices with a structure that has a stable and stable insulating layer like a silicon thermal oxide film on the surface, and a method for manufacturing them (easily manufactured) have been realized. My dear friend, semiconductors that use high melting point metals for electrodes and interconnects!Ill never made it into the mainstream of semiconductor technology. Structures with a The silicon oxide layer is [0VD810.
It is possible to selectively form silicon oxide M only on the high melting point metal #1 surface. Furthermore, this 0VD810
It is difficult to form a uniform thickness in a 1mm area, and there is a problem that 0VD810*Fi overhang occurs at the 9-step difference. For this reason, this OVD810mt interlayer insulation is used as a high melting point metal layer with an interlayer insulation step and 0V.
When trying to realize a semiconductor with a three-layer structure of D8 to@ and other conductive layers, there is a drawback that there are many short circuits or disconnections. In addition, the surface K of high melting point metal is
K, which forms 0VD8i01, is the ninth trap to prevent oxidation of high-melting point metals.Once the temperature inside the OVD chamber is lowered, the sample containing the high-melting point metal is placed in the OVD chamber, and the inside of the scissor chamber is placed in an inert atmosphere. After raising the temperature, supply the reaction gas into the 1* chamber and bring it to 0VD810. Friends must be formed. This has the drawback that the operation is complicated and takes a long time. In the conventional method, 0VD810. 0VD810° had to be made as thick as, for example, zooog in order to eliminate Mt# during the breakdown voltage and presence of pinholes, making it difficult to increase the density of semiconductor devices.

By the way, the MI8 field effect transistor (hereinafter referred to as "M
18FFIT J), a structure shown in Fig. 1 has been proposed in the past. Reference numeral 1 denotes a substrate, in which a source region λ and a drain region J are provided, and on the substrate 1, a gate electrode j made of poly81 or a high melting point metal is provided via gate oxidation APR. And the gate electrode! A 0VD8 to insulating group is provided on the surface of the 0VD810 on both sides of the gate electrode j.
．． A contact hole 7 is formed in A and the gate oxide region μ, and a source electrode lil and a drain electrode D are provided in contact with the source area λ and the drain region 3, respectively, through the contact hole 7. In such a structure, it is clear that the distance X between the 94 wall of the gate electrode j and the contact hole 7 poses a problem with the withstand voltage, especially when a high melting point metal is used as the gate electrode j. I couldn't. If we consider the process steps to realize the structure shown in Figure 1, the gate voltage @
+i 0VD8i0. , and then a contact hole 7 is formed using phosphorography and etching techniques. 0VD8i0. Since A is uniformly formed on the gate oxide surface other than the surface of the gate electrode j, it becomes necessary to form a contact hole 7.
Due to the limits of accuracy of the ring-two-fi technology used at this time, it is difficult to reduce the distance X to 1 μm or less. In this way, in the conventional technology, the distance X is shortened and the nine structure MI8j'
It was difficult to manufacture IT and rounding, making it impossible to realize high-density semiconductor devices. (9) In the conventional semiconductor device, it is difficult to round off the distance existing between the gate region under the gate electrode j and the contact hole 7 faster than the operating speed t.

(Object of the Invention) An object of the present invention is to provide a semiconductor device having an electrode/contact hole structure in a self-aligned positional relationship suitable for high density, and a method for manufacturing the same.

Another object of the present invention is to provide a high-speed semiconductor device and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor device having a highly insulating silicon oxide film only on the surface of an electrode made of a high melting point metal, and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same with fewer short circuits and disconnections in electrode portions made of high-melting point metal.

Another object of the present invention is to provide a method for manufacturing a semiconductor device using a high melting point metal as an electrode with high yield.

(Structure of the Invention) In order to achieve the above object, a typical semiconductor device according to the present invention includes a high melting point metal layer provided on a base body having an insulating layer on the substrate, and an internal silicon oxide film. and a silicon layer, the internal silicon oxide film is provided between the high melting point metal layer and the silicon layer, and the internal silicon oxide film is formed by internally oxidizing the silicon layer. The silicon layer is an oxide film, and the silicon layer is in contact with the substrate through a contact hole drilled in the insulating layer, and the contact hole is provided near an end of the high melting point metal layer.

(9) A typical embodiment 1111 of the method for manufacturing and using a semiconductor device according to the present invention includes a step of forming a high melting point metal layer in a predetermined shape on a base body made of a substrate provided with an insulating layer; a step of forming a high melting point metal oxide layer at @m of the metal layer, a step of forming a contact hole in the insulating layer in contact with an end Kll of the high melting point metal layer, and a step of forming the contact hole and the high melting point metal oxide layer. a step of forming a silicon layer so as to cover the high melting point metal layer, the high melting point metal oxide layer, and the silicon layer, and heat treating the substrate having the high melting point metal layer, the high melting point metal oxide layer, and the silicon layer in an atmosphere containing water volume, and forming a silicon layer on the high melting point metal layer and the silicon layer. forming an internal silicon oxide layer between the layers. Unfortunately, depending on the λ-th U aspect of the manufacturing method, in the first embodiment described above, a silicon layer is formed on the contact hole and the high melting point metal oxide layer, and afterward, 11 sides of this silicon layer are oxidized, and then the internal silicon is formed. It is characterized by performing an oxidation group formation process. Further, according to the rattan 3 and rattan - aspects of the manufacturing method, in the first and λth aspects, respectively, the high melting point metal oxide forming step, the contact hole forming step, and the O order are performed by avoiding the order. do.

(Example) The present invention will be explained below based on examples.

FIG. 2 shows an example in which the system is applied to the Honkai Meikai MI81'IT. For example, ll is a single crystal substrate with a specific resistance of about JΩ-〇P, and λ and 13 are the source and drain regions provided in the substrate, respectively. is O1λrfirn.A gate electrode made of a high melting point metal layer, for example M6 with a thickness of 0.3 μm, is formed on the substrate ll via a gate oxide Hip.
9, this gate electric & l! has a predetermined shape, for example, a rectangular cross-sectional shape. 16 is formed by oxidizing the silicon layer constituting the source electrode and the drain electrode from the inside, that is, from the side of the melting point metal layer which is the gate electrode/j, and has a thickness of, for example, f! dJ'/') is a silicon oxide film, and 17 is a contact hole drilled in the gate oxide film /N. A source electrode it and a drain electrode l? made of a silicon layer are provided through the contact hole 17f in a self-aligned position 11. are provided so as to be in contact with the source region 1 and the drain region 13, respectively. Source electrode it and drain voltage 4kl? All-constituting silicon layer F
It can be made of ipoly81 or amorphous silicon, and the thickness is, for example, 0#! μm, and its impurity concentration is about t O”
ah-” f h b.

In such a MI8FBIT, the gate electrode 12 and the contact hole 17 are connected to the gate electrode l! 0 V
D810. The size of the element is smaller than that used in the case of using the same method, and the structure is suitable for increasing bulk density.

Furthermore, the distance between the gate region and the contact hole is 11111y.
Since the length can be shortened, the operating speed of the semiconductor device can be further increased.

In addition, as will be described later, the internal silicon oxide 11/4 has the same film quality as a silicon thermal oxide film, for example, has a dielectric strength voltage, so MI8Fm! T is the gate electrode l
! The insulation properties between the source electrode (or the drain electrode) can be improved.

Figure t83 shows an example of a pigeon house in which the present invention is applied to a semiconductor device with a so-called two-layer gate structure. J7 is a cell plate electrode made of po1781 provided on the gate oxide ll1v, and 21 is a cell plate electrode made of po1781, for example, oxidized on the cell plate electrode coO.

The gate electrode 12 made of a high melting point metal layer is a silicon oxide film with a thickness of 0.7 μm formed using a gate oxide W1/4.
The internal silicon oxide film 1114 is provided on the surface of the gate electrode 1zc1, and the internal silicon oxide film 1114 covers a part of the internal silicon oxide film. This is a silicon layer provided so as to be in contact with region 2 in substrate 11 through cover contact hole 23. The above-mentioned cell plate electrode is used as the electrode of the OF'i capacitor portion. In the semiconductor device #: of this structure, like the one in FIG. 2, a contact hole 23 is provided in a self-aligned positional relationship with respect to the gate electrode lj through the internal silicon oxide 1174. However, the number of contact holes is one for one gate electrode.

Next, another 1I embodiment having one contact hole for one gate electrode is shown in FIGS.

In figure 1, l! is the gate oxide film/l on the base@it
With the gate electrode provided through t, the gate electrode l! An internal silicon oxide film 14 is provided on the surface of the gate electrode II, and an internal silicon oxide film #1 is provided near one end of the gate electrode II.
4, the silicon layer here is in contact with the area inside the substrate 1/ through a contact hole J3 provided in a self-aligned position with respect to the gate electrode /J'', and the gate electrode
Near the other end of j is a cell plate electrode 2j provided via internal silicon iron oxide l≦ and on gate oxide 1%/4c, and this cell plate electrode @2! consists of another silicon layer that is insulated and separated from the silicon layer here. In Figure 1, one of the two high melting point metal layers provided via the gate oxide # slag on the substrate it is connected to the gate voltage @ /j
The other side is used as a cell plate electrode roller, and internal silicon oxide 9I/4 is provided on the surfaces of the gate electrode lj and cell plate electrode roller, covering the internal silicon oxide @/4 and the gate oxide film l. A silicon layer λ is provided, and two of these silicon layers are gate electrodes l! Internal silicon oxide film 1 at one end of
The substrate is in contact with the region 241 in the substrate /, / through the contact hole 2Jt which is in a self-aligned positional relationship through the contact hole 6, and corresponds to the other end of the gate electrode lj and the cell plate electrode roller. Other area cores are provided within ii. The silicon layer λλ is the gate electrode l! It is not necessary to invade both the cell plate electrode roller and the cell plate electrode roller, and it is sufficient that the contact hole is in contact with the area reference through the contact hole λ3.

Figures 3 to ! mentioned above. In the example shown in the figure, the substrate //, the region cocoa, and the silicon layer Coco-Coj are shown in FIG. All you have to do is use the same thing. In addition, in all of the structures in Figures jIJ to Jll, the internal silicon oxide film 14 is selectively provided only on the surface of the high melting point metal layer used as the gate electrode @it or the cell plate electrode J4, and the internal silicon oxide film 14 is provided on the other parts. Internal silicon oxidation on the surface #/! is not formed. Figure 3 ~ Theory! Semiconductor devices with the structure shown in the figure all have a thin internal silicon oxide layer.
1/A through the gate electrode l! and contact hall co J
Since they have a self-aligned positional relationship, they are suitable for increasing the density of integrated circuits. Furthermore, since the distance between the gate region and the contact hole is shortened, the semiconductor device can be highly integrated and operate at high speed.

In addition, for the sake of brevity, the silicon layers /If, /P, 20. Ko! Although we will explain the structure in which the .

Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described.

pmll single crystal silicon substrate//gate gate on top/4
For example, a silicon layer with a thickness μooX is formed as a candy layer to be used for CK, and then a high melting point metal layer is formed.
3^ A single point metal layer is processed using the well-known ring 2-fi technology and etching technology to form a gate electrode IS.
Get the structure of the diagram. The material used for the high melting point metal layer of the gate electrode must have low resistivity and high heat resistance, and the oxide of the material must be easily reduced by heat treatment in an atmosphere containing bulk water. Yes, for example, pigeons.

W * T @ + 'r1 There is fathom. This embodiment will be described in detail below using M as an example. 6th-Am gate electrode l! The thickness is approximately JOO formed by electron beam evaporation method.
M is OK.

Next, from the main surface 30 side to the one with the structure shown in #l7-A,
The impurity of IIi, for example, HiA, is dosed @X10”e-
”, gate electrode lj with implantation energy/00 kaV
Using the mask as a mask, ions are implanted and then annealing is performed to form a source region I and a drain region IJ, thereby obtaining the structure shown in FIG. 4-B.

゛Next, the surface of the high melting point metal layer used as the gate electrode @/j is oxidized to form a high melting point metal oxide layer 31t-.
Obtain the structure of -O1 ml. M is generally stably obtained when M is used as the high melting point metal layer V.

Examples of oxides include molybdenum dioxide (hereinafter referred to as "hato o1") and molybdenum dioxide (hereinafter referred to as "M, o,").
There is. Mt, 0. is easily obtained by low-temperature heat treatment in an atmosphere containing Met-oxygen, but this M.0. begins to sublimate when the temperature reaches a high temperature of about 100°C or higher. Therefore, as the high melting point metal oxide layer 31, M@0. When using M・0. This is inconvenient as peeling of the film may occur.

Therefore, the melting point of the high melting point metal oxide layer J/ is 1200.
It is necessary to use 1 M, O, which is stable at high temperatures as high as ℃. However, it has not been easy to form M.Om on the conventional M.Om surface. As a result of various studies, we found that M・o, t
We have discovered two methods of oxidizing M that can be stably produced on the surface of M. The first method is to heat M. to 70'C in an oxygen atmosphere.
-HM・0. is oxidized to the surface of M. Tube formation followed by M.0. M・O,l is heat treated at a temperature close to or higher than the sublimation point of
In this method, Me Om is formed on the surface of M. instead of M.O. The 20th method is to press a gong in an inert gas (e.g. nitrogen gas) atmosphere containing a trace amount of oxygen (7.0% or less).
・Heat-treated at a temperature close to or higher than the sublimation point of 0.M@#! This is a method of forming Mo1st on the surface. With these two methods, the Meflt compound on the 9M surface is M,
0. Being a good friend of FiXS diffraction and electron diffraction.

In this example, the first method was used to form M.Os, which would become the high melting point metal oxide layer J/. For example, a substrate with 1M. Heat treatment M for 30 minutes at
・M・0ttllk with a thickness of about 0OA is formed on the 11th side of
) (b) (c) Fi formation temperature is j 00 respectively
'C.

Me0illK for the case of 3λo”c, izo℃
The thickness depends on the formation time. As will be described later, the thickness of the internal silicon oxide @i group formed depends on the thickness of the M・0□ gland formed by converting MeO, so in order to control the thickness of the internal silicon oxide @/4, This M2O.

It is important to accurately control the zero test thickness.

Figure 7 shows M.0. It is shown that the accuracy depends on the control of the film thickness of M. is superior in terms of controlling the film thickness of Moo and preventing oxygen from diffusing into M.

If oxygen diffuses into M, it is not very desirable because M will undergo a large volumetric contraction in the internal silicon oxidation lIK formation process described later.

Next, a resist pattern is formed on the structure shown in FIG. 4-0 using a known phosphorography technique. This resist pattern JJ has, for example, an open bottom J field for forming a contact hole, as shown in Figure 6-D. It is preferable to form them so that they overlap. Note that in conventional manufacturing plants, when a resist pattern is used in which the gate electrode @/j overlaps with the gate electrode 1B of the 1st part J, the gate electrode 1 is exposed in the subsequent process! Since the contact electrode would be short-circuited, the opening JJa must be formed at a distance from the gate electrode 12, and the distance at this time is usually determined by the amount of side etching during lithography and the amount of side etching during etching. In consideration of this, it is normal to set the number of voices to m or more. In the present invention, as described later, the trap silicon layer JJ
Internal silicon oxidation 11 after making the connection with the substrate//
Since the gate electrode lj and the silicon layer JJ are insulated and separated by forming the gate electrode 174, it is possible to form a resist pattern in which the gate electrode @II and a part of the opening 3 overlap. - Gate oxidation 1174 (
The resist pattern 321 is used as a mask to be drilled using a known etching technique to form a contact hole 17, and then the resist pattern 32 is removed to obtain the structure shown in Fig. 6-H. Next, the structure shown in Fig. 4-II is obtained. Silicon layer 3J on top of the thing
is formed to obtain the structure shown in Fig. 4-2. Silicon layer JJId
It may be p.+yst or amorphous silicon. In this example, psly81 is 1jo by electron beam evaporation method.
It was formed to a thickness of 0 nm. Thereafter, in order to lower the resistance of this poly 81, impurities such as arsenic are added by ion implantation. Other formation methods such as OVD may be used to form the poly 81 used as the silicon layer 33. may be added. It goes without saying that the impurity concentration of poly8i can be set appropriately depending on the use of poly81. The high melting point metal oxide layer 31 is reduced by heat treatment in 11N air (raw gas), and at the same time, the silicon layer 3J is oxidized from inside the tube, that is, from the high melting point metal layer side, and internal silicon oxidation lI! /4 to obtain the structure shown in Figure 4-0. In this example, 10
A heat treatment was performed at a temperature of 00°C for 40 minutes to reduce Mo and bind it, and at the same time reduce the internal silicon oxidation Y14I4 to about 7O
A thickness of oX was formed. In the above example, heat treatment is performed at 100°C for 60 minutes, and this heat treatment condition is such that the high single point metal oxide layer 31 is simultaneously reduced (silicon layer J3 adds phosphine (1'Hs) to the internal atmosphere). It is also possible to convert the internal silicon oxide into 1I16tl-phosphorus glass.

Next, the gate electrode l! A portion of the upper silicon layer J j th is removed using a well-known phosphorography technique and an etching technique, and the remaining silicon layer is used as a source electrode it and a drain electrode @it to obtain the structure shown in FIG. 6-H. In this case, an insulating wire such as a silicon oxide film formed by oxidizing the silicon layer 331 may be provided in the gap between the source electrode it and the drain electrode l.

After this, steps for forming interlayer insulating lines, wiring layers, etc. may be performed as necessary.

The changes in the structure before and after the internal silicon oxidation imaging process described above will be explained based on the results of Auger electron spectroscopy measurements. Figure (4) is before internal silicon oxide group formation;
Regarding the structure of Figure 6-6-1l1, after the internal silicon oxide film formation step, that is, with respect to the structure of Figure 4-0, the silicon layer 33I! Structure 7c tree 1y') from surface to substrate//force direction distribution in depth direction is shown, respectively. The horizontal axis represents the time during which the sample was etched, which corresponds to the depth from the surface of the silicon layer 33. (a) , (
b), (cl are curves showing silicon and oxygen 1M·, respectively.

Figure 1 (4) is M. M, o, is formed on top, MoO is formed on top, and poly8i is formed on top.
clearly shown. Comparing Figure 1) with Figure R, M, 0. The part that was M, K is reduced to poly
poly81 from the vicinity of the interface between 8.1 and M2O.
It can be seen that about 7001 internal silicon iron oxides are formed in the direction of the 11E peak.

According to FIG. This indicates that no silicide is formed. Furthermore, since FIG. 6 shows an Auger electron distribution, it is judged that both interfaces are formed very homogeneously and uniformly. By heat-treating the structure shown in FIG. 4-V in an atmosphere containing hydrogen, internal silicon oxidation 1111 as shown in FIG. 6-0 is obtained! The reason why /A is formed is considered as follows.

That is, Mo01 is reduced by the following reaction, and M, 0.
+λH, -11Mo+koH,0 H8 generated at this time
It is considered that poly8, which is the silicon layer 33, is saponified by N/4 to form internal silicon oxide N/4. Therefore, the amount of hydrogen used as the heat treatment atmosphere may be sufficient as long as it is used in the above-mentioned reduction reaction. Since the amount of H and 0 generated in the above reduction reaction is limited at most by the # bulk amount constituting MoOI, the maximum thickness of the internal silicon iron oxide 16 that can be formed is
, fl is determined by the thickness.

Next, the iron quality of the internal silicon oxide lIJ formed in the above-mentioned internal silicon oxide line forming step is
'1llll[i, so I'll explain the results. First, XP
8(x-ray photoselect?..5pec
tr. 1copy) Internal silicon oxidation I by measurement
When we examined the composition of I/6, we found that the silicon 2
Since the binding energy of p electrons is /OJ, J eV, which is almost the same as the binding energy value of col electrons /OJ, 4A eV of normal silicon #oxide film 0 silicon, the composition of the internal silicon oxide film 14 is normally It was determined that the composition was similar to that of the thermal oxide film of silicon. Next, dilute hydrofluoric acid with internal silicon oxidation of 111/4 (hydrofluoric acid diwater = J
: ioo ), the etching speed is lλoR7
The etching rate was almost the same as the etching rate of 102X/min using a similar solution for normal silicon ll'alization.

Next, a 100μ square po1 is placed on the internal silicon oxide fA/6.
781 112 layer electrode formed, internal silicon iron oxide 1
When we measured the withstand voltage and leakage current of No. 6, the withstand voltage was 1O
6■/(to) or more, the leakage current is less than IOA,
A value equivalent to that of a normal silicon thermal oxide film was obtained. From the above bond value results, it was concluded that the film quality of internal silicon oxide @/4 was - etc.7 compared to a normal silicon thermal oxide film.

As explained above, when the method according to the present invention is used, silicon@33 and gate electrode l! Since insulation separation can be performed after forming the silicon layer 33, a part of the contact hole forming opening 5321 can be formed overlapping the gate electrode ij in the resist pattern forming process, so that the contact hole 17 can be self-aligned with the gate electrode lj. It can be formed in the desired position. As a result, it is possible to realize a semiconductor device 1 having a structure in which the gate electrode lj and the contact hole 17 are in close proximity to each other via the thin internal silicon oxide film 16, which has a small cutting area and is suitable for increasing the density of integrated circuits. For example, the distance between the gate electrode and the contact hole can be reduced by more than an order of magnitude compared to the conventional structure, and the cell area can be reduced by several IO%. Furthermore, the gate electrode l
The distance between the gate region under j and the contact hole 17 is uniquely determined by the thickness y of the internal silicon oxide film/A, and since this distance is short, an extremely high-speed semiconductor can be realized.

1 with a diagram of Jiu Xie! As explained above, the S quality of the internal silicon iron oxide has the same film quality as the thermal oxide film of silicon, and the OVD
Since it is superior to 810□, by using the present invention, it is possible to realize a semiconductor device with good insulation properties between the gate electrode and the silicon layer used as another electrode. Furthermore, a high melting point image l141I is evenly and uniformly formed on the surface of the internal silicon oxide II/AFi and high melting point metal layer! Since it is formed using H and 0 generated when reducing the compound layer, it has a structure that uniformly and selectively covers only the surface of the high melting point metal layer. Since the internal silicon ridge 16 is not formed in an overhang shape at the stepped portion of the electrode /j, there is no problem of disconnection of the silicon layer at the stepped portion. Since there are no short circuits or disconnections, the manufacturing yield is also extremely high. Furthermore, during the internal silicon oxide expansion formation process, gates can be easily formed without requiring complicated procedures and time to prevent the formation of 0VD8 io on the conventional M. Internal silicon oxidation on top of Ir*/
Naturally formed in 4.

In addition, since M.01 of the high melting point metal oxide layer J/ can be relatively resistant to acid cleaning, by performing an appropriate acid cleaning session in the process when moving from Figure 4-D to Figure A-g. The surface of the element can be cleaned, the manufacturing yield can be improved, and the manufacturing equipment can be prevented from being contaminated.

The manufacturing method described above is not limited to the steps shown in FIGS. 6-A to 4-0, and various examples can be considered.

As a first modification, the ion implantation step and the refractory metal oxide layer forming step are reversed in the embodiment shown in FIG. That is, the structure shown in FIG. 6-A is subjected to a process of forming a high melting point metal oxide layer to obtain the structure shown in FIG. By doing this, the structure shown in Figures P-B is obtained, and then the same process as in the case of Figure 6 is performed to obtain the structure shown in Figures A-D to Figure 6.
- Obtain structure 1 in diagram H. According to this method, Gate Electric/
crystalline high melting point metal oxide layer 31
Since this structure is formed, the blocking power against ion implantation can be increased, and this is effective in correcting the so-called tearing phenomenon. For example, in the case of M., etc., the % trap is effective when the gate electrode 13f has a high crystallinity or is made into a thinner film of 200X or less.

Further, as a modification example 1, there is one in which the high point metal oxide layer forming step and the contact hole forming step are reversed. That is, based on the structure of Figure 4-B, Figures 4-D and 6-
The structures shown in Figures 1-oh and 10-B are obtained by performing four different processes to obtain the structure shown in Figure E, and then the process of forming a high melting point metal oxide layer is performed to obtain the structure shown in Figure 10-0. obtain. In this case, a part of the substrate ii exposed through the contact hole 17 is also oxidized when forming a single layer of high melting point metal oxide, but the oxidation temperature at this time is as low as 300'' C1i degrees.
Since the silicon oxide film formed thereon is only about the same thickness as the natural oxide film of silicon, light etching treatment with dilute hydrofluoric acid can be applied to the gate oxide film/4C without reducing its thickness. The structure shown in the 1O-0 diagram can be realized. Note that M.0m has sufficient resistance to dilute hydrofluoric acid. Thereafter, the same structure as shown in FIGS. 6-Y to 4-H is obtained by the same steps as in FIG. 6.

By the way, in the example of the manufacturing method explained so far, when the poly8i used as the silicon layer 33 is thin (for example, 110019 degrees), the M6 and po1781 boundaries thiK
It becomes difficult to form a somewhat thick internal silicon oxide film. The reason for this is thought to be that if the silicon layer 33 is too thin, H and O will dissipate to the outside through pinholes and grain boundaries of silicon/fjJJ during formation of the internal silicon oxide film. In order to solve this problem, after obtaining the structure of the kite 6-F@, a silicon oxide film 3 is formed on the surface 1 of the silicon layer 31, and after obtaining the structure of the kite 6-F@, It is sufficient to perform the rounding process to obtain the structure 1 in Figure 1-0 to obtain the 1st/-H structure. After that, this silicon oxide film 3≠ must be 4/! You can leave it on and use it or remove it depending on your needs.

Internal silicon oxidation @/4 using the structure shown in Figure 1 /-A
The results of Auger electron spectroscopy when the formation process was carried out are shown in Figure 2, comparing them with those when no silicon oxide film was formed. As the silicon layer 33, poly 81 t- with a thickness of tiooX formed by electron beam evaporation was used, and the silicon oxide film 3hiro was made, for example, by thermal oxidation to a thickness of -00.

Figure 7 λ ((transformation) is when internal silicon oxidation formation is performed without providing a silicon oxide film 3-layer, and the rattan lJ diagram) is when internal silicon sensitization gland formation is performed with a silicon oxide film 3-layer provided. The depth distribution of the constituent elements from the surface of Silico 7133 to the substrate // force direction is shown. If there is silicon oxide 1lIJ4I, from the first figure CB), po
Relatively thick internal silicon oxide 1 between ly81 and M.
1/A is formed and poly81 and internal silicon oxide W
It can be seen that both the interface with Ik16 and the interface between internal silicon oxide film/6 and Mo are formed homogeneously and uniformly. In addition, poly81 is thermally oxidized to form a silicon oxide film 3.
4! It has also been confirmed that even though - is formed, M. is not oxidized.

On the other hand, as a countermeasure for the case where the silicon layer J3 is thin, it is effective to make the surface of the silicon layer 330 amorphous or cover it with a precise coating. or nitriding *1-
After deposition, the surface of the silicon layer may be directly nitrided.

The above describes the manufacturing method of a semiconductor device having two contact holes for one gate electrode in (9) and then briefly explains the manufacturing method of a semiconductor device having one contact hole for one gate electrode. .

p! ll Single crystal silicon substrate//Gate oxidation experiment/I
1. Forming poly8i which will become the cell plate electrode 20 via I4. This is processed and an insulating layer of silicon oxide film 21 is formed on its surface, and a high melting point metal layer is further formed so as to cover the gate oxide 11114 and silicon oxide film λ1, and this high melting point metal layer is used as a cell plate electrode. The gate electrode l! is processed into a predetermined shape so that it overlaps at the step part. Fully formed 1st j-A
Get the structure of the diagram. Thereafter, the same steps as those shown in FIGS. 4-B to 6-G are performed to obtain the structures shown in FIGS. 73-8 to 73-8, respectively.
The structure of 73rd-G(2) is obtained. What is different from the series of 11116 diagrams is that there is only one impurity region λ- provided in the substrate by ion implantation (m/j-B diagram), and the number of contact holes J is also the same as that of the gate electrode l! There is only one point. Thereafter, the silicon pigeon λ is processed as necessary to obtain the structure shown in Fig. 73-H.

Next, let's talk about another example of the manufacturing method when there is only one contact hole #! Illustrate. No. 741! -A- structure (same as the one in Figure j-A) was subjected to the same high melting point metal oxide layer forming process as in obtaining the structure of 4-0-.
- Obtain the structure of diagram B. Next, obtain the structure 4 of Figures 6-9 to 4-H and perform the step 1WII1.
Obtain the structure of OE-Edit/4A-B diagram. At this time, one contact hole J is formed for the gate electrode 12.

Next, 14th C-1! The structure shown in the figure is heat-treated in an inert atmosphere (for example, nitrogen) to diffuse impurities in the silicon layer λ into the substrate, forming an impurity-filled region λ-.
Obtain the structure shown in Figure 44-H. Then Figure 1-G and Figure A-
A process similar to that for obtaining the structure shown in Fig. H is performed to obtain the structures shown in Fig. 14 cm G and Fig. 1 μ-H. At this time, a part of the silicone layer is used as a cell plate electrode. Note that the process of obtaining the structure of Figure 1 $-H and the process of obtaining the structure of Figure 1-0 may be reversed.

Next, another embodiment of the manufacturing method in which there is only one contact hole will be described. 1j-Ae%Q) ml@
1j-8 to 1j-, respectively, by the same process as that of forming the high melting point metal layer which will become /j and cell plate electrode λ, 6, and then obtaining FIGS. ot
Obtain the structure of p:i. What is different from the series of FIGS. 6 at this time is that a contact hole λ3 is provided only near the end of the gate electrode @/j on the opposite side from the cell plate electrode λ6, and the silicon layer 1 is formed through this contact hole 23. It is connected to one impurity region 2hiro. Thereafter, the silicon layer 2λ may be processed if necessary.

7g/J- to Figure 1j-1 (Figure and transfer is-person figure~Saba 1s-H1! Also in the example of Q, there is no tar A figure~my-
BTaA, mto-h diagram ~ 1st O-OQ and 1st/-A
Modifications such as those shown in Figures 1 to 1/-B are possible;
II/0- also in the examples shown in Figure A to Figure 1-H.
Modifications such as those shown in Figures A to 10-0 and Figures ii to 1i-B are possible.

The present invention is not limited to the embodiments described above.
For example, when forming an internal silicon oxide film, the internal silicon oxide film may be formed by reducing part of the M@ and oxidizing the silicon layer at the same time, without reducing all of the M@.

In addition, a null single crystal silicon substrate is used as the substrate // and the regions l//J are formed.

2μ, pall impurity may be introduced into the core, i
The impurity may be introduced into i as shown in Fig. 1-2 using impurity diffusion from the silicon layers tr, i, λ, and JJ. Furthermore, only the silicon layer separated from the refractory metal layer by the internal silicon oxide film may be removed, and another conductive layer with low resistance may be provided in the area where the silicon layer was. Furthermore, although the explanation so far has focused on MI8FHT, the present invention is not necessarily limited to MI8FITK, and may be used where it is necessary to form the positions between electrode wirings or between electrode wiring and contact holes in a self-aligned manner. However, the present invention can be applied only if the high melting point metal oxide can be reduced by heat treatment in an atmosphere containing hydrogen, and it is clear that most high single point images are subject to non-invention. If a high-temperature process is not involved, a metal having the above-mentioned properties and having a melting point lower than the high-melting point metal may be used in place of the high-melting point metal layer.

(Effects of the Invention) As explained above, by using the present invention, it is possible to selectively form an internal silicon oxide group having a film quality equivalent to that of a normal thermal oxidation gorge of silicon only on the surface of a high melting point metal layer. In connection with this, various other effects can be obtained as follows.

Since the distance between (1) the gate electrode via the internal silicon oxide i* and (2) the distance between the gate electrode and the contact hole can be determined only by the thickness of the internal silicon oxide film, a high-speed semiconductor device can be realized.

(3) Since the internal silicon oxide film has good insulation properties, a semiconductor device with excellent insulation properties between the gate electrode and the silicon layer can be realized.

(4) Since the internal silicon oxide film is formed by uniformly oxidizing the silicon layer after covering the gate electrode, there is no short circuit between the gate electrode and the silicon layer.
Semiconductor devices without silicon layer defects can be manufactured with high yield (5) Internal silicon oxidation m The element surface can be easily cleaned by animal cleaning, which improves manufacturing yield and reduces contamination of manufacturing equipment.

[Brief explanation of drawings]

Fig. 1 is a sectional view of the conventional MI8PlaT, Fig. 2 is a sectional view of MI8FIT which is an embodiment of the present invention, and Figs.
Figure J is a sectional view of a semiconductor device according to another embodiment of the present invention, and Figures 6-A to AH are cross-sectional views of the semiconductor device of Figure 2.
Figure 7 is a diagram showing the formation time dependence of M. Diagram showing the measured and determined distribution of constituent elements in the depth direction, 8g?
-Figure A/wJ? -B figure, 10-person figure ~ 1o-o figure,
ii-Am and 1/-B are diagrams for explaining a modification of the manufacturing method of the semiconductor device in FIG. 2, and FIGS. 13-A to 1
3-H diagram, stripe l reference diagram to stripe l≠-H diagram and 1st yo-A
FIGS. 3 to 5 are diagrams for explaining the manufacturing method of the semiconductor devices shown in FIG. 3, FIG. 3, and FIG. 5, respectively. /, //...Substrate, ko, pigeon...source area, 3゜13
...Drain region, Hiro, /41C...Gate oxide film,! , /j...gate electrode, 6...OVD810m
,7, /7゜ko3...contact hole, t,
it...source electrode, F,/ri...drain electrode,
16...Internal silicon oxide film, λ0. Jj, 24...
-Cell plate electrode, Jλ, 33...Silicon layer, CoV, 27...Region, 30...Main surface, 31...High melting point image 141! Chemical layer, 3 resist patterns,
3 things...opening for contact hole formation, 3μ...
Silicon oxide film. /4 Figure 2 ° A3-Figure 4 Figure 1. ．． -A figure ↓ ↓ ↓ le ↓↓ ↓＋＋ Getsu - ε figure f Otsu - C figure O 6 - p Saya 6 - E figure Sai'g - F figure O 6-6 figure ya t - H figure @ time (minute no yahu diagram suha 0, tsuku M-between (minute) -B figure/θ 20 30 Suha 0・Vri between B4-(/97-) Main tZU Sai/3-4 figure ↓ ↓ ↓ 1 ↓ I ↓ ↓ O/3-C flash Pno 3-D close O / J-E flash, 3-F closed / 3-q Akari' / 3 H diagram O 14-Ha listening / 4-B diagram f 14-C flash '14- D lock No. 14-1 Ke/4-F Seno/4-(7 Azo/4-H Figure O15-A Figure ↓ 111 ↓ ↓ ↓ (Inno 5-5 Figure 1'/ -ft5- C Figure 7 Ya15-D Figure 7 O-B-E chuu

Claims (1)

[Claims] (1) Provided on a substrate with an insulating layer interposed therebetween, comprising a high melting point metal layer, an internal silicon oxide film, and a silicon layer,
The internal silicon oxide film is provided between the high melting point metal layer and the silicon layer, and the internal silicon oxide film is made of silicon formed by internally oxidizing the silicon layer from the high melting point metal layer side. The semiconductor device is an oxide film, and the silicon layer is connected to the substrate through a contact hole drilled in the insulating layer. (2) In the invention v1 according to claim 1, the high-melting point metal layer has a predetermined shape, and the contact hole is located near at least one end of the high-melting point metal layer in the interior of the high-melting point metal layer. A semiconductor device characterized by being provided with a silicon oxide film in between. (3) In the invention described in claim 2,
The contact hole is formed on both sides 1111 of the high melting point metal layer.
A semiconductor device characterized in that a silicon layer provided near the substrate and in contact with the substrate through the λ contact holes is insulated and isolated. (4) In the invention described in claim 1,
Another silicon layer, which is an insulating layer different from the silicon layer, is located near the end opposite to the end of the high melting point metal layer where the contact hole is provided, and is separated from the internal silicon oxide film and forms the insulating layer. It is characterized by being placed across the line. (phrase) A step of forming a metal layer with a height of 11 m4 in a predetermined shape on a substrate via an insulating layer, a step of oxidizing the surface of the high melting point metal layer to form a high melting point metal oxide layer, and a step of forming a high melting point metal oxide layer on the surface of the high melting point metal layer. forming a contact hole in the insulating layer adjacent to the end; forming a silicon layer so as to connect the contact hole with the high melting point metal oxide layer; A semiconductor characterized by comprising the step of heat treating a substrate having a melting point metal oxide layer and the silicon layer in an atmosphere containing hydrogen to form an internal saponified silicon film between the high melting point metal layer and the silicon layer. A method for manufacturing a device. (6) forming a high melting point metal layer in a predetermined shape on a substrate via an insulating layer; forming a high melting point metal oxide layer by talizing the surface of the high melting point metal layer; A step of forming a contact hole t- in the insulating layer adjacent to the high melting point metal layer 01llllIs, a step of forming a silicon layer to cover the contact hole and the high melting point metal oxide layer, and a step of forming a silicon layer on the surface of the silicon layer. A method for manufacturing a semiconductor device characterized by comprising the steps of forming a saponified silicon film and forming the high melting point metal layer. Step of forming into a shape and forming the high melting point metal layer
forming a contact hole in the insulating layer in contact with I, oxidizing the surface of the high melting point metal layer to form a high melting point metal oxide layer, and covering the contact hole and the high melting point metal oxide layer. Manufacturing a semiconductor device comprising the steps of forming a silicon layer, and forming an internal silicate layer between the high melting point metal layer, the high melting point full metal layer, and the silicon layer. Method. (8) forming a high melting point metal layer in a predetermined shape on a substrate via an insulating layer; and forming a contact hole in the insulating layer adjacent to an end of the high melting point metal layer;
a step of oxidizing the surface of the high melting point metal layer to form a high melting point metal oxide layer; a step of forming a silicon layer so as to cover the contact hole and the high melting point metal oxide layer; and a step of forming a silicon layer on the surface of the silicon layer. a step of forming silicon oxide at, and the high melting point metal layer. heat-treating the substrate having the high melting point metal oxide layer, the silicon layer, and the silicon saponification film in an atmosphere containing hydrogen to form internal silicon oxide IIK between the AiIk point metal layer and the silicon layer; A method of manufacturing a semiconductor device, comprising: