JPH0277162A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0277162A JPH0277162A JP149789A JP149789A JPH0277162A JP H0277162 A JPH0277162 A JP H0277162A JP 149789 A JP149789 A JP 149789A JP 149789 A JP149789 A JP 149789A JP H0277162 A JPH0277162 A JP H0277162A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- tungsten
- film
- ion
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 50
- 239000010937 tungsten Substances 0.000 claims abstract description 49
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 42
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 abstract description 23
- 238000000137 annealing Methods 0.000 abstract description 14
- 238000005468 ion implantation Methods 0.000 abstract description 14
- 238000010438 heat treatment Methods 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 239000011229 interlayer Substances 0.000 abstract description 10
- -1 tungsten nitride Chemical class 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 5
- 229910001930 tungsten oxide Inorganic materials 0.000 abstract description 4
- 239000007789 gas Substances 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000010301 surface-oxidation reaction Methods 0.000 abstract description 2
- 230000001546 nitrifying effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 11
- 239000012535 impurity Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は半導体装置の製造方法に関し、詳しくは高融
点ゲート電極を用いたＭＯＳ型半導体素子を打する半導
体装置のイオン注入法による製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application This invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device using an ion implantation method for implanting a MOS type semiconductor element using a high melting point gate electrode. Regarding.
（ロ）従来の技術
従来、例えば集積度の高い半導体装置の製造において、
不純物ドーピングや固体表面の物性制御の際マスクパタ
ーン通りに高精度の選択ドーピングができるイオン注入
法が効果的に用いられている。一方、集積度の向上に伴
いアニーリングや表面平坦化の目的で高温加熱処理が汎
用されるようになっているため、用いる材質にも種々の
制限が生じるようになっている。(b) Conventional technology In the past, for example, in the manufacture of highly integrated semiconductor devices,
When doping impurities or controlling the physical properties of a solid surface, an ion implantation method that allows selective doping with high precision according to a mask pattern is effectively used. On the other hand, as the degree of integration increases, high-temperature heat treatment for the purpose of annealing and surface flattening has become widely used, and various restrictions have also been placed on the materials that can be used.
例えばＦＥＴのゲート電極としては、少なくともイオン
注入処理後のアニール処理（例えば約１０００℃）に耐
える材質が必要であるため融点の高いシリコンが従来使
イつれていた。しかし、最近、半導体装置の微細化と共
に融点が高くかつ比抵抗がより小さい電極材料が求めら
れるようになり、タングステン（Ｗ）、モリブデン（Ｍ
ｏ）、チタン（’Ｌ’ ｉ ）等のメタルゲート電極の
応用が検討されている。低抵抗ゲートとして、タングス
テン／多結晶シリコン（ｎ’−ＰｏｌｙＳ ｉ）構造が
有望であるが、５００〜６００℃以上の熱処理を行うと
Ｗ／ｎ’−ＰｏｌｙＳｉ界而でシリザ面ド化反応が生じ
実用化できない。For example, silicon, which has a high melting point, has traditionally been used as the gate electrode of an FET because it requires a material that can at least withstand annealing treatment (for example, about 1000° C.) after ion implantation treatment. However, recently, with the miniaturization of semiconductor devices, electrode materials with higher melting points and lower resistivity have been required, such as tungsten (W), molybdenum (M
o), applications of metal gate electrodes made of titanium ('L' i ), etc. are being considered. A tungsten/polycrystalline silicon (n'-PolySi) structure is promising as a low-resistance gate, but if heat treatment is performed above 500-600°C, a silica surface conversion reaction occurs in the W/n'-PolySi boundary. It cannot be put into practical use.
そこでシリザイド化反応を防止するために、拡散バリア
となる窒化チタン（ＴｉＮ）膜を用いて、Ｗ ／ Ｔ
ｉＮ ／ ｎ’−ＰｏｌｙＳ １ｌｆｉ造を有するゲー
ト構造が提案されている。Therefore, in order to prevent the silicide reaction, a titanium nitride (TiN) film that acts as a diffusion barrier is used to prevent W/T.
A gate structure with iN/n'-PolyS 1lfi structure has been proposed.
（ハ）発明が解決しようとする課題
しかし、上記タングステンゲート電極を適用してイオン
注入法によりＭＯＳ型半導体素子を形成する半導体装置
°の製造においては、タングステンの結晶構造が柱状に
なっているため、タングステンゲート電極形成後にゲー
ト摺成面よりソース、ドレイン形成用のイオンを照射を
したとき、タングステン結晶構造の隙間をイオンが大き
な衝突もせず結晶内部まで侵入するいわゆるチャンネリ
ングが生じ易く、また照射されたイオンがゲート電極の
中を通過してゲート下地のチャンネル部にまで注入され
、しきい値電圧を狂わす恐れがある。(c) Problems to be Solved by the Invention However, in manufacturing a semiconductor device in which a MOS type semiconductor element is formed by an ion implantation method using the above-mentioned tungsten gate electrode, since the crystal structure of tungsten is columnar, When ions for forming sources and drains are irradiated from the gate sliding surface after forming a tungsten gate electrode, so-called channeling, in which the ions penetrate the gaps in the tungsten crystal structure to the inside of the crystal without large collisions, tends to occur. There is a possibility that the ions passed through the gate electrode and injected into the channel portion under the gate may disturb the threshold voltage.
またゲート電極形成後、この上に通常常圧ＣＶＤ法で層
間絶縁膜（ＮＳＣ，ＮＳＣ／Ｂｌ）ＳＧ等）の形成が行
われているが、この時ゲート電極表面が酸化されて酸化
タングステン（ＷＯ，）が生成する。この後、９００〜
１０００℃程度の高温熱処理（例えばアニール処理）を
行った場合、酸化タングステン自体、高温熱処理に対し
て昇華が起こり、強度もなく非常に不安定である為絶縁
膜との界面、例えばＮＳＧ／Ｗ界面が不安定となり、後
のコンタクト形成工程に支障が生じる不都合があった。Furthermore, after the gate electrode is formed, an interlayer insulating film (NSC, NSC/Bl, SG, etc.) is usually formed on the gate electrode by normal pressure CVD, but at this time the gate electrode surface is oxidized and tungsten oxide (WO) is formed. , ) is generated. After this, 900~
When high-temperature heat treatment (for example, annealing treatment) of about 1000°C is performed, tungsten oxide itself sublimes due to the high-temperature heat treatment, and is very unstable and has no strength, so it may not be strong at the interface with the insulating film, such as the NSG/W interface. This has the disadvantage of causing instability and hindering the subsequent contact forming process.
また上記３層膜、Ｗ／ＴｉＮ／ｎ’−ＰｏｌｙＳｉでは
エツチングが困難である。Furthermore, etching is difficult with the three-layer film W/TiN/n'-PolySi.
この発明は、上記課題を解決するためになされたもので
あり、ゲート電極のエツチングが比較的容易であって、
イオン注入処理時におけるタングステンゲート電極のマ
スク性を向上し、さらに層間絶縁膜形成又はアニール処
理時におけるタングステンゲート電極表面の不安定な酸
化タングステンの生成を防止してコンタクト形成の容易
な半導体装置の製造方法を提供しようとするものである
。This invention was made to solve the above-mentioned problems, and etching the gate electrode is relatively easy.
Manufacture of a semiconductor device that facilitates contact formation by improving the maskability of a tungsten gate electrode during ion implantation processing and further preventing the formation of unstable tungsten oxide on the surface of the tungsten gate electrode during interlayer insulating film formation or annealing processing. It is intended to provide a method.
（ニ）課題を解決するだめの手段
この発明によれば、半導体基板上に絶縁膜を介して少な
くとも表面がタングステンからなるゲート電極を設け、
該ゲート電極の表面を窒化処理した後、このゲート電極
面側からイオン注入処理を行ってゲート電極下部にチャ
ンネル領域を形成することによりＭＯＳ型半導体素子を
構成することを特徴とする半導体装置の製造方法が提供
される。(d) Means for solving the problem According to the present invention, a gate electrode having at least a surface made of tungsten is provided on a semiconductor substrate with an insulating film interposed therebetween,
Manufacture of a semiconductor device characterized in that a MOS type semiconductor element is constructed by nitriding the surface of the gate electrode and then performing ion implantation from the gate electrode surface side to form a channel region under the gate electrode. A method is provided.
この発明においては、まず所定の導電型不純物がドーピ
ングされたＳｉ、ＧａＡｓ等の半導体基板上に絶縁膜を
介してタングステンゲート電極を設ける。In this invention, first, a tungsten gate electrode is provided on a semiconductor substrate of Si, GaAs, or the like doped with impurities of a predetermined conductivity type, with an insulating film interposed therebetween.
絶縁膜は、例えばこの半導体基板を高温の酸化雰囲気中
にさらして酸化膜を成長させるか、あるいはＣＶＤ法に
よって酸化膜を堆積して作製することができる。タング
ステンゲート電極は、この半導体基板上に第２図に示す
ように、例えばスパッタリング法によりタングステン膜
を堆積し、次いで例えば反応性イオンエツチング法によ
り所定パターンにエツチングすることにより形成できる
。The insulating film can be produced, for example, by exposing the semiconductor substrate to a high-temperature oxidizing atmosphere to grow an oxide film, or by depositing an oxide film by CVD. The tungsten gate electrode can be formed by depositing a tungsten film on the semiconductor substrate by, for example, sputtering, and then etching it into a predetermined pattern by, for example, reactive ion etching, as shown in FIG.
このゲート電極の厚さは０．３〜０．５μｍが適してい
る。A suitable thickness of this gate electrode is 0.3 to 0.5 μm.
他の態様として、絶縁膜上にタングステン膜を直接堆積
する代イつりに、第３図に示すようにまずｎｏ−ポリシ
リコン膜８を形成し、この上にＴｉＮ膜９、さらにこの
上にタングステン膜ＩＯを形成しこれをゲート電極とす
ることもできる。すなわち、少なくと６表面がタングス
テンで構成されたゲート電極であればよい。上記６膜の
厚さはそれぞれ０．１〜ＯＪｕｍ、 ０．０１−０．１
μｍ、及び０．１〜ＯＪμｍが適している。またさらに
他の態様としては、絶縁膜上にｉ゛−ポリシリコン膜を
形成し、この上に直接タングステン膜を形成してゲート
電極とすることもできる。この構造のものは上記３層構
造のものに比べてエツチングが比較的簡単に実施できる
点で好ましいものである。As another embodiment, instead of directly depositing the tungsten film on the insulating film, as shown in FIG. It is also possible to form a film IO and use it as a gate electrode. That is, it is sufficient that the gate electrode has at least six surfaces made of tungsten. The thickness of the above six films is 0.1~OJum, 0.01-0.1, respectively.
μm, and 0.1 to OJ μm are suitable. In yet another embodiment, an i-polysilicon film may be formed on the insulating film, and a tungsten film may be directly formed thereon to form the gate electrode. This structure is preferable in that etching can be performed relatively easily compared to the three-layer structure described above.
この発明におけるゲート電極の窒化処理は酸素を排除し
たＮｌｌ３ガス中で加熱して行われる。このときの加熱
温度は６００〜９００℃が適しており、加熱炉としては
電気炉、グラファイトヒータ炉、ランプ加熱炉が用いら
れるが、中でもランプ加熱炉は瞬時加熱が行イっれ酸素
の巻き込み防止に有効であり、高品質の窒化タングステ
ンがタングステンゲート電極の表面に形成されるので好
ましい。このようにして、例えば第４図に示すような半
導体基板か得られる。ここで１は半導体基板、２は絶縁
膜、３はタングステンゲート電極、４は窒化タングステ
ン膜である。The nitriding treatment of the gate electrode in this invention is performed by heating in Nll3 gas from which oxygen is excluded. The suitable heating temperature at this time is 600 to 900°C, and electric furnaces, graphite heater furnaces, and lamp heating furnaces are used as heating furnaces, but among them, lamp heating furnaces perform instantaneous heating to prevent oxygen from being entrained. This method is preferable because it is effective for tungsten gate electrodes and high-quality tungsten nitride is formed on the surface of the tungsten gate electrode. In this way, a semiconductor substrate as shown in FIG. 4, for example, can be obtained. Here, 1 is a semiconductor substrate, 2 is an insulating film, 3 is a tungsten gate electrode, and 4 is a tungsten nitride film.
この発明においては、この後にこのゲート電極面側から
イオン注入処理を行いゲー１ｄ［極上部にチャンネル領
域を形成する。イオン注入処理は通常イオン源にｐＨ３
、ＢＦ３やＡ ｓ Ｈ、などのガスを１Ｏ−３Ｌｏｒｒ
程度導入し、ＤＣやｒｉ Ｆ放電によって生しるプラズ
マ中よりイオンを引き出して半導体基板の所定位置に照
射して行イつれる。このゲート電極面側からイオン照射
を行うと、例えば第５図に示すようにイオンは、絶縁膜
２を通過し、タングステンゲート電極下部はタングステ
ン窒化膜４によって遮閉されて、ドレイン５及びソース
６に相当する部位に的確に注入され、ゲート電極下部は
ほとんど注入されず、ドレイン５とソース６及びそれら
の間のゲート電極の下部にチャンネル領域を形成する。In the present invention, ion implantation is then performed from the gate electrode surface side to form a channel region at the top of the gate 1d. The ion implantation process is usually performed using an ion source with a pH of 3.
, BF3, As H, etc. at 1O-3Lorr
Ions are extracted from plasma generated by DC or RIF discharge and irradiated onto a predetermined position on the semiconductor substrate. When ion irradiation is performed from this gate electrode surface side, the ions pass through the insulating film 2, as shown in FIG. The channel region is formed under the drain 5, the source 6, and the gate electrode between them, with almost no implantation under the gate electrode.
上記のようにして得られたＭＯ６型半導体素子は通常層
間絶縁膜の堆積やアニール処理に付される。ここで層間
絶縁膜は、例えば第１図に示すようにゲート電極の窒化
１漠４の上部周辺に例えばＣＶＤ法によってＳｉｎ、を
堆積して形成される。The MO6 type semiconductor device obtained as described above is usually subjected to interlayer insulating film deposition and annealing treatment. Here, the interlayer insulating film is formed, for example, by depositing Sin around the upper part of the nitride layer 4 of the gate electrode by, for example, the CVD method, as shown in FIG.
またアニール処理は、この層間絶縁膜の堆積後、イオン
注入処理により誘起された照射損傷を除去し、注入不純
物原子を格子位置に導入し電気的に活性化す゛る目的で
行われる。Further, annealing treatment is performed after the interlayer insulating film is deposited for the purpose of removing radiation damage induced by the ion implantation treatment, introducing implanted impurity atoms into lattice positions, and electrically activating the implanted impurity atoms.
しかしこのアニール処理はイオン注入処理後に行えばよ
く、上記層間絶縁膜の形成前に行ってらよい。アニール
処理温度は９００−１０００℃が適している。However, this annealing process may be performed after the ion implantation process, and may be performed before the formation of the interlayer insulating film. A suitable annealing temperature is 900-1000°C.
（ホ）作用
この発明において形成されたタングステンゲート電極表
面の窒化タングステン膜は、イオン注入処理の際照射さ
れ°たイオンを遮閉してチャンネル領域へのイオン注入
を防止する。(E) Function The tungsten nitride film formed on the surface of the tungsten gate electrode in the present invention blocks ions irradiated during ion implantation processing and prevents ions from being implanted into the channel region.
また、この窒化タングステン膜は耐熱性、耐酸化性に優
れているので、ゲート電極上への層間絶縁膜の形成及び
アニール処理の際、タングステンゲート７１極の表面酸
化劣化を防止する。Furthermore, since this tungsten nitride film has excellent heat resistance and oxidation resistance, it prevents surface oxidation deterioration of the tungsten gate 71 electrode during formation of an interlayer insulating film on the gate electrode and annealing treatment.
（へ）実施例
実施例Ｉ
まず、シリコンにホウ素をドープしたＰ型の半導体基板
を高温の酸化雰囲気中にさらし酸化シリコン膜を成長さ
Ｕｏた。次に第２図に示すようにこの酸化シリコン膜（
絶縁膜２）上に、スパッタリングにより厚さ０．４μｍ
のタングステン膜を堆積し、反応性イオンエツチング法
によりタングステンゲート電極３を形成した。得られた
半導体基板をランプ加熱炉に入れ酸素を排除してＮ ｌ
−１３ガス中７００℃で窒化処理をし、第４図に示すよ
うに、タングステンゲート電極上に窒化タングステンｃ
４４を形成した。次に第５図に示すように、タングステ
ンゲート電極面側からＡｓ（ヒ素イオン）をイオン照射
しドレイン５及びソース６を形成した。(F) Examples Example I First, a P-type semiconductor substrate in which silicon was doped with boron was exposed to a high temperature oxidizing atmosphere to grow a silicon oxide film. Next, as shown in Figure 2, this silicon oxide film (
On the insulating film 2), a thickness of 0.4 μm is formed by sputtering.
A tungsten film was deposited, and a tungsten gate electrode 3 was formed by reactive ion etching. The obtained semiconductor substrate is placed in a lamp heating furnace to exclude oxygen and Nl
-13 gas at 700°C, and as shown in Figure 4, tungsten nitride C was applied on the tungsten gate electrode.
44 was formed. Next, as shown in FIG. 5, a drain 5 and a source 6 were formed by irradiating As (arsenic ions) from the tungsten gate electrode surface side.
次にこの半導体基板をＣＶＤ装置に入れ、第１図に示す
ように５ｉＯｚ膜（Ｂ間絶縁膜７）を堆積した。次に、
１０００℃の電気炉中でアニール処理を行い上記イオン
注入処理により誘起された照射損傷を除去し、注入不純
物原子を格子位置に導入し電気的に活性化し、コンタク
ト形成をして半導体装置を製造した。この製造工程にお
いては、ゲート１ｎ極へのコンタクト形成は容易であっ
た。次に得られた半導体装置のゲートに電圧をかけてソ
ース・ドレイン間の電流特性を測定したところ、安定な
特性が得られ、イオン注入処理によるチャンネル領域の
悪影響はなく、タングステンゲート電極の窒化膜によっ
て照射されたイオンが遮閉されていることが確認された
。Next, this semiconductor substrate was placed in a CVD apparatus, and a 5iOz film (B insulating film 7) was deposited as shown in FIG. next,
Annealing treatment was performed in an electric furnace at 1000°C to remove radiation damage induced by the ion implantation process, implanted impurity atoms were introduced into lattice positions, electrically activated, and contacts were formed to manufacture a semiconductor device. . In this manufacturing process, it was easy to form a contact to the gate 1n pole. Next, when voltage was applied to the gate of the obtained semiconductor device and the current characteristics between the source and drain were measured, stable characteristics were obtained, and the channel region was not adversely affected by the ion implantation process, and the nitride film of the tungsten gate electrode It was confirmed that the irradiated ions were blocked by
実施例２
実施例１において、タングステンを堆積する代わりに、
第３図に示すようにｎ゛−ポリシリコン膜８、’ｒｉＮ
ＶＡ９、タングステン膜ＩＯを順次堆積し、この堆積物
を反応性イオンエツチング法でエツチングしてタングス
テンゲート電極を形成する以外は実施例Ｉと同様にして
半導体装置を製造した。Example 2 In Example 1, instead of depositing tungsten,
As shown in FIG.
A semiconductor device was manufactured in the same manner as in Example I except that VA9 and tungsten film IO were sequentially deposited and the deposits were etched by reactive ion etching to form a tungsten gate electrode.
この結果、実施例Ｉと同様にこの製造工程においては、
コンタク；・形成が容易であり、得られた半導体装置は
安定な特性が得られた。As a result, similar to Example I, in this manufacturing process,
Contact: - Easy to form, and the resulting semiconductor device had stable characteristics.
実施例３
ゲート電極がタングステン（Ｗ）膜と多結晶ポリシリコ
ン（ｎ ’−ＰｏｌｙＳ ｉ）との２層膜（Ｒ造からな
る半導体装置の製造方法の一例を、第６図に示す工程説
明図に基づいて説明する。Example 3 An example of a method for manufacturing a semiconductor device in which the gate electrode is made of a two-layer film (R structure) of a tungsten (W) film and a polycrystalline polysilicon (n'-PolySi) is shown in FIG. 6. The explanation will be based on.
ゲート酸化膜（Ｓｉｆｔ）形成後に、多結晶ポリシリコ
ン（ｎ ’−ＰｏｌｙＳ ｉ）およびタングステン（Ｗ
）を堆積しく同図（ａ））、反応性イオンエツチング（
ｒｔｌＥ）により、２層Ｋ （Ｗ／ｎ’−ＰｏｌｙＳ
ｉ）からなるゲート電極を形成する（同図（ｂ））。そ
の後８００〜９００℃の温度で、アンモニア雰囲気中に
てアニーリング処理を行い、窒化層（Ｗ−Ｎ）を形成す
る（同図（Ｃ））。このとき通常の電気炉で行うと酸素
等の巻き込みによりＷＯｔが形成されるために、ランプ
加熱炉を用いるほうがよい。さらにソース・ドレインを
形成するためにＡｓ”（ｎ’）またはＢＦｆｆｉ′（ｐ
゛）を注入しく同図（ｄ））、常圧ＣＶＤ法等により絶
縁膜（ＮＳＣ）を形成した（同図（ｅ））後に、注入し
た不純物（Ａｓ’、 ＢＦ、″）を活性化するために９
５０−１０００℃、 ３０分程度にて窒素ガス雰囲気中
でアニーリング処理に付しく同図（ｒ））、コンタクト
形成して半導体装置を製造した。After forming the gate oxide film (Sift), polycrystalline polysilicon (n'-PolySi) and tungsten (W
) is deposited (see figure (a)), reactive ion etching (
rtlE), the two-layer K (W/n'-PolyS
A gate electrode consisting of i) is formed ((b) in the same figure). Thereafter, an annealing treatment is performed in an ammonia atmosphere at a temperature of 800 to 900° C. to form a nitride layer (W-N) (FIG. 4(C)). At this time, if a normal electric furnace is used, WOt will be formed due to the inclusion of oxygen, so it is better to use a lamp heating furnace. Furthermore, in order to form the source/drain, As''(n') or BFffi'(p
After implanting the impurities (As', BF, '') and forming an insulating film (NSC) by normal pressure CVD (see (e)), the implanted impurities (As', BF, '') are activated. for 9
The semiconductor device was manufactured by annealing in a nitrogen gas atmosphere at 50-1000° C. for about 30 minutes and forming contacts (FIG. 2(r)).
上記のごとく製造された半導体装置には以下に示す特徴
が得られた。The semiconductor device manufactured as described above had the following characteristics.
■ Ｗ／ｎ”−ＰｏｌｙＳ ｉ２２層構造エツチングが
、実施例２におけるＷ／ ’ｒ ｉＮ／ｎ”−Ｐｏｌｙ
Ｓ ｉａ層構造に比べて比較的容易である。■ W/'riN/n''-PolyS i2 two-layer structure etching in Example 2
This is relatively easy compared to the Sia layer structure.
■ Ｗ／ｎ’−ＰｏｌｙＳ ｉ膜をアンモニアガス雰囲
気中でアニーリング処理すると、Ｗ表面が窒化（Ｗ・Ｎ
の形成）されると同時に、Ｎ原子が該膜中を拡散し、Ｖ
Ｊ ／ １”−ＰｏｌｙＳ ｉ界面でＷ−Ｎ、５ｉ−Ｎ
等の窒化膜が形成される。そのために、１０００℃程度
の高温アニーリング処理を行っても、ＷとＳｉの相互拡
散が抑制され、シリサイド層が形成されない。■ When the W/n'-PolySi film is annealed in an ammonia gas atmosphere, the W surface becomes nitrided (W/N
At the same time as the formation of V
W-N, 5i-N at J/1”-PolyS i interface
A nitride film such as the following is formed. Therefore, even if high-temperature annealing treatment at about 1000° C. is performed, mutual diffusion of W and Si is suppressed and no silicide layer is formed.
■ Ｗ＠にＷ−Ｎ＠が形成されることにより、Ｗｈ＜有
する通常の柱状結晶構造が変化し、イオン注入時のマス
ク性が向上するため、不純物のＳｉ基板への貫き抜けが
防止されチャンネリングが防止される。■ By forming W-N@ on W@, the normal columnar crystal structure with Wh ring is prevented.
■ Ｗ膜にＷ−Ｎ膜が形成されることにより、該Ｗｒ１
４上に常圧ＣＶＤ法等によりＮＳＣ膜（４００℃前後）
形成するときの酸化性雰囲気によっても、Ｗ膜の酸化反
応が防止され、Ｗ／Ｎ Ｓ Ｃ界面の特性が安定になる
。■ By forming a W-N film on the W film, the Wr1
4. NSC film (approximately 400°C) is formed on top of 4 by normal pressure CVD method etc.
The oxidizing atmosphere during formation also prevents the oxidation reaction of the W film and stabilizes the characteristics of the W/N SC interface.
（ト）発明の効果
この発明によれば、タングステンゲート電極へのコンタ
クト形成が容易な半導体装置の製造方法を提供すること
ができる。(g) Effects of the Invention According to the present invention, it is possible to provide a method for manufacturing a semiconductor device in which contact formation to a tungsten gate electrode is easy.
この発明によれば、ゲート電圧に対するソース、ドレイ
ン間の電流特性の安定な半導体装置の製造方法を提供す
ることができる。According to the present invention, it is possible to provide a method for manufacturing a semiconductor device with stable current characteristics between a source and a drain with respect to a gate voltage.
この発明によれば、タングステン（Ｗ）層に形成される
窒化膜により、１０００℃程度の高温処理に付してらシ
リサイド層が形成されない耐熱性を有し、またＡＩとＷ
との反応が防止できてＡｌ−８ｉ膜に対するバリア性が
向上され、さらにＮＳＣ／ＢＰ Ｓ Ｇ等の層間絶縁膜
形成時の酸化性雰囲気に対してもＷの酸化反応が防止で
き、安定した電流特性を有する半導体装置を提供するこ
とができる。According to this invention, the nitride film formed on the tungsten (W) layer has heat resistance that prevents the formation of a silicide layer even when subjected to high-temperature treatment at about 1000°C.
This improves the barrier properties against Al-8i films, and also prevents the oxidation reaction of W in the oxidizing atmosphere during the formation of interlayer insulating films such as NSC/BPSG, resulting in stable current flow. A semiconductor device having these characteristics can be provided.
第１図は、この発明の実施例によって製作したＭＯ９型
半導体素子のタングステンゲート電極の説明図、第２図
、第４図、第５図は第１図に示すタングステンゲート電
極を製作する手順を順次示した説明図、第３図は第２図
に相当する（Ｉの態様を示す図、第６図は、この発明の
製造方法の一例を、断面概略図により説明する工程説明
図である。
■・・・・・・半導体基板、 ２・・・・・・絶縁膜、
３・・・・・・タングステンゲート電極、４・・・・・
・窒化タングステン膜、
５・・・・・・ドレイン、 ６・・・・・・ソース
、７・・・・・・層間絶縁膜、
８・・・・・・ｎ゛−ポリシリコン膜、９・・・・・・
’ｒｉＮ膜、 ■０・・・・・・タングステン膜。
ＷＫ１ｖ！Ｊ 第２図（ｅ）FIG. 1 is an explanatory diagram of a tungsten gate electrode of an MO9 type semiconductor device manufactured according to an embodiment of the present invention, and FIGS. 2, 4, and 5 show the steps for manufacturing the tungsten gate electrode shown in FIG. 1. The explanatory drawings shown in sequence, FIG. 3, correspond to FIG. 2 (a drawing showing the aspect of I, and FIG. 6 are process explanatory drawings illustrating an example of the manufacturing method of the present invention using schematic cross-sectional views. ■... Semiconductor substrate, 2... Insulating film,
3...Tungsten gate electrode, 4...
・Tungsten nitride film, 5...Drain, 6...Source, 7...Interlayer insulating film, 8...N-polysilicon film, 9...・・・・・・
'riN film, ■0...Tungsten film. WK1v! J Figure 2 (e)
Claims (1)
ングステンからなるゲート電極を設け、該ゲート電極の
表面を窒化処理した後、このゲート電極面側からイオン
注入処理を行ってゲート電極下部にチャンネル領域を形
成することによりＭＯＳ型半導体素子を構成することを
特徴とする半導体装置の製造方法。1. A gate electrode whose at least the surface is made of tungsten is provided on a semiconductor substrate via an insulating film, and after the surface of the gate electrode is nitrided, ions are implanted from the gate electrode surface side to form a channel at the bottom of the gate electrode. A method of manufacturing a semiconductor device, comprising forming a MOS type semiconductor element by forming regions.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-138156 | 1988-06-03 | ||
| JP13815688 | 1988-06-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0277162A true JPH0277162A (en) | 1990-03-16 |
| JPH0748562B2 JPH0748562B2 (en) | 1995-05-24 |
Family
ID=15215330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP149789A Expired - Fee Related JPH0748562B2 (en) | 1988-06-03 | 1989-01-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0748562B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015754A (en) * | 1999-06-16 | 2001-01-19 | Hyundai Electronics Ind Co Ltd | Method for forming conductive line of semiconductor device |
| US6333250B1 (en) | 1998-12-28 | 2001-12-25 | Hyundai Electronics Industries Co., Ltd. | Method of forming gate electrode in semiconductor device |
| US6340629B1 (en) | 1998-12-22 | 2002-01-22 | Hyundai Electronics Industries Co., Ltd. | Method for forming gate electrodes of semiconductor device using a separated WN layer |
| US6468914B1 (en) | 1998-12-29 | 2002-10-22 | Hyundai Electronics Industries Co., Ltd. | Method of forming gate electrode in semiconductor device |
| EP1298710A1 (en) * | 2001-09-07 | 2003-04-02 | Infineon Technologies AG | Method for protecting a tungsten element in semiconductor device fabrication |
| KR100393964B1 (en) * | 2000-12-18 | 2003-08-06 | 주식회사 하이닉스반도체 | Method of forming Gate of SRAM Device |
| JP2004080011A (en) * | 2002-07-09 | 2004-03-11 | Samsung Electronics Co Ltd | Method of manufacturing semiconductor device including silicon oxide layer |
| JP2010109385A (en) * | 2010-01-14 | 2010-05-13 | Foundation For Advancement Of International Science | Method for manufacturing semiconductor device |
-
1989
- 1989-01-06 JP JP149789A patent/JPH0748562B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6340629B1 (en) | 1998-12-22 | 2002-01-22 | Hyundai Electronics Industries Co., Ltd. | Method for forming gate electrodes of semiconductor device using a separated WN layer |
| US6333250B1 (en) | 1998-12-28 | 2001-12-25 | Hyundai Electronics Industries Co., Ltd. | Method of forming gate electrode in semiconductor device |
| US6468914B1 (en) | 1998-12-29 | 2002-10-22 | Hyundai Electronics Industries Co., Ltd. | Method of forming gate electrode in semiconductor device |
| JP2001015754A (en) * | 1999-06-16 | 2001-01-19 | Hyundai Electronics Ind Co Ltd | Method for forming conductive line of semiconductor device |
| KR100393964B1 (en) * | 2000-12-18 | 2003-08-06 | 주식회사 하이닉스반도체 | Method of forming Gate of SRAM Device |
| EP1298710A1 (en) * | 2001-09-07 | 2003-04-02 | Infineon Technologies AG | Method for protecting a tungsten element in semiconductor device fabrication |
| JP2004080011A (en) * | 2002-07-09 | 2004-03-11 | Samsung Electronics Co Ltd | Method of manufacturing semiconductor device including silicon oxide layer |
| JP4493295B2 (en) * | 2002-07-09 | 2010-06-30 | 三星電子株式会社 | Method for manufacturing a semiconductor device including a silicon oxide layer |
| JP2010109385A (en) * | 2010-01-14 | 2010-05-13 | Foundation For Advancement Of International Science | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0748562B2 (en) | 1995-05-24 |
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