TW558755B - Method of forming multiple oxide layers with different thicknesses in a linear nitrogen doping process - Google Patents

Abstract

Multiple oxide layers with different thicknesses are formed on a semiconductor substrate with a silicon surface, having a first and second region. A sacrificial oxide layer is formed on the silicon surface to cover both the first region and the second region, with a mask layer formed on the surface of the sacrificial oxide layer. By defining and patterning the mask layer, a first opening and a second opening, having predetermined surface areas, are formed in portions of the first and second regions of the mask layer to expose portions of the. The sacrificial oxide layer has a surface area equal to the first predetermined surface area, and portions of the sacrificial oxide layer having a surface area equal to the second predetermined surface area. A linear nitrogen doping process is then performed to simultaneously implant nitrogen ions with a first and second predetermined concentration into the first and second region, through the first opening and the second opening, respectively. Thereafter, the mask layer and the sacrificial oxide layer are removed, respectively. An oxidation process is performed to two silicon oxide layers with different thicknesses in the first and second regions.

Description

558755 V. Description of the invention (1) Field of the invention The present invention provides a method for forming oxide layers with different thicknesses at the same time, especially a method using a linear nitrogen ion implantation (丨 ear nitrogen doping) and a single oxidation process on a semiconductor substrate. Method for simultaneously forming oxide layers of different thicknesses. Background: With the development of high-density wafers and the emergence of system-on-chip (S0C), there are more and more integrated circuits that require two or more than two. Gate oxide layers with different thicknesses to meet different operating voltage components. For example, the operating voltage of a general flash memory (f 1 ash memory) memory cell is 3.3 volts, while its peripheral circuit requires 5 volts. Therefore, in addition to the longer gate channel of the peripheral circuit, the gate oxide layer is relatively thicker than the free oxide layer in the memory cell circuit to avoid electrical breakdown caused by high voltage. In addition, in general read only memory (ROM), two or more gate oxide layers with different thicknesses are often required. There are several ways to make oxide layers with different thicknesses. Among them, in 1993, an invention patent by Nakata et al. (U. S. Pat. No. 5, 254, 489) disclosed a method for fabricating gate oxide layers with two different thicknesses'. please

558755

ί ϊ:: A to FIG. 1 D ’FIG. 1 A to FIG. 1 are schematic cross-sectional views of methods disclosed in the above patents for different thicknesses of open electrode oxide layers. As shown in the figure, the surface of the semiconductor substrate 1 includes two semiconductor substrates in each area separated by the insulating layer 2. There is a first on the surface of the semiconductor substrate 1. The first oxide layer 3 is well known to those skilled in the art. The method is as follows: Dry oxygen in a pure oxygen environment at 800 to 5 ° C is shown in Figure 1B, followed by a nitrogen or ammonia gas environment. Nitriding the surface of the semiconductor substrate 1 to form a nitrided oxide layer (!) 6. Among them, the nitriding temperature in a nitrogen environment is about 1000 to 12 00 ° C, and the nitriding temperature in an ammonia gas environment is about 900 to 5500 ° C. Next, as shown in FIG. 1C, a photoresist layer 4 is used to shield the nitrided oxide layer 6 that is not to be removed, and an argon fluoride acid solution is used to remove the nitrided oxide layer 6 'not covered by the photoresist layer 4. A part of the surface of the semiconductor substrate is exposed. Finally, as shown in FIG. 1D, an oxidation process is performed to form a thicker oxide layer 5 on the surface of the bare semiconductor substrate i. However, the above-mentioned method of separately forming an oxide layer by using a shielding method has several major problems. First of all, the use of a shielding layer is liable to cause pollution, making the quality of the gate oxide layer requiring high quality unstable, and the quality of the nitrided gate oxide layer is inferior to that of the pure silicon oxide layer. Secondly, the emulsified layer provided under the shielding layer will still undergo oxidation in other areas.

558755

Slight oxidation occurs, and the conventional method is too time consuming, especially when the semiconductor layer is used. SUMMARY OF THE INVENTION Making the gate oxide layer thicker than a few layers is not only unsuitable for use in high-yield substrates, which requires three degrees of control problems. At least two light forces are required. The semiconductor process can make the gate oxides of different thicknesses quickly and stably form a failure rate. Therefore, the object of the present invention is to provide a method for forming a thick oxide layer together to obtain a high product yield. Another object of the present invention is to provide a method that requires only one linear nitrogen doping and one oxidation process. The method of simultaneously forming oxide layers of different thicknesses on a semiconductor substrate can precisely control the thickness of the oxide layers. The method of the present invention includes a lower substrate, wherein the semiconductor substrate includes a first region and a first oxide sacrificial layer, covering the first, and (3) the surface layer of the oxide sacrificial layer is respectively located on the first substrate. A region and the first opening of the predetermined area are exposed to the surface of the sacrificial layer, and a plurality of second steps) (1) providing a semiconductor with a silicon surface, and the silicon surface to two regions, (2) in The silicon surface is shaped into two regions and a masking layer in the second region, wherein the masking second region includes an average score of the second openings having the first predetermined area and the predetermined predetermined oxidation area.

558755 V. Description of the invention (4) Disposed on the second area and exposing the surface of the oxide sacrificial layer the same as the second predetermined area, (4) Performing a nitrogen ion implantation process through the first opening And the second opening is implanted with a first predetermined concentration of nitrogen ions and a second predetermined concentration of nitrogen ions on the silicon surface in the first region and the second region, respectively, (5) removing the mask layer (6) removing the oxidation sacrificial layer, and (7) performing an oxidation process, and simultaneously forming a first predetermined thickness and a second predetermined thickness on the silicon surface in the first region and the second region, respectively. Silicon oxide layer. -Wherein, the nitrogen ion implantation system is a linear nitrogen ion implantation process and adheres to the following relational formula, where k is a constant: (the first predetermined area / the second predetermined area) = k ( The first predetermined concentration / the second predetermined concentration). In a preferred embodiment of the present invention, the first predetermined area is larger than the second predetermined area, the first predetermined concentration is larger than the second predetermined concentration, and the first predetermined thickness is smaller than the second predetermined thickness. Detailed description of the invention Please refer to FIG. 2A and FIG. 2B. FIG. 2A and FIG. 2B are schematic diagrams of a linear nitrogen doping profile of the present invention. As shown in FIG. 2A, the present invention precedes the surface of a semiconductor substrate 10

558755 V. Description of the invention (5) A photoresist layer 12 is formed on _____, and a nitrogen ionization conductor substrate 10 surface is obtained to obtain a linear nitrogen ionization ^ 20 ^ with openings 21, 22, and 23 of different areas in the half, respectively The second layer 12 and A3, and AP Al, are used to divide the semiconductor substrate 10 with the area of If f area A 丨 and a2. "The same surface below each opening is shown in Figure 2B. 'The horizontal axis is generated by the linear nitrogen tempering process.' The vertical axis represents the implantation ion doping concentration. The results show that at the same dose, the nitrogen ion implantation measured by the secondary ion implantation (Secondary Ion Mass, SIMS) on the surface of the semiconductor substrate 10 (VC and CO and the opening area (Αρ A And M) are linearly related. The degree of value A 1: A y A C!: C 2: C π plus nitrogen as implanted in the semiconductor substrate 10 will be suppressed (depress ) The growth rate of oxygen ions is different. Therefore, the present invention is to use the linear relationship between the concentration of nitrogen ions and the product of 9 ′ and the mechanism of nitrogen ion suppression to effectively control the growth of the two-layer surface layer, and Simplify the manufacturing process of the conventional method. Please refer to Figure 3A to Figure 3D for oxidation. Figure 3A to Figure D are schematic cross-sectional diagrams of the present invention for making oxide layers with different thicknesses on a plate ητ ^ 30. See Figure 2. No. In a preferred embodiment of the present invention, the SOI substrate 30 is a Λ, S, a commercial product formed including a P-type semiconductor silicon layer = 1 micron and an insulating layer (not shown) )., '· From' formed

558755 V. Description of the invention (6) The detailed steps of the SO I substrate 30 are not the focus of the present invention, so they will not be repeated here. The first step of the present invention is to first perform an isolation process, and use an insulating layer 32 to electrically isolate the active areas 36 and 38. This isolation process is a technique well known to those skilled in the art, such as 10-calized oxidation on si 1 icon (LOCOS). An oxide sacrifice layer 3 4 with a thickness of about several tens to several hundreds angstroms (A) is then formed on the active regions 36 and 38 on the SOC substrate 30, preferably between 150 and 250 angstroms. between. In a preferred embodiment of the present invention, the oxidation sacrificial layer 34 is formed by a dry thermal oxidation lambda method in a pure oxygen environment of 900 to 110 ° C. In addition, the present invention is not limited to SO I Application of substrates, other semiconductor substrates, such as silicon substrates, are also included in the scope of application of the present invention. As shown in FIG. 3B, a yellow light technology (ithography) is then used to form a surface on the surface of the oxide sacrificial layer 34. Patterned photoresist layer 4 0. The photoresist layer 40 includes a plurality of openings 4 of the same area a, which are evenly distributed on the oxidation sacrificial layer 34 in the active region 36, and an opening having an area μ. 42 exposes the active area 38. It should be emphasized that the area error of the opening 41 must be controlled to the minimum range to achieve the maximum reliability. Next, a nitrogen ion implantation process 50 is performed, and N + or N 2 ions are passed through The openings 41 and 42 are implanted into the shallow surface of the SOI substrate 30 through the sacrifice layer 34 to form a shallow surface nitrogen ion distribution 52 and 54. This nitrogen ion cloth is made

$ 11 pages 558755 V. Description of the invention (7) The nitrogen ion energy used in Cheng 50 is about 10 to 40 KeV, preferably 30 KeV, and the implantation dose is about 1E14 to 1E16 atoms per square centimeter (atoms / cm2 ), The nitrogen ion implantation process 50 takes about several minutes to several tens of minutes. It is worth noting that the implanted shallow surface nitrogen ion distribution 5 2 and 54 are closer to the interface between the oxide sacrificial layer 34 and the SOI substrate 30, so the nitrogen ion energy needs to be appropriately adjusted according to the thickness of the oxide sacrificial layer 34. . Then, the photoresist layer 40 is completely removed in an oxygen plasma environment. As shown in FIG. 3C, after removing the photoresist layer 40, the SOI substrate 30 subjected to nitrogen ion implantation is then subjected to an annealing process at 950 ° C for about 5 to 15 minutes to implant the The lateral diffusion of nitrogen ions on the shallow surface of the SOI substrate 30 tends to enter the SOI substrate 30. It should be emphasized that the reaction time and temperature of the tempering process may be changed according to circumstances, such as the amount of implanted nitrogen ions and the heating rate of the RT A reactor. Basically, the temperature of the tempering process is between 75 and 110 ° C, and the tempering time is between about 1 and 1000 minutes. After the tempering process, as a result, a shallow surface of the SOI substrate 30 near the oxidized sacrificial layer 34 in the active region 36 will form a nitrogen ion diffusion region 62 '. The shallow surface of the SOI substrate 30 near the oxidized sacrificial layer 34 in the active region 38 will be formed. There is a nitrogen ion diffusion region 64, in which the nitrogen ion roll in the nitrogen ion diffusion region 64 is greater than the nitrogen ion concentration in the nitrogen ion diffusion region 62. As mentioned previously, when the nitrogen ion implantation is accurately controlled, the opening area in the photoresist layer 40 is large, and the nitrogen ion concentration in the nitrogen ion diffusion region 64 and the nitrogen ion diffusion region 62 is

Page 12 558755

5. Description of Invention (8) Both can be controlled. In addition, since the ion energy implanted during the nitrogen ion implantation is the same, the maximum vertical concentration distribution depth is fairly close in the nitrogen ion diffusion region 64 and the nitrogen ion diffusion region 62. Taking the nitrogen ion implantation energy of 30 KeV and the thickness of the oxide sacrificial layer 34 as about 200 angstroms as an example, the maximum nitrogen ion concentration vertical distribution depth of the shallow surface of the SOI substrate 30 is about 30 to 50 angstroms. As shown in FIG. 2D, a thermal oxidation process is performed on the SO I substrate 30 to form a gate oxide layer in the active regions 36 and 38. This thermal oxidation process is performed at a dry or wet oxygen environment at a temperature of 750 to 1000 ° C for 10 minutes to about 2 hours, preferably at a temperature of 8500 ° C. 2 hours of dry pure oxygen oxidation. As a result, a thicker gate oxide layer 72 was formed on the surface of the SOI substrate 30 in the active region 36 and a thinner gate oxide layer was formed on the surface of the soI substrate 30 in the active region 38. 74. The thickness of the gate oxide layer is between 20 and 150 angstroms, and the thickness of the gate oxide layer 74 is between 20 and 120 angstroms. As mentioned above, since the nitrogen ions implanted on the surface of the 〇〇substrate 30 have a tendency to inhibit the surface oxidation rate of the SO I substrate 30, and the strength of the growth rate of the gate oxide layer is inhibited and the strength of the implanted SiO substrate 3 The nitrogen ion concentration on the surface is related, so the thickness of the gate oxide layer to be formed can be controlled by controlling the implanted nitrogen ion concentration.

Refer to FIG. 4 and FIG. 4B. FIG. 4a and FIG. 4B are schematic cross-sectional views of another embodiment of the present invention. The steps before removing the photoresist layer, including the photoresist layer 40 coating, exposure and development, and nitrogen ion implantation process 50, are the same as the aforementioned preferred embodiments, and are not repeated here. Figure 4A shows the bottom

Page 13 558755 V. Description of the invention (9) 30 After the photoresist layer 40 is removed, the SO I substrate 3 0 that has been implanted with nitrogen ions is subjected to a 9 5 0 ° C return for about 5 to 15 minutes. In the fire process, the lateral diffusion of nitrogen ions implanted on the shallow surface of the SO I substrate 30 is directed to the SO I substrate 30, and a diffusion region 62 is formed in the active region 36 and a diffusion is formed in the active region 38. 6 4. In this embodiment, the S 0 I substrate 30 is then subjected to a wet after-etching process, using a diluted hydrofluoric acid solution to remove the oxide sacrificial layer in the active region 36 and the active region 38 (not shown). . Next, as shown in FIG. 4B, similarly, a thermal oxidation process is performed on the S 0 I substrate 30 to form a gate oxide layer in the active regions 36 and 38. This thermal emulsification process is carried out in a dry or wet oxygen environment at a temperature of between 750 to 1000C for 10 minutes to about 2 hours, preferably a dry pure for about 2 hours at a temperature of 850 ° C. Oxygen oxidation. As a result, a thicker gate oxide layer 72 was formed on the surface of the soj substrate 30 in the active region 36 and a thinner gate oxide layer was formed on the surface of the SO I substrate 30 in the active region 38. 74. The thickness of the gate oxide layer is between 20 and 150 Angstroms, and the thickness of the gate electrode layer 74 is between 20 and 120 Angstroms. Compared with the conventional manufacturing method, the features of the present invention can be as follows: (1) Only one nitrogen ion implantation process and one thermal oxidation process are needed; (2) using a thermal oxidation process to form gates of different thicknesses at the same time Floor;

558755 V. Description of the Invention (ίο) (3) Gate oxide layers of different thicknesses can be effectively controlled; (4) The quality of the gate oxide layer formed is better than that formed by conventional techniques; and (5) the process is simplified save time. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 15 558755 Brief description of the diagrams Brief description of the diagrams Figures A to D show cross-sectional schematic diagrams of two conventional methods for manufacturing gate oxide layers with different thicknesses. Figures 2A and 2B are schematic diagrams showing the outline of linear nitrogen ion implantation according to the present invention. 3A to 3D are schematic cross-sectional views of a preferred embodiment of the present invention. Figures 4A and 4B are schematic sectional views of another embodiment of the present invention. Explanation of symbols in the figure 1 semiconductor substrate 2 insulating layer 3 first oxide layer 4 photoresist layer 5 oxide layer 6 nitride oxide layer 10 semiconductor substrate 12 photoresist layer 20 nitrogen ion implantation 2 22-22 23 V 30 SOI substrate 32 Insulating layer 34 Oxidation sacrificial layer 36 ^ 38 Active region 40 Photoresist layer 4 2 42 D 50 Nitrogen ion arrangement process 52 ^ 54 Nitrogen ion distribution 62, 64 Nitrogen ion diffusion region Ί2, 74 Gate oxide layer

Claims (1)

558755 Semiconductor plutonium :: with; and -sub-oxidation ... = ... and the surface of the stone eve at least contains -th-乂 and the first region, the method includes the following steps: and the = into a sacrifice of oxide to cover the first- A region is formed with a mask layer on the surface of the sacrificial sacrificial layer; the masking layer is defined and patterned so that the masking reed includes a first pre-product in the first region and the second region, respectively. A first opening and a second opening of a second predetermined area, the first hole exposing the surface of the oxide sacrificial layer that is the same as the first predetermined area, and the second opening is exposed to the second predetermined area The same area of the sacrifice of oxidation; the surface; that is, a linear nitrogen ion implantation process is performed, and a first region and a second region are implanted in the first region and the second region with a first A predetermined concentration of nitrogen ions and a second predetermined concentration of nitrogen ions, where (the first predetermined area / the second predetermined area first predetermined concentration / the second predetermined concentration), the k value is a constant; remove the Mask layer Oxidizing the sacrificial layer; and performing an emulsification process, and simultaneously forming a silicon oxide layer of a first predetermined thickness and a second pre-thickness on the silicon surface in the first region and the second bar region, respectively. & 558755 VI. Patent Application Range 2. The method of applying for the first item of the patent scope, wherein the first predetermined area is larger than the second predetermined area 'the first predetermined concentration is greater than the second predetermined concentration, and the first predetermined thickness is less than The second predetermined thickness. 3. The method according to item 1 of the patent application, wherein the thickness of the sacrifice oxide layer is between 150 and 250 angstroms (angstrom, A). 4. The method according to item 1 of the patent application, wherein the shielding layer is a photoresist layer. Round of Fan Lizhuan. Please refer to Di Shenji as a method of item 5 in which the semiconductor substrate is 6. The method of item 1 in the scope of patent application where the semiconductor substrate is a silicon-on-insulator (SOI) Substrate. 7. The method according to item 1 of the scope of patent application, wherein the nitrogen ion system used in the nitrogen ion implantation process is N2 +, its energy is about 30KeV, and the dose is about lE14cnr2 to iE16cm_ ^ :. 8. A method of forming oxide layers of different thicknesses at one time, the method comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a silicon surface 'and the silicon surface includes at least a first region and a second region; Page 18 558755 6. The scope of the patent application forms a sacrificial oxide layer on the silicon surface, covering the first region and the second region; forming a shielding layer on the surface of the sacrificial oxide layer, wherein the shielding layers are respectively A first opening having a first predetermined area in the first region and the second region exposes the surface of the oxide sacrificial layer the same as the first predetermined area, and a plurality of second openings having a second predetermined area. Is evenly distributed on the second area and exposes the surface of the oxide sacrificial layer the same as the second predetermined area; a nitrogen ion implantation process is performed, and the first openings and the second openings are respectively formed in the first Implanting a first predetermined concentration of nitrogen ions and a second predetermined concentration of nitrogen ions on the silicon surface in a region and the second region; removing the mask layer; removing the oxidation sacrificial layer; and performing an oxidation process, At the same time, a silicon oxide layer with a first predetermined thickness and a second predetermined thickness is formed on the silicon surface in the first region and the silicon surface in the second region, respectively. 9. The method according to item 8 of the patent application, wherein the first predetermined area is larger than the second predetermined area, the first predetermined concentration is larger than the second predetermined concentration, and the first predetermined thickness is smaller than the second predetermined thickness. 10. The method according to item 8 of the scope of patent application, wherein (the first predetermined area / the second predetermined area) = k (the first predetermined concentration / the second predetermined concentration Page 19 558755 VI. Range of patent application), k value is a constant. 11. The method of claim 8 in which the thickness of the oxide sacrificial layer is between 150 and 25 angstroms (angstrom, A). 1 2. The method according to item 8 of the patent application, wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate. 1 3. The method according to item 8 of the patent application, wherein the shielding layer is a photoresist layer. 14. The method according to item 8 of the scope of patent application, wherein the nitrogen ion system used in the nitrogen ion implantation process is N2 +, its energy is about 30KeV, and the dosage is between lE14cm-2 to lE16cm ~. Page 20