JPS58170121A - 2進数値チェック回路装置 - Google Patents
2進数値チェック回路装置Info
- Publication number
- JPS58170121A JPS58170121A JP58012098A JP1209883A JPS58170121A JP S58170121 A JPS58170121 A JP S58170121A JP 58012098 A JP58012098 A JP 58012098A JP 1209883 A JP1209883 A JP 1209883A JP S58170121 A JPS58170121 A JP S58170121A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- binary
- output
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims description 9
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- 238000011156 evaluation Methods 0.000 claims 1
- 235000009508 confectionery Nutrition 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- GGWBHVILAJZWKJ-UHFFFAOYSA-N dimethyl-[[5-[2-[[1-(methylamino)-2-nitroethenyl]amino]ethylsulfanylmethyl]furan-2-yl]methyl]azanium;chloride Chemical compound Cl.[O-][N+](=O)C=C(NC)NCCSCC1=CC=C(CN(C)C)O1 GGWBHVILAJZWKJ-UHFFFAOYSA-N 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3202543.2 | 1982-01-27 | ||
| DE83100394.2 | 1983-01-18 | ||
| EP83100394A EP0084843B1 (en) | 1982-01-27 | 1983-01-18 | Programmable circuit arrangement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58170121A true JPS58170121A (ja) | 1983-10-06 |
| JPH0354488B2 JPH0354488B2 (enExample) | 1991-08-20 |
Family
ID=8190241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58012098A Granted JPS58170121A (ja) | 1982-01-27 | 1983-01-27 | 2進数値チェック回路装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58170121A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150599A (ja) * | 1985-12-24 | 1987-07-04 | Nec Corp | メモリ回路 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4157480A (en) * | 1976-08-03 | 1979-06-05 | National Research Development Corporation | Inverters and logic gates employing inverters |
-
1983
- 1983-01-27 JP JP58012098A patent/JPS58170121A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4157480A (en) * | 1976-08-03 | 1979-06-05 | National Research Development Corporation | Inverters and logic gates employing inverters |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150599A (ja) * | 1985-12-24 | 1987-07-04 | Nec Corp | メモリ回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0354488B2 (enExample) | 1991-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0287337B1 (en) | Programming circuit for programmable logic array i/o cell | |
| KR890005156B1 (ko) | 반도체 기억장치 | |
| US6373762B2 (en) | Programmable voltage divider and method for testing the impedance of a programmable element | |
| US6970794B2 (en) | Semiconductor having reduced configuration pins and method thereof | |
| CA1083671A (en) | Electrical identification of multiply configurable circuit array | |
| US4740919A (en) | Electrically programmable logic array | |
| KR960005361B1 (ko) | 용장 디코더 회로 | |
| US4449203A (en) | Memory with reference voltage generator | |
| US5452229A (en) | Programmable integrated-circuit switch | |
| JPH05299606A (ja) | 半導体メモリ装置及びそのビット線の短絡救済方法 | |
| US5469379A (en) | Multi-level vROM programming method and circuit | |
| JPS5856286B2 (ja) | 出力バッファ回路 | |
| JPS58170121A (ja) | 2進数値チェック回路装置 | |
| US4815022A (en) | Programmable logic array for carrying out logic operations of binary input signals | |
| US3422283A (en) | Normal and associative read out circuit for logic memory elements | |
| JPS6010392B2 (ja) | 2ポ−ト・ランダム・アクセス・メモリ素子 | |
| JPS60111397A (ja) | 集積回路メモリ | |
| EP0084843B1 (en) | Programmable circuit arrangement | |
| US3487383A (en) | Coincident current destructive read-out magnetic memory system | |
| US3548389A (en) | Transistor associative memory cell | |
| JP6586398B2 (ja) | オプションコード供与回路及びその供与方法 | |
| JPS63107000A (ja) | プログラマブル・リ−ド・オンリ−・メモリ | |
| JPS5951021B2 (ja) | 論理演算装置 | |
| JPH0492292A (ja) | 半導体集積記憶回路装置 | |
| JPS63177397A (ja) | 半導体集積回路装置 |