JPS58169977A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To obtain a transistor without strains in the curve of voltage and current between a source and a drain by a method wherein N<+> layers of unnecessary parts are removed by a lift-off method, when the source region and the drain region constituted of the N<+> layers are formed. CONSTITUTION:A thin films Si layer 102 is grown on a substrate 101 constituted of glass, ceramic, etc., than an Mo layer 103 is adhered thereon, and unnecessary parts thereof are removed by a photo etching, accordingly the remnant layers 103 are turned as the mask for lift-off. Next, the N<+> layers 104-2 and 104-1 are grown while breaking off on and between the masks, then the masks are lifted off with the N<+> layers 104-2 thereon, and accordingly the N<+> layers 104 at a fixed interval are made to remain on the Si layer 102. Thereafter, the source electrode 106 and the drain electrode 107 constituted of Mo are formed on the N<+> layers 104-1, and a gate electrode 113 is provided therebetween via a gate insulation layer 109.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thin film transistor having a thin film semiconductor layer based on silicon.
A thin film transistor having a gate coplanar type structure has a gate insulating layer provided on the surface opposite to the substrate of a thin film-like semiconductor layer having a silicon matrix provided on a substrate. at a constant voltage (V
s) is applied and the voltage (VD) between the source and drain electrodes is varied (t-), the current (l o ) flowing between the source and drain electrodes is #i changes into envy, but shows no tendency to increase.

However, the 1*Vo-1o characteristic does not become a winning type in the case of a small chain acid with 0, but the Vo-1o'% characteristic distortion becomes φ, and the transistor does not exhibit favorable transistor characteristics.

The cracking is caused by insufficient ohmic contact between the semiconductor layer made of thin silicon and the electrode.

+4 in an attempt to resolve this! J half-4 body layer and 111m1 (pole (source electrode, drain ″1τ−)
It has been proposed that +r-Kanai, which uses silicon as a matrix, be present between the two.

In order to form the n-layer, it is necessary to dope a Kn-type impurity into the silicon-based layer (71).

However, as a method of doping unpure %J into this silicon, the thermal diffusion and If ion immersion irradiation is used, both require heat treatment at a temperature of 900°C or higher, so glass substrates are used, and films are formed at relatively low temperatures. II&'
It is unsuitable for the 2D and 3T manufacturing process.

For this reason, in the past, glow discharge (GD) method, Hibachième deposition (HVD) method, I! It has been proposed as a normal method to remove one layer of the semiconductor layer and leave the n-layer only at the interface between the source and drain electrodes and the semiconductor layer. Selective etching with layers is required. However, since both the n-layer and the semiconductor layer are based on silicon, it is currently extremely difficult to increase the selective etching ratio using either wet etching or dry etching. As a result, since the selective etching ratio was not large, when etching the n-layer, the underlying semiconductor layer was also etched in all directions, causing roughness. It is difficult to control the amount of etching on the surface.

As a result of the above, it has been extremely difficult to produce thin film transistors with stable characteristics with good reproducibility.

The object of the present invention is to provide a method for manufacturing a thin film transistor having the above-described structure, which eliminates the drawbacks of the conventional method by removing unnecessary portions of the n-layer without selectively etching the n-layer and the semiconductor layer. It is to make a proposal.

A method for manufacturing a thin film transistor according to the present invention includes: a thin film-like semiconductor layer provided on a substrate and having a silicon body; a source region layer provided on the semiconductor layer and composed of a single layer made of silicon; a drain region layer, a gate insulating layer disposed on the semiconductor layer in a portion between the source region layer and the drain region layer, a gate electrode provided on the gate insulating layer, and a gate electrode provided on the source region layer. In a method for manufacturing a thin film transistor having a structure including a source electrode with 8 digits and a drain electrode provided on the drain region layer, the n-layer is patterned to form the source region and the drain region. When using the lift-off method,
1Isf) Removal of the n layer is considered a 4I feature.

The thin film transistor produced by the method of the present invention is
Based on this point, We -to
! It exhibits favorable transistor characteristics with no compromise in performance.

Hereinafter, the present invention will be specifically explained with reference to Figure 1iK. This is a process diagram.

In the first embodiment, first, as shown in step -), a thin film-like semiconductor layer 102 made of silicon, which is known in the art, is formed on a substrate 101 made of glass, ceramic, or the like. Thereafter, a Mo layer 103 having a thickness of about 100 nm is formed by vapor deposition on the surface of the semiconductor layer 102 using a vapor deposition technique such as an electron beam vapor deposition method [step (b)]. Subsequently, unnecessary portions of the moving layer 106 are removed by a normal photoetching technique (step (c)), and the remaining portion of the Mo layer 103 is used as a mask for lift-off.

Next, approximately 0
．． Form n-layers 104-1 and 104-2 with a thickness of one tone [
Step (d)]. After that, phosphoric acid (85% water IW liquid) and steelmaking acid (60% water full 1% K)! Glacial acetic acid: Dried water-25!1
:5=4 (capacity ratio) (Erachan) 1) The member obtained in step (d) was immersed in the solution at a temperature of 50° C. for a specified period of time to remove the etching solution on the semiconductor layer 102. After dissolving the existing layer 103, ultrasonic cleaning (125 W, 50 Hz) is performed for about 10 minutes while the MO layer 103 remains immersed in water, and then washed with water to form on the MO layer 103. Lift off the n-layer 104-1. In this way, the n-layer 104-1 is applied only to the necessary portions of the semiconductor layer 102.
[Step (C)]. After that, Noble Mo is evaporated,
The MO layer 105 is formed to have a thickness of about 0.1 mm [step (f)].
, using the above-mentioned etchant I, leaving the Mo layer only on the 0th floor 104-i, and forming the source electrode 106. A drain electrode 107 is formed [Step (g)].

Next, using the well-known QD method, under desired conditions, the silicon nitride layer 108 is made approximately 0.3 cm thick and the gate insulating layer 1 is formed.
09 [Step (h)]. Next, add 20 Hs to C8.
The silicon nitride layer 108 is etched using a parallel plate plasma etching apparatus using a mixed gas containing
A selective dry etching process is performed on the source electrode 106. Contact hole 11 for drain electrode 107
0 and 111 are formed respectively (Step 11(i)). After that, by electron beam evaporation method, AI was evaporated to approximately 0.6
The Aj layer 112 is formed to a thickness [evaporation level (j)].
"-' Next, this AI layer 112 is heated to about 46℃ and 2+9yfl! (8
51 water 188): nitrate (601 aqueous solution): glacial acetic acid engineering pure water - 16:1:2!1 (volume ratio) Photoetching treatment was performed using a Kara family etching solution (etchant). , gate electrode 116° source extraction electrode 11
4. Forming the drain extraction electrode 115 [step (k
)].

Thereafter, it was heat-treated at about 650° C.2 in a nitrogen atmosphere and used as a thin film transistor.

Here, the semiconductor layer "102.n layer 104-1.104-2
The tit-IVD method was used to melt-evaporate silicon using an electron beam, and both processes were performed at a substrate temperature of about 450°C.

Further, when forming the n-layer, phosphorus was heated and evaporated from the crucible at the same time as silicon was deposited.

In this embodiment, an example is given in which a Mo layer is used as a mask for lift-off, but it is also possible to use a Cr layer, a silicon oxide layer, a silicon nitride layer, or a composite layer of these in place of the Mo layer. Since it is possible to turn off the n-layer without leaving much of it, a thin film silicon transistor with a similar structure can finally be produced.

FIG. 2 shows the steps of a manufacturing method according to another embodiment of the present invention. A semiconductor layer 202 made of thin film silicon is deposited on a substrate 201 . Thereafter, a silicon nitride layer 203 is deposited to a thickness of 0.4 degrees by the QD method, and a Mo layer 604 is deposited to a thickness of 0.5 degrees by the drawn electron beam evaporation method [step (a)]. Thereafter, the Mo layer 204 was etched by photoetching using the etchant I described in Example 1, followed by hydrofluoric acid (50-aqueous solution); pure water-1 to 10
(The silicon nitride layer 206 is etched using an etching solution (etchant I) having a volume ratio of
The silicon nitride Y layer 203 is etched for approximately 2C1Jt. In order not to corrode the etchant 204, the cross-sectional shapes of the etched layer 204 and the silicon nitride layer 206 have a constricted shape ideal for the lift-off method as shown in FIG.

Next, layers 205-1 and 205-2 were deposited to a 0.1-tone layer by the QD method, and then immersed in etchant fiber to dissolve the silicon nitride layer 203, followed by ultrasonic cleaning and water washing to form the Mo layer 204 and One layer 205-2 deposited thereon is peeled off. After that, the process described in Example 1 is
) A thin film transistor was created using the same process as in the previous step.

In the example @2, the semiconductor layer, n layer, and silicon nitride layer were created by the QD method. As described in this embodiment, if thin films of 21s class 1 or higher, which can be selectively etched, are laminated and used as a lift-off mask, an ideal cross-sectional shape can be formed. Therefore, the method according to the present invention is also possible in the case of a thin film deposition method that is excellent in step couplets, such as the QD method.

Furthermore, since the method according to the present invention does not use a commonly used photoresist as an i-layer for lift-off, the n-layer can be deposited at a substrate temperature of 250° C. or higher.

[Brief explanation of drawings]

Figure 1 is a schematic process diagram for explaining the production process in the first embodiment NK, and Figure 2- is a schematic process diagram for explaining the production process in the second embodiment example. FIG. 3 is an explanatory diagram for explaining a second embodiment example. 101, 201...Substrate 102, 202...
・・・Yabaghat+゛104-1.104-2.205-1.205-2-・
...N-tier applicant Canon Co., Ltd.

Claims (4)

[Claims] (1) A thin film semiconductor layer with silicon as the base provided on the substrate, a source region layer and a drain region layer formed of n-layers with silicon as the base formed on the mosquito semiconductor layer, and the source a gate insulating layer provided on the portion between the gate region l- and the drain region layer, a gate insulating layer provided on the gate insulating layer, and the source pj;
Source tIL and cutting 61 provided at tM 1m-h
In a method for manufacturing a thin film transistor having a structure including a drain 'wL pole provided on a drain glume region layer, n
A method for manufacturing a thin film transistor in which the n/d in the undamaged portion is removed by a lift-off method when patterning 1111 to form the source chain acid and front d-drain regions. (2) A method for manufacturing a thin film transistor according to claim 1, which has a laminated beak structure of a plurality of pigeons with different lift-off mass used for lift-off. (3) The lift-off mask is composed of m1 layer made of silicon oxide or silicon nitride, Cr (chromium) or iiMo
The method for manufacturing a thin film transistor according to claim 2, wherein the second layer is made of (molybdenum) and has a two-layer structure. (4) The specific resistance of the n-layer is 10 Ωl or less II! A method for manufacturing a membrane transistor.