JPS58169612A - Bus control system - Google Patents

Abstract

PURPOSE:To realize a high-speed transfer of data between terminals and to suppress deterioration of the processing capacity of a CPU, by using two data buses for the transfer of data which requires the decision of the CPU and for the transfer which requires no decision of the CPU. CONSTITUTION:A primary control part 401 corresponding to a CPU performs the control for initialization, combinations of terminal pairs, starting, etc. of terminals 402-408 via an I/O bus 410 which functions as the 1st data bus. The started terminal transmits data output request signals 412-414 or data input request signals 415-417 to a bus control part 407. The part 407 delivers signals 418-420 which permit the output of data onto the 2nd data bus 411 as well as latching signals 421-423 which give the timing to fetch the data on the bus 411 on the basis of the variable priority pair orders of the terminals 402-406.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a terminal including a CPU and a memory (CPU includes anything from a microprocessor to a large one,
It relates to a path control system that connects terminals (including small to large terminals) using l-chips.

[Technical background of the invention and its problems]

Conventional high-speed data transfer methods are known to be based on DMAK and 7° rectifier channel.
One data transfer can be performed without CPU relay.

Figure 1 shows a system using DMA102.
Data transfer by 101 is performed by K as follows.

The CPU 101 outputs the upper address from the CPU upper address bus 109 and outputs the lower address from the data bus 114', controls the output of the CPU address latch signal 115 and the CPU pass enable signal 116, and outputs the lower address from the CPU upper address bus 109. CPU address latch 103
K is latched and output to the CPU lower address bus 110 at a predetermined timing.

From this k, system address bus 113KdROM
105, an address for accessing the working RAM 106 or buffer memory 107 is output,
The CPU 101 takes in the data of the nine chips selected by the address decoder 123 via the data bus 114, or transfers the data via the data bus 114 and the bidirectional driver 108.

On the other hand, when performing data transfer using the DMA 102, K is
DMA from a terminal not shown! ! When the compensation request signal 119 is output, the DMA 102 outputs the CPU 101 K path exclusive request signal 121, and when this is accepted (path request confirmation signal 122), the DMA 102 exclusively uses the bus and sends DM to the terminal.
A confirmation signal 120 is issued.

Then, for example, the DMA 102 outputs the lower address from the DMA lower address bus 112 and outputs the lower address from the data bus 11.
4 outputs an upper address, controls the output of a DMA address latch signal 117 and a DMA bus enable signal 118, causes the DMA address latch 104 to latch the upper address, and outputs it to the DMA upper address bus 111 at a predetermined timing. Then, the upper address is transferred to the system address bus 1 via the CPU upper address bus 109.
13, the lower address is CPU 1st address bus 1
Through 10 and 113K.

This allows the DMA 102a buffer memory 107 to be accessed. DMA102 is DMA confirmation signal 1
20, it is possible to respond to a data transfer request from an external terminal (not shown) via the bidirectional driver 108.

However, when data transfer is being performed by the MA 102, the DMA 102 monopolizes the data bus 114 and the CPU 10I cannot operate.
Using DMA reduces the processing power of the CPU.

FIG. 2 shows a system using selector channel 203-1 and selector channel 203-2.

In this system, ■ 10 paths 206 from CPU 201
extends, and a memory path M extends from the main memory 202. The I10 bus 206 and the memory path 207 are connected to the selector channel 203-1 and the selector channel 203.
-2 respectively. Furthermore, selector channel 203
-I terminal 204 via K company selector path 208-1
is connected to the selector channel 203-2K, and the terminal 205 is connected to the selector channel 203-2K via the selector bus 208-2.

In such a system, for example, even if the terminal 204 and the main memory 202 perform high-speed data transfer using the memory path 207, selector channel 203-1, and selector path 208-1, the CPO 201 Since the connected I10 path 206 is not exclusive,
CPU 201 and terminal 205 are connected to I10 path 206
, selector channel 203-2 and selector node 20
Data can be transferred using B-2.

However, even in such a system, the CPU 201
Data transfer that is not relayed by
A relay between the CPU 201 and the terminal 204 was required, making it impossible to perform high-speed data transfer.

[Purpose of the invention]

An object of the present invention is to provide a bus control method that eliminates the above-mentioned drawbacks, enables high-speed data transfer between terminals, and does not reduce the processing ability of the tc4cPU during this high-speed data transfer. be.

[Summary of the invention]

Therefore, in the present invention, a first data bus is used for transferring data that requires judgment by the CPU, and a second data bus is used for transferring data that does not require judgment by the CPU. Then, it was decided that high-speed data transfer between terminals would be performed using the second data bus, and that the exclusive position of the second data bus would be from the terminal pair with the lowest priority.

However, this priority level is not fixed and can be varied under the control of the CPU.

[Embodiments of the invention]

In the 3rd N, 401 is a main control push part corresponding to CPUK. This main control unit 401 controls the first data base I1.
0 bus 410, the terminals 402 to 408 are controlled such as initial settings, combinations of terminal pairs, and activation. The activated terminal sends a data output request signal 412
-414 or data input request signals 415-417 are sent to the path control unit 407, which is a terminal. The bus control unit 407 transmits data to the terminals on the image information bus 411, which is a second data bus, based on the variable priority pair order of the terminals 402 to 406 set by the main control unit 401 via the I10 path 410. Output permission signals 418 to 42 that permit output
0 and outputs latch signals 421 to 423 that provide timing for capturing data on the image information bus 411. Various methods can be considered for how to make the image information bus 411 exclusive to the terminal based on the priority order, but here,
When requests are received from multiple terminals at the same time, the terminals assigned by the CPU are sequentially monopolized in a time-sharing manner starting from the terminal with the highest priority: p request.

FIG. 4 is a diagram showing the configuration of the path control unit 407.
An interface port 701 connected to the path 410 and the main control unit 40 via this interface port 701
The request signal 41 is based on the command for determining the combination of terminal pairs received from 1, that is, the pair determination command.
A multiplexer (hereinafter referred to as "a") 702 that multiplexes P! numbers 418 to 417 and a permission signal and a latch signal generated internally based on the pair determination command to a corresponding terminal 11i] (P! numbers 418 to 420 and a latch signal). 421 to 423, and a D-type flip 70 (hereinafter referred to as D-F/F) 704 for latching the request signal.

705 and this D-F''/F 704, 705 outputs are read respectively 1)-F/F 706, 707, J AND or NAND gates 708 to 714, and 6-phase internal clocks C1 to 714 from the system clock e. It consists of a counter 715 and a decoder 716 for creating O6, and a set-reset flip-flop (hereinafter referred to as R-8F/F) 717 for creating the timing pulse of the permission signal, and these are connected as shown in t-S. It is.

The pair determination command is given at the start of a series of system operations, and remains unchanged until the end of the operation. In other words, when applied to a facsimile machine described later, the operation mode may be, for example, transmitting operation, receiving operation,
In the case of transmitting/receiving operations, copying operations, etc., appropriate combinations are given at the time of activation of the selected l operation mode.

Gate 708, D-F/F 704, 706, and gate 71O9712 are ILJi road block A corresponding to terminal pair 1, and similarly gate 709, D-F/F 7
05, 707, Game) 711, 713 are circuit blocks B corresponding to other terminal pairs. For convenience of illustration 2
Although the circuit block is one circuit block, it is not limited to this. The relationship between these circuit blocks is D-F/
F7 [Game that uses IR output 4 as gate control input] 7
14, the circuit block A is given priority over the circuit block B by K. The above pair determination command determines the operation of Mx 702 and DMX 703, but since the priority relationship between circuit blocks A and B is determined, it also determines the priority order between multiple pairs. This is K.

Here, an outline of its operation will be explained. Now, the pair has been decided.
It is assumed that the incoming and outgoing lines of Mx 702 and DMx 703 are connected as shown in the figure based on the command. This means that a pair A' of terminals 402 and 403 and a pair B' of terminals 404 and 405 are determined, and a pair A' of terminals 402 and 403 is determined.
' has been determined to have priority over pair B'.

Now, as shown in FIG. 5, the data output request signal 412 of the terminal 402 of the pair A' and the data input request signal 415 of the terminal 403, and the data output IT signal 413 of the terminal 404 of the pair B' and the data input request signal 415 of the terminal 405 are transmitted. Assume that the data input request signals 416 are output almost simultaneously and there is a conflict. Then, when the punt of the signal 412 and the signal 415 is established, it is latched that the input/output requests of the pair A' are completed in the D-F/F 704, and when the AND of the signal 413 and the signal 416 is also established, the D-F/F 704 is latched. -F/F'705 to pair B'
It is latched that all input/output requests have been completed. And these are D-F/F respectively in ~internal claw claw
706, 707 K is read. This is accompanied by a signal (
Processing letter II) 5011-J"H@(BUSYρtona Luka, Shin J) 502HA@Waiting at L'"ott (WAIT
,), a game controlled by signal 501) 710
and 712 for internal clock e1~, respectively.

Output permission signal and internal clock e that are “L” for a period of
, ~e, a dangerous latch signal is obtained for a period of 1L'' and is output as an output permission signal 418 and a latch signal 421 to the terminals 402 and 403, respectively. The transfer of the long data is completed. Therefore, the output of the data output request signal 412 and data input request signal 415 that requested the transfer becomes @L''. Note that DF/F 704 is cleared at the time of output of latch signal 421, and DF/F 704 is cleared when latch signal 421 is output.
Cleared by 706, 707 a internal error e,
Of these, the D-F/F 707 will be set again at the next internal clock a.

Pair B', which has been forced to wait, uses its internal clock oe,→.

Then, the transfer is performed according to the output permission signal 419 and latch signal 422 generated by the circuit block BK which operates in the same way as the pair A'.

Next, assuming that Fig. 3 is applied to a facsimile machine,
I will explain in detail.

The terminal includes a reading section 402, an encoding section 403, a decoding section 404, a recording section 405, a memory 406, a transmission control section 409, and a transmission control section 409 connected to the transmission control section 408.
Let be the network control unit.

ζ Here, the facsimile apparatus will be described as being set to the transmitting/receiving operation mode. In this case, the pair determination command is a command that determines the pair of the reading section 402 and the encoding section 403 and the pair of the decoding section 404 and the recording section 405, and also has a content that gives priority to the former over the other. Suppose there is.

Now, in operation, when the reading section 402 reads the original and is ready to output image information, the reading section a outputs the data output request signal 412. On the other hand, when the encoding unit 403 is ready to input image information, it sends a data input request signal 41
Outputs 5.

In contrast, the network control unit 409
The input image information L1 is sent to the decoding unit 404 via the transmission control unit 408 and the I10 path 410 under the control of the main control unit 4010. Then, when the image information is decoded into image information by the decoding unit 404, the decoding unit outputs a data output request signal 413. On the other hand, when the recording unit 405 is ready to input image information, it outputs a data input request signal 416.

Now, if the data output request signals 412 and 413 conflict, the bus control unit 407 controls the image information bus 411 based on the pair determination command as described above. Here, since the processing of the reading section 402 is given priority over the processing of the decoding section 404, the bus control section 407 controls the processing of the reading section 402→encoding section 403 as shown in FIG. The processing state signal 501 is set to the processing end state BUS Yl, and an output permission signal 418 is output to the # weir section 402. Furthermore, the bus control unit 407 outputs the encoded 5403 Heratch signal 421 while outputting the output permission signal 418 .

From this K, line drawing information is output from the reading 15402,
The encoding unit 403 takes in image information from the image information bus 411 while the latch signal 421 is being output. The bus control unit 407
Thereafter, the output of the latch signal 421 is stopped, and further the output of the output permission signal 418 is stopped. As a result, the reading section 40
2->The processing status signal 501 for coding part theft is the processing end status E.
It becomes ND1.

Therefore, the data output request signal 412 and the data input request signal 415 are no longer output.

During this time, the processing status signal 502 of the decoding unit 404→recording unit 405 was in the waiting state WAIT, but since the processing status signal 501 was in the processing end state END, the processing status signal 502 was in the waiting state WAIT. It becomes Y. Therefore, the bus control unit 407 sends an output permission signal 4 to the decoding unit 404.
19, and further outputs a latch signal 4 to the 1st functional section 405.
Outputs 22. From this K, image information is output from the decoding unit 404, and the recording unit 405 takes in the image information from the image information bus 411 while the latch signal 422 is being output. The bus control unit 407 then stops outputting the latch signal 422 and further stops outputting the output permission signal 419. As a result, the processing status signal 5 of the decoding unit 404→recording unit 405
02 becomes the processing end letter III END26. Therefore, the data output request signal 413 and the data input request signal 416 are no longer output.

As described above, the image information is transferred between each terminal in a time-sharing manner, and after the image information taken in by the encoding unit 403 in the above explanation is encoded, the image information is transferred to the I1
The data is sent to the transmission control unit 408 via the 0 bus 410, and further sent to the line from the network control unit 409. In addition, the recording section 4
The image information sent to 08 is output as a hard copy.

This is an explanation of the operation in the transmission/reception mode, but in addition, for example, in the case of the copy mode, that is, the mode in which the reading section and the recording section are directly connected, the operation is explained based on the bare determination command in that case as shown in Fig. 6. as.

Mx 702 and DM, 7o'3 change their internal connection states. In this case, circuit block B is shown by a broken line because it is substantially in an inactive state.

Furthermore, the data output request signal 414 or defer input request signal 417 is output from the memory 406 in FIG. If so, the path control unit 407 performs the operation described above, so that the main control unit 401 can transfer data to the memory 406 or to another terminal, or from another terminal to the memory 406. It can be done without doing.

〔Effect of the invention〕

As described above, according to the present invention, high-speed data transfer is possible using the second data bus without the intervention of the CPU (that is, the CPU interprets instructions).

Further, even if the second data bus reaches 100% operating rate, the CPU can perform processing using the first data bus, and the processing capacity of the CPU does not decrease.

Furthermore, by the second data bus, without CPU intervention,
It is possible to transfer data between terminals, including memory, and the system has great utility value.

[Brief explanation of the drawings] Fig. 1 is a block diagram of a system using the conventional method of Company 27, Fig. 3 is a block diagram of a system using the method of the present invention, and Fig. 4 shows the configuration of the path control section. Block diagram shown, No. 5
The figure is the ninth timing chart explaining the present invention.
This figure is a block diagram showing an example of the same configuration as that in FIG. 4 but different operating states. 401... Main control unit (CPU) 402-406... Terminal 407... Path control unit 410... First data bus 411... Second data bus

Claims (1)

[Scope of Claims] (1) A first data bus used for transferring data that requires judgment by the CPU, and a second data bus used for transferring data that does not require judgment by the CPU. death,
These data buses connect the CPU and terminals including memory to Ii! path control characterized in that the second data bus is exclusively used by the terminals according to the priority assigned by the CPUK, and data that does not require judgment by the CPU is transferred between the terminals. method. (2) The path control system according to claim (1), characterized in that the data bus of Iris 2 is time-divisionally used exclusively by IIK from terminals with higher priority. (8) Priority and terminal pair combination is CPUC
) Claims characterized in that they are variable according to instructions.
@ Bus control method described in (2).