JPS58169305A - Converting method of binary code - Google Patents

Abstract

PURPOSE:To reduce DC and a low-band component, by displaying two pieces whose polarity of the digital sum is opposite and whose absolute values are equal, as one group, in a converting method of a variable length code, which converts the number of bits, and limits the minimum value and the maximum value of the number of ''0'' between ''1'' and ''1'' to some value. CONSTITUTION:''10'' of a code is made ''2'', ''01'' is made ''1'' and ''00'' is made ''0'', by which a code is expressed by 4-scale. A bit of ''0'' is made -1, a bit of ''1'' is made +1, and the sum total is taken at each code, by which the sum (abbreviated as DSV) is derived. Positive and negative values of DSC are made maps B, A, respectively. In case of encoding, an accumulated value of DSV is seen, and when it is positive and beginning of the following code is in a low level, a code of the map A is used, and when said beginning is in a high level, a code of the map B is used. By executing such encoding, DC and a low-band component can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention (a) relates to a method for converting a binary Kari-go which is applied to a platform for transmitting a Ko-value Hakama-go using a m-ki recording and reproducing device as a medium.

In this invention, in the code after 11 conversion, the minimum value of O between l and / is limited to d, and the maximum value of O between l and l is limited to d.
is limited to k, and the data bits are made to correspond to the n bits of the code, and the transformation: W :l i :::I
l:* t,, 2:::7 2; 2:: is ((1,
kpm, nor) and lI! be revealed.

This invention takes! At the long length*t, we aim to reduce the direct current and low frequency components, and also increase the maximum inversion amount ■'f' 11
The difference between 1111 and the minimum inversion interval Tewin is made small.

An embodiment of this invention will be described below.

In this example, the tree is set to <t, s; t, ko; 7). Also, this sign is inverted after 7 in NRZI. (as-/)(kxJ), so if the data bit cell is T, then e
(Tmax--T).

(Twin=T).

2nd wi and 3111 are encoding tables of an embodiment of the present invention, which are shown in FIG. 2, and J[ is expressed in NRZ.

1 bit of data is converted into a quantity of 2 bits).

(rsa+7), so the code corresponding to the data in l-bit to γ-bit weight is kobitsu),
1 bit), 1 bit, 1 bit), 10 bits, /, 711 bits, and 2 times.

A sign is determined corresponding to the number of l's that exist between - in the data and the number of l's that are 7 consecutive bits. In addition, the code can be praised on the approach by the 1C committee, where the # code is CIO>;, (0/) is 7, and <00> is O. -Like I■.

Since Natsu- occurs after l in the code shown in No. 11JII, if its low level is set to O and its high level is set to I/, the encode table can be represented by the expression of NR4 as shown in No. 711.

((1-/) #) The condition is that the case O or l must be continuous in the NRZe field, so the previous code (MRZ
)eThe last pitch) is Of) and the table shown in 111711 people is used, and when this is l.

1117 [The table shown in IB is used. This 11
As is clear from FIG. 13, the digital sum (hereinafter abbreviated as DIIV) can be obtained by setting the bit of O to -l and the bit of l to 10l, and taking the sum in the # position.

The sign of this D8V of 0 corresponds to the data 7-, and the amount of IF for which DIiV is not 0 has a negative DflV of 1i (117 mm) when the sign is changed from a low level. Let Map A be the one, and DIIV be the king's! Whelk B
Then, when No. 11 met from a high level, there was a meeting (No. JliB).
Let map A be the one where D8ma is positive.

Map B is the one where D8V is negative. Then, when encoding, ' looks at the accumulated value of nsv, and if this is positive and the next sign's brass association is at a low level e, the sign of map A is used, and this brass association 9 is at a high level. Notokai is map 1tf
) When the cumulative value of c and nsv is negative, the selection of maps A and B is done in the opposite way to the improvement. By performing such encoding, it is possible to reduce the direct current and low frequency components.
A pull can be decoded at will, and even if an error occurs, the pull satisfies the one-permanence condition of a variable-length code, that is, the propagation is **. Also.

As a code corresponding to 17-bit data, an IF code (three examples are shown) may be used, with IIV having positive/negative polarity and l/l as shown in FIG.

111j cabinet and jllllB are NRZI”C’mugigen*
ht decoding table. When performing variable-length interpolation decoding, Harukai takes the l# bit of the code into a register, searches for the code that corresponds to the l# bit, and if found, decodes it from the table.

If you can't find it, please refer to the previous application.
It is necessary to sequentially perform steps corresponding to the bits. On the other hand, in one embodiment of the present invention,
Except for the data of (/ / / / / / /”), as is clear from the jII, at most the previous l bits,
It is uniquely decoded by examining the l bit of II.

The encoder converts 1 bit into 1 bit, and the 2 bits underlined in FIG. 3 are converted into 1 bit. And the jl
lA indicates a table when the l bit to be decoded is O, and jllB indicates a table when it is 7. In addition, the 2 V corresponding to data with 7 consecutive l's can be decoded by detecting the pattern of bit '1 of the IO bit of (///10) according to the approach 6.Furthermore, A code that does not match 1M1 to any of the above-mentioned Detu F rules will be detected as an error.

An example applied to the variable length code of (7) will be described.

Figure 4 and Figure 711 &! , which shows the configuration of an encoder in an embodiment of the present invention, and zgu is a time chart representing the operation of this encoder.

In the fourth [, data is supplied to the terminal indicated by 1, and 2
Cuckoo CKII is supplied to the terminal indicated by. This clock CxH material is obtained by dividing the clock CI shown in the jliA by 1, and the ringing island number th#s, which is equal to the bit frequency of the input data, indicates an active counter.

This counter 3 is cleared by the output of Yuta Tsuta C1 [counting H and NOR game with input inversion] 4. ′
jI Yunta 3's top level output is AMD game) 5
A signal $ is formed by supplying the signal to one input of the NOR gate (4). )10R data is supplied as the other input of)4.

Therefore data or signal 8. By becoming O,
Output of NOR gate 48. is 0! , this clears Power Run #3. In other words, ★ counter 3 generates outputs corresponding to l consecutive songs of data, and is cleared with a maximum of 77 pieces.

The data is separated into leads.

In addition, when the data and signal S are supplied with A) ID gauge 7, a signal 8.
is carved. In addition, the signal 88 is inverted and supplied by the A)fD gate 1 to form the signal 8-, which is the delimiter of the signal 88.

The output of advanced callan #3 is supplied to (J-1) decoder S. In this case, the least significant bit and the signal 8s are passed through an itastarucip OR gate 9. therefore,
When a continuous machine of 1 reads data of 4 days, (/1
J bits of 0) are added to the decoder $, and if there are 7 consecutive machines, J bits of <iit> are added to the decoder $. The data indicating the continuous unit of 1 appearing at the output of the decoder 8 is supplied to the assembly circuit 10 which uses an AγD gate and an OR gauge.

Encoding is performed according to the table shown in Figure 2.
A code emerges from the combinational circuit 10. In this case, any bits not specified in Fig. 2 are considered to be O. For example, the code (0/00> that corresponds to data (10) is @
(&1 @ &@ g kB ”””al,) is <o
oiooooooooooo>14! Pitsu). Along with this, as is clear from the second cabinet, al.
Since the J bit of &'@ is 0, these 3 bits are not output from the tg path 10.

Also, JK79 Tubu 7 Tabu 11 was kicked out II.

Confucian J#84 specifying maps A and B is formed.

The output of the NARD game (NARD game) 12 of input inversion is supplied as the input of 711 and Y of the JK79 block 11.
When (To r) is <oo>, the output signal s4 is shattered by the data # CKIi, and when this is (l/), the signal 84 is not inverted (MAND day) 12, Signal C and an inverted version of the output of AND gate 13 are supplied.

Signals 8s and B4 are supplied to AND gate 13.

The selection of this map alternately selects pines 1A and B for each / code, and <oioootoiotoi.

Only in the case of pattern O), the map is taken from map B, which is the same as map 1 of the wings. this is.

The absolute values of Dllv are equal and the sign of (nsv volume 0) is 7
This is because the interval of is an odd number -, and the number of enemies of l of the sign of (nsv!qo) is an even number. However, the above-mentioned l dabit pattern is lk3! There is no iL. Generally, D
If the absolute values of llv are equal, if the number of l is odd, then 9
The next code is from a map different from the current one, and if this is an even number, it may be the same map.

(nsv!qO), the opposite selection should be made.

Note that a ROM may be used in place of the total m amount of 11 m116. In this case, the 3 bits supplied to the decoder $ and the output of the summer ND gate 12 are used as the ROM address.

As shown in FIG.
* II * l@ * BY
* m, e M 1@ -
This is used as one input for each of the following 14. Also, 14. Is, l@, 17 indicates a serial-in/parallel-out shift register that can be connected in parallel. This shift register 1
As inputs for each of ``4 to 11'', each output of ``Itacruship OR game'' 1., IIm mmmmmm*expletive, 4 is supplied. However, when input to al, it is always given ON. Also, shift) registers 14 to 1
T's parallel listening C-~014 is Ita exclusive OR
Game) 1. , Ns...-1114. In this case, the pattern # outputs Cs and Cma corresponding to 龜, 龜, are shifted as they are in registers 14 and 15.
It is used as a preset input. This shift) register 14~
17eIPw As input, the start pulse CK from terminal 18 is supplied, and the signal Is from terminal 1s (the t11th and t'1li
1) will be supplied.

The output CI4 of the 7th register #1T is passed through the inverter 20 to the tartar input of the D-type 7rip 7w tube 21,
A serial code is obtained at the output terminal 22. In the above-described embodiment of the present invention, the operation when the data shown in the twtc is supplied to the input terminal 1 will be described. At this time, the 1st HD, 1ielIIx *
Signal IIs * 8m e I shown in jl II'
A signal 84 is generated which switches between maps A and II shown in FIG. The numbers fslWiD&- indicate the output of *counter 3, and this and signal 8. Also, the decoder 8 is supplied with a numerical code shown at jllH.

We met. The jllI shows the signal 8s, which indicates the delimitation of the data hood, and therefore the tHH
&- put 0? The calculated number represents the number of consecutive l's in the l word of the data. For example, the first WH &: 0 that can be invited is
It means that the l word of the data is (/////10), and *Shaso-ji 10 also corresponds to this data! Taken from Tupum (am e as...1.4
) as ll bits of ((as) 0/(1
14) 10/Ca,) 101010) occurs.

O is supplied to the serial inputs of the shift registers 14 to 17. This Schiff) Regis #14~
When the outputs C1 to C□ are all O to the IF pattern, signal 1. At the start-up 9, the output of the parent circuit 10 is turned on, and as shown in the frame (■) in J, the outputs C3 to C14 of the shift registers #14 to #17 are the outputs of the parent circuit 10. It changes to the corresponding one. Next, when a new code is entered at the start of signal 8, registers #14 to #17 of signal #17 perform a shift operation by Yubuya Tsuta CI, and 0 is input. By that,
As shown below the diagonal concentration line in 1st *J.

The outputs of the registers #14 to #17 become 0 in sequence.

In addition, the output csi of the shift) register 11 is taken out,
The output terminal 22 has a number shown in the figure! The serial output code shown in □1
RZI) is obtained.

Also, in the first order, the code corresponding to the power Φ of the decoder 8 is -
The same operation as described above is performed.

Furthermore, Ill corresponding to the output (2) of the decoder 8 is coded. In this case, the code corresponding to ■ is valid (l bit), and the output of the shift register corresponding to this ≦ bit is all O, so it is p-coded as is and l
The bit is 0! because there is.

l of the sign corresponding to Φ still remaining in the shift register
bits are saved. Such output sign is .

For example, an image is recorded on a magnetic tape by a rotary head. FIG. 9 shows the configuration of a decoder in an embodiment of the present invention, and FIG. 10 shows a time charge representing the operation of this decoder.

In the fs9 diagram, a code sequence reproduced from, for example, a magnetic tape is supplied to an input terminal indicated by 23.

A collector CI is supplied to a terminal indicated by 24. This code system is D$79 Tsubu 7w Tsubu 2S and Itacruship O
It is converted into an NRZ wave* (l is a high level, 0#i is a wave/amount corresponding to a low level) by passing through the R game) 2@ and the D 79 tube 7w tube 21. Further, the tartuter CI is divided into 100 stations by the D-type 7 lip 7w tube 2I via the mum ND gate 21, and the two tartuta CXX are separated by one phase.

and CKII are formed.

Figure 1A shows Tarotsuta CI, Figure 1B and Figure 11
Cu, Tartuta CKH, and Cl- are shown.

These tarets CIE and Cl1l correspond to the cobit No. IF. Moreover, the first O'1liD is 5
An example of a code sequence corresponding to rIIK is shown, and by passing through the 7 rip 7 w knobs 25 and 27, the 7th
As shown in the 0 cabinet insult, l p) accompanied.

Data D converted to NRZ is generated. This data DI is supplied as the serial input of shift registers 30 and 32, and as the least significant bit of the parallel input.

The reproduced data is rearranged and arrayed to determine where to divide the code sequence into groups of 2 bits each. In this example, when the framing is normal, <
7 Reminder is performed by utilizing the fact that there are only four consecutive one-bit patterns of 01> at most. Shift register X#30&! , works with cxiil and schiff)
Regis #32 is.

One consecutive bit of data #D1 is taken into the registers 30 and 32. The least significant bit of the parallel shift of registers 30 and 32 is signal 8. and 8! When the 02 bits (S·, 8ma) extracted as (-1#) and supplied to the decoder 34 are (O7).

Output of decoder 348. (This is an OR game)
35 is used as the tariff input for force #3G. Karan #36 counts Tarotsuta CIH, and makes it 7.
For example, if l≦the total is equal to or greater than 1, a mid-range output that becomes O is generated, and this carry is supplied. If 7 or more (Ol) patterns are consecutive, it is a missed 7 frame, but taking into account errors during transmission, 14 (O7) patterns are detected and considered as a missed frame.

The data shown in the first OHM is Turk C'KII.

and CKH, alternately shift registers #sO and 3.
Since 2.9 is included, the signal life and 8. teeth.

#/7IIF and G. (8=, Recommendation) in the place of CO/), as shown in l1110Wivt.

Signal 8. becomes /, so in the same figure /,, 2°J・
...As shown by ≦, the counter 36 indicates the evening lesson
When the signal 8 becomes O by counting KH, *(8selly) becomes (Oo), the signal #3G is turned on. The time chart shown in Chapter io*F shows that the correct location is Leheni's house.

If Miss 7 Ray^ is raw-1, due to Karan #s@'s key output power, evening stomach ivy C1L will not be able to pass through Antogame) 2$, and this is 7-mer.

The phase of the attack and CKH is inverted.

0 meeting where misframes are corrected. The output signal 8- (FIG. 1O) of the decoder 34 and the reference output of the counter 36 are used for the decoding operation. The signal 8. and the output of the counter S@ are supplied to an anti-game 31.

The output of this &day) $7 is sent through the 7 drop tube 7w tube 3@ and the VOR gauge SS, and the signal 1. ．． 311 is applied 0 This signal lI@ is, as shown in the first OIIIJ, I! In decimal display (///10) - in decimal display (01010
If a bit pattern of 10100> is detected, it becomes l. In other words, the code corresponding to (llllllll) of the data <ioi.

0101010100>or<otooioiotOlo
loo) is not decoded by the decoding table shown in jll, as described above.

A platform with such a code is (010101010101
It is converted into an IFI with a pattern of 010/>.

Such a conversion is performed using cascaded shift registers 30
31 and 31 as inputs, and l' as inputs to all the cascade-connected shift registers 32 and 33 as inputs. And signal 81
When becomes 7, these preset inputs are loaded into the shift register 5oNss. In this way, by converting the s number, the <01> Kobitsu)
is decoded into l, so 7 bits) are decoded into l data.゛Also, shift) register 31 and parallel output 8 of 3s,
1-81. is supplied to the assembly circuit 4.

This coarse gold tI circuit 40 has an AND gauge and the like connected according to the decoding table shown in FIG.
The dexf output is taken out to the output terminal 41. It is also possible to use a ROM instead of coarse gold for the circuit 40. Further, a code field that does not correspond to the decoding table shown in jll may be regarded as an error, and a signal indicating the presence or absence of an error may be generated from the parent circuit 40.

N of the j-bit Karigo in the decoding table of Figure 3
What is converted to Rz corresponds to the signal "11~all. Signal 8°, 11 e 8 for the 1st oHx, Lt MI III M s Ill WRllo in the same figure, respectively.
111e'14e its is shown. The data shown in the first OWIP is obtained at the output terminal of the circuit 40#) which is combined with the J pins 81 to SL (not shown).

By adding this to D 7 ri 7 4 tsu 1 +, a decoded output as shown in 10WiQ can be obtained.

Understand from the explanation of one embodiment above! So that it can be done.

According to this invention, it is possible to perform modulation with suppressed DC components. Therefore, it is suitable for application to a platform that cannot transmit a DC component, such as an i1 rotary head type day recorder. Also, the maximum return test ■T111 pin! and the minimum reversal interval - T multiplication in is 2! and T, the difference between them is small, so the spectrum of the envy output is concentrated. Therefore, it becomes easy to set up a recording ifrazer, etc.

In addition, there is an advantage that the amount of beater shift is reduced.

Furthermore, since not only the DC component but also the low frequency component is suppressed, Tarstalk interference is reduced.

Fig. 7 shows the shape-1 Fig. 2, JIi, and 4! used for explaining the present invention. This invention is the M1 of the Cabinet! ! 1Ff
``An example of a table is shown in Table 1.''

No. jll is an abbreviation-9 that shows an example of the decoding table.
Figures 411 and 7 are boot starter diagrams of an encoder that can be used in an embodiment of the present invention, No. Jll is a time charge used to explain the operation of this encoder, and Figure 7 is a boot starter diagram of a decoder in an embodiment of the present invention. The first oria is a time chart used for the operation** of this decoder.

3.36... Counter, II, 34...
・Decoder, 10.40... circuit, 1
4. Is, 16.17, 30.31.32.33...
...Sifushi register.

Substitute agent: Masamasa Sugiura

Claims (1)

[Claims] Converting grave bit data into an n-bit code,
In a variable-length code conversion method in which the minimum and maximum values of the number of leapfrogs between / and l are converted to d and k, respectively, the code whose digital sum is O is Correspond to the 7 items. For codes whose digital sum is not O''C, the polarity of the digital sum is opposite when the code goes from a low level or a high level, and seven pairs of codes whose absolute values are equal correspond to one piece of data. A binary code conversion method that emphasizes