JPS58169245A - Microprogram controller - Google Patents

Abstract

PURPOSE:To checks the advance of a sequence all the time by an address comparison and to detect a fault immediately, by comparing the output of an address storage device with that of a comparison address storage device which generates expected addresses successively according to the progress of a program. CONSTITUTION:A microprocessor MPU outputs a storage address of a control memory CS to a comparing circuit CMP. Prior to the start of operation, addresses of the program of the microprocessor MPU are written in a buffer memory BF in specific order. The addresses of this memory BF are read by a clock RCK and compared with a program address MPA by the circuit CMP when the comparison address is generated. The comparison output of this circuit CMP is applied to a logical circuit together with a comparison enabling signal and when the comparison result shows coincidence, an FF is set. Thus, the advance of the sequence is checked all the time to detect a fault immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION +11 Technical Field of the Invention The present invention relates to a microprogram 1114m* that can constantly check the progress of diatance.

Background of 121a technique and conventional technology One micro 10 gram tI &out''C in electronic computer
When controlling M, it is often the case that no checks are performed on each address. Even if they did, they would not actively compare the addresses, and would only display the resultant force 1 with a lamp, etc., to see if they had passed the address. It should flow through the two addresses.

To tell you that this address must not pass, the voice says that Microgateram has been initially loaded, so checking the address and controlling the computer will be accurate. However, since the microprogram itself does not check the result of address comparison,
Even if an abnormality occurs in the flow of control, even if normality cannot be detected as a result of control, such as when there is a double failure, the state is equivalent to no abnormality.

■Purpose of the Invention The purpose of the invention is to provide a microprogram system@package that can quickly detect abnormalities by constantly checking the progress of the sequence by comparing addresses. +41 Structure of the Invention The structure of the present invention is as follows. Issue commands one after another from the desired address! Iku Nippu 4G Control 4i2IIKm.

It has a comparison address storage device that can generate a predicted address corresponding to the difference between Micro 7 and Gram, and an address comparison circuit that compares the output of the original comparison address storage device and the instruction successive address, Each time the output of the address comparison circuit is generated, the output of the comparison address storage device is updated, and the comparison is performed for the 8th address.

(Examples of 51 inventions FIG. 1 is a block diagram showing an example of the present invention.

Figure 2 shows the operating waveform diagram of Figure 1. A microprocessor U reads out the address of the stored program in the IN control memory CB and supplies it to the comparison circuit OMF. B.P.
is a first-in, first-out II (IF function F011 buffer memory I). Before starting operation, the microprocessor prepares the memory by loading the addresses of 14 and 2 memory in a specified order into the IIF. Reads the buffer memory 1ν. After generating a soft address OP, the address is compared with the microphone program address MP in a comparator circuit OM.The conveyor enable signal 01
11 in Maru and if the comparison result is good, compare 7 lip 7 stomach tube F? Set. The output of the 7-rip 7a-p νν is logically calculated with the instruction fetch signal we8mR to generate the subsequent clock Ra of '/'. When the comparison operation is completed for all pre-charged addresses, the buffer BF becomes empty and the IM
Emit P signal. Microprocessor MPU in seven stages
Or horizontal blue result Che! and next address buffer BP
Write K. FIG. 2 shows an operation time chart of the single circuit diagram, in which the microbe 0/?
As the program address MP changes one after another, buffer B
When the comparison address CP from P is entered and can be compared, the 9th order comparison address is extracted and stored again.

is shown.

Note that the buffer Bv may not be a first-in, first-out type yxv0 but may be a 'C-first-first-out al LIFO.

11. Effects of the Invention In this way, according to the present invention, it is possible to dynamically check the dynamic control of the microprogram 7, including the ordering of addresses at multiple locations. Since all checks are performed, reliability of control can be further improved. Since the buffer memory/comparison circuit section can be a small piece of hardware, it does not need to be large-scale.%11
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[Brief explanation of the drawing]

Figure 91 is a configuration diagram showing an embodiment of the invention, Figure 2 is a ts
(Operation time chart in Figure 1)! show. MPU...Microprocessor C8...PIIJI! 1 memory BF-...Buffer memory OMP...Ratio 112 circuit MP...Micro block 2 address OP...
Comparison address? ? ...7 lips 70 Tub W OII A R---Instruction emission signal NOX-5 output Yoshitsuk Patent applicant: Fujitsu Ltd. Representative: Sosuke Tsuguri, patent attorney

Claims (1)

[Claims] In a microphone four-program system device that continuously issues commands from sufficient addresses, there is a comparison address memory that can occasionally issue scheduled addresses corresponding to the age of the microprogram, and an output of the comparison address memory 11. and an address comparison circuit for comparing the instruction successive address, and each time an output of the address comparison circuit is generated, the output of the comparison address storage f device is read, and the S+ next child address is compared. Microphone 41a/
') A mat.