JPS58168231A - Etching method in preparation of semiconductor device - Google Patents

Etching method in preparation of semiconductor device

Info

Publication number
JPS58168231A
JPS58168231A JP5010982A JP5010982A JPS58168231A JP S58168231 A JPS58168231 A JP S58168231A JP 5010982 A JP5010982 A JP 5010982A JP 5010982 A JP5010982 A JP 5010982A JP S58168231 A JPS58168231 A JP S58168231A
Authority
JP
Japan
Prior art keywords
etching
wafer
area
mask
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5010982A
Other languages
Japanese (ja)
Inventor
Toshio Oshima
利雄 大島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5010982A priority Critical patent/JPS58168231A/en
Publication of JPS58168231A publication Critical patent/JPS58168231A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To amplify an etching end signal, and easily and accurately monitor the end of etching by enlarging the etching area by removing the resist at the wafer area which does not become a product. CONSTITUTION:A hard mask A is produced by vacuum depositing a chrome film 2 on a glass substrate 1 in such a way that the periphery of mask pattern 3 which is smaller than wafer 4 is perfectly covered by said chrome, and it is then stacked, through positioning, on the wafer 4 on which negative photo resist 5 is coated and then exposing is carried out. Since the corresponding part 5A on the wafer 4 at the external side of pattern 3 is not exposed, such part is removed by developing process. In case of executing the etching SiO2 using CHF2 as the etching gas, since the etching area is expanded, amount of CO generated increases and light emitting intensity of plasma changes largely at the end of etching.

Description

【発明の詳細な説明】 (1)MIiOal1分野 本実−は亭導体装置OS造におけるエツチング方法に関
し、更に詳しく紘工νテンダ1)@点検出をよ)害鳥な
らしめるようにし大半導体装置O製造におけるエラチン
1方法に調する。
Detailed Description of the Invention (1) MIiOal1 Field This article relates to the etching method in the conductor device OS fabrication, and in more detail, Hiroko ν tender 1) @ point detection to make it a pest and large semiconductor device O fabrication. According to the Eratin 1 method.

(2)  技11011’景 半導体デバイスの高性能化、高集積化に伴ない、製造工
isKおける基本プwx*ス技術として黴顔Δターン形
成a術が重IIa1れ、そOvL暫開発が進められてい
る。黴lll1Δターン形成技術は写真刺販技111に
よりてホトレジスト/4p−ンをクエへ*1iiK膠威
す為レジストΔターノ形成工程と、このレジストAI−
ざt!スクとして素子に必要な半導体%p、p体中金属
属會化学県晶によりエツチングして黴−、、杉−ン會−
威する工Vチンダニ楊に大別畜れる。   。
(2) TECHNOLOGY 11011' Background With the increasing performance and high integration of semiconductor devices, mold face delta turn formation a technology has become important as a basic process technology in manufacturing technology, and interim development of OvL is progressing. It is being The mold 1Δ turn formation technology is based on the photoresist/4p-n by photoembroidery technique 111.
Zat! Semiconductor %P, which is necessary for the element as a mask, is etched with a metal metallurgy chemical prefecture crystal in the P body.
It was defeated by the intimidating Tech V and Chidani Yang. .

黴IsAメーン會**、よく工、チンダする技術として
、髄未紘水S*によゐ化学二yチンrが主流!亀してい
え・、17−かし・薬品の職扱″?不便さや愈Ikなど
ツj[−で、竺近では水溶撒を用い、ないで気薯xi、
會用い九ドツイエッチンダ技術が注目され実態に供され
ている。ドライニッチyダは真空中でOプラズマ−ex
Δツタ反応會用い九反応で、−工曽鷹の向上、工@O簡
嵩化中自動化、安倉無会!化牟J’011mがある。こ
Oような工fチンダニSに)いてエラチン10終点を正
確に知、ること紘重am、ことでhj1%41に上記ド
ライエ、チンダにおいてはエツチングO終点を検出すh
仁とが必畳不可決であみ。
At the main meeting of Mold IsA**, the most commonly used technology for engineering and processing is chemical dilutions based on marrow water S*! 17-How to deal with pharmaceuticals? Inconvenience, anxiety, etc., in the area, water-soluble sprays are used, and do not use water-soluble sprays.
The nine-dot etching technology used in the industry has been attracting attention and is being put to practical use. Dry niche y da is O plasma-ex in vacuum
With nine reactions using the ΔIvy Reaction Society, - Improvement of Kusotaka, Automation during the simplification and bulking of Engineering @O, and Mukai Yasukura! There is Kamu J'011m. By using such a technique (such as this), it is possible to accurately know the end point of etching O in the above-mentioned Dreyer and Chinda.
Jin and Ami are indispensable.

<3)  Ii未技術と間越点 しか為に、例えばソースドレインとのコンタクトホール
を形成する九めにエツチングを行うような場合には、そ
のエツチング面積が狭い、このようにエツチング面積が
狭い場合には、エツチングO終点をエッチングブスリ発
光強度O変化で知る方法においては、その変化が少ない
丸め、そOエツチングの終点検出が#AJli″cTo
り九、このため、寸法精度O良いレジストΔターノが得
られにくい欠点があり九。
<3) Due to the lack of Ii technology, for example, when etching is performed in the ninth step to form a contact hole with a source/drain, the etching area is small. In the method of determining the end point of etching O by the change in the etching luminescence intensity O, the end point of etching can be detected by rounding, which has little change.
For this reason, there is a drawback that it is difficult to obtain a resist Δ turn with good dimensional accuracy.

(4)発INO目的および構成 本実−はかかる状況に鎌み、エツチング終点を明確に知
る丸めになされえ4ので工、チン!前にウェハの一部分
のレジス)を除去することによってエツチング面積を拡
大するようにしえこと1*黴とする。
(4) The purpose and structure of the INO should be rounded to take into account this situation and clearly know the end point of the etching. The etching area is expanded by removing the resist from a portion of the wafer beforehand.

この15に本発明を榔威し九通論的根拠は、次のとTh
j)である、すなわち、例えはエツチングガスにCI!
y、用いて810.を工rチン!する場合、C1[F、
はプラズマ中で解離シ:CCF、中Mを生威し、ウェハ
上01110.と反応してC0,81F4*どを作ると
考えられている。このうちCOは波長fi04nmでl
I&党する。ζO尭党強度はジャストエツチング(Jl
)0酋と価で拡、前0fi5が強く終点検出Kjlll
用で龜為、Jl前0604詣O発光強度はCOO量が多
い攬と、し丸がりて8凰01面O広いはど強(、結果と
ルて脅光強度の111g後の変化量を火車くな)、終点
O検出が容易になる。このようKIiO,画、すなわち
レジスタにおおわれていないエツチングINが広いはと
終点検出が中ルヤすい、これはq「、でIIO,lエツ
チングする場合のみならず、ドライエツチングで本例と
同様の原理で終点検出する場合にすべで成立することは
明らかである。
The basis for applying the present invention to this 15th theory is as follows.
j), that is, for example, etching gas is CI!
y, using 810. I'm working on it! , C1[F,
Dissociate in plasma: CCF, medium M and deposit 01110 on the wafer. It is thought that it reacts with C0,81F4* to produce C0,81F4*. Of these, CO has a wavelength fi of 04 nm.
I & party. ζO party strength is just etching (Jl
) Expanded with 0 and value, the previous 0fi5 was strong and the end point was detected Kjllll
Due to the long time, the luminous intensity of 0604 in front of Jl is high when the amount of COO is large, and the curved and rounded 8-01 side is wide. ), it becomes easier to detect the end point O. In this way, if the KIiO, image, that is, the etching IN not covered by the register, is wide, it is easy to detect the end point. It is clear that this holds true when the end point is detected by .

エラチン/l1llt広くするためには、例えば製品と
ならないクエへの一部分OレジストカエッチンダO前に
**されていれによく、このためには実施例でのべる如
1轡別のマスクを使用すれば嵐い・ 以下、本実−の一実施例會図面に基づいて説明する。
In order to widen the eratin/l1llt, for example, a part of the resist that will not be used as a product may be applied before the etching. For this purpose, a separate mask may be used as described in the examples. Hereinafter, one embodiment of the present invention will be explained based on the drawings.

(5)実施例 ガラス基板1上にタ■ム属!を蒸着して、バーyマスク
ムを製造する。ζO場舎、後記のウェー−4よ〉も七の
面積が小でiるマスクΔターy3oysm全体をクロム
で完全におおうように蒸着しておく、このようなハード
マスクムtクエハ4上に位置合わせして両者を重ねる。
(5) Example Tam on the glass substrate 1! is vapor-deposited to produce a bary mask. ζO area, wafer 4 to be described later) is also placed on such a hard mask wafer 4, which has a small area and is deposited so that the entire surface of the mask Δta is completely covered with chromium. Combine and overlap both.

崗、ウェハ4上にはネガ形のホトレジストSがm布され
ている。
A negative photoresist S is coated on the wafer 4.

次に露光を行なう0本例では置部露光を行なうが、露光
はζO方法に@らず、働O方法、例えば同様(Q−rス
フ管用いて投影露光する方t7&(グロジエクシ冒ン馬
光)、あるいは塘′klチッlずつレチクルの像を焼き
つける方法(ステップアンPvビート露光)も使用で龜
る。籐mm1K示す状態でm光した場合、iスクΔター
ンsO外儒蕩分でつエバ4上の1幽する部分5ムは秦外
纏によりて露光されず、Itりて光重合奮起ζ畜ず硬化
しない0次に露光しえウェハt@像tKつけて未露光部
分を除去する。
Next, exposure is carried out.In this example, positional exposure is performed, but exposure is not carried out using the ζO method, but using the working method, for example, the same method (projection exposure using a Q-r tube). , or the method of printing the image of the reticle in units of 1000 pixels (Step Pv Beat Exposure) is also slow to use.If you use m light in a state where the rattan mm1K is displayed, the i-screw Δturn sO extrapolation will be delayed. The upper part of the wafer t@image tK is not exposed because it is not exposed to light and is not cured by photopolymerization.

本例においては、マスタパターン30外儒部分でウェハ
4上の対応部分5ムは露光されていないの′″ee檎像
)諌蕩分Sムは除去される・かかる状態Oウェハをプラ
ズマエ、チンダしホトレジストの付いていない部分音除
去する。
In this example, the outer part of the master pattern 30 and the corresponding part 5 on the wafer 4 are not exposed. and removes partials that are not covered by photoresist.

本例にシける4リシリコンの工、チyダは以下の条件で
行り九、エツチングガスcar、100G、流量150
1177分、ステージ温度30℃、減圧度0、3 T@
rr s  ウェハ径4イン気高周波出力800W′e
番る・ 工、チンダモーターは以下の方法で行った。
In this example, the 4-resilicon process was performed under the following conditions: etching gas car, 100G, flow rate 150
1177 minutes, stage temperature 30℃, degree of vacuum 0, 3T@
rr s Wafer diameter 4 inches High frequency output 800W'e
The turning, machining, and chinda motor were performed using the following method.

石J[チェンバーO外11に光ファイバーの一端をと)
付け、その他端に分光器を坂)付け604mmの光を轍
〉出し、さらにその先にフォ)wルティグライヤを付け
てその強度変化を電気信号に置換する。
Stone J [Put one end of the optical fiber outside chamber O at 11]
A spectroscope is attached to the other end to emit a 604 mm beam, and a tiglare is attached at the end of the track to convert the intensity changes into electrical signals.

試験結果1114図に示す、謳4図に示されるように本
方法を用い九場合(1!l中、曲線aで示す)、明らか
に通常の方法の場合′(−中、−一一で示す)に比べて
ジャストエツチング前後の信号変化量が人動く、終点の
検出が容易である。
Test results 1114 As shown in Figure 4, when this method was used in nine cases (indicated by curve a in 1!l), in the case of the conventional method' (indicated by -11 in -11), ), the amount of signal change before and after just etching varies, making it easier to detect the end point.

尚、測定には波兼約604 nmの光を用いた。Note that for the measurement, light with a wavelength of approximately 604 nm was used.

木偶においては、このように従来の工、チンダにおける
よりもエツチング画積が拡大されているので工、チング
によ多発生するcookがふえ、発光強度が強くなる。
In the wooden figurine, the etching area is expanded compared to that in the conventional wood figurines, so the amount of cook that occurs frequently in the wood figurines increases, and the luminescence intensity becomes stronger.

従ってエツチング終了時におけるプラズマ元の発光強度
変化は相対的に大きくなる。
Therefore, the change in the emission intensity of the plasma source at the end of etching becomes relatively large.

(6)発明の効果 本発明は、以上説明しえように製品とならないウェハO
s分のレジストをWk*することによりて工、チングa
Sを拡大するように構成し九4のであるからエツチング
の終点信号が大要〈な)、エツチング終了f:容易にし
かも確実に−iニタすることがで暑る。従って、このよ
うなエツチング方法によjl黴細ノリーンを形成する効
果を得ることが可能となる。
(6) Effects of the invention As explained above, the present invention provides a
By applying s resist to Wk*,
Since it is configured to enlarge S, the end point signal of etching is essential, and the etching end f: can be easily and reliably monitored by -i. Therefore, it is possible to obtain the effect of forming a moldy nolin by such an etching method.

【図面の簡単な説明】[Brief explanation of drawings]

菖1図は本発明の一実施例において使用されるマスクを
示す平面−1 籐2図は本発明の一実施例において使用されるクエへを
示す千画図、 菖Saaは本発明の一実施例において使用されるマスク
とウェハを重ねた状態上水すaM図、j1411はエラ
チン/4=りO結果上水すグラフである。 1・・・ガラス基板、2−・・クロム属、3・・・マス
クツタ−7,4・−・ウェハ、5−・・ネf#Mホトレ
ジスト、ム・・・ハードマスク。 轡許出願人 富士通株式会社 轡許出願代雇人 弁通士青木 網 弁塩士画、−和之 弁1±−j’i ii挙男 弁履士 山 口 陥 之 第4図
Diagram 1 of the irises is Plane-1 showing a mask used in an embodiment of the present invention. Diagram 2 of the rattan is a 1000-page diagram showing a mask used in an embodiment of the present invention. Iris Saa is a plane-1 diagram showing a mask used in an embodiment of the present invention. J1411 is a graph showing the overlapping state of the mask and wafer used in the above. DESCRIPTION OF SYMBOLS 1...Glass substrate, 2-...Chromium metal, 3...Mask vine 7, 4...Wafer, 5-...Nef#M photoresist, M...Hard mask. License applicant: Fujitsu Ltd. License application agent, hired attorney, Aoki Amiben, illustrated by Shioji Amiben, - Kazunoben 1±-j'i ii, Ikedo Yamaguchi, illustration 4

Claims (1)

【特許請求の範囲】[Claims] 1、 クエハ上Oレジス)の一部分鵞エッチンl前に除
去することによってエラチン/m11mを拡大し九こと
t特徴とすみ、牛導体装置O幽造におけるエツチング方
法。
1. The etching method in the conductor device O-resist is characterized by enlarging the elastin/m11m by removing a part of the surface (on the surface of the surface) before etching.
JP5010982A 1982-03-30 1982-03-30 Etching method in preparation of semiconductor device Pending JPS58168231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5010982A JPS58168231A (en) 1982-03-30 1982-03-30 Etching method in preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5010982A JPS58168231A (en) 1982-03-30 1982-03-30 Etching method in preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58168231A true JPS58168231A (en) 1983-10-04

Family

ID=12849917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5010982A Pending JPS58168231A (en) 1982-03-30 1982-03-30 Etching method in preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58168231A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5897975A (en) * 1994-12-02 1999-04-27 Hyundai Electronics Industries Co., Ltd. Phase shift mask for formation of contact holes having micro dimension

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5897975A (en) * 1994-12-02 1999-04-27 Hyundai Electronics Industries Co., Ltd. Phase shift mask for formation of contact holes having micro dimension

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