JPS58165495A - Burst signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a simple and inexpensive burst signal generating circuit, without using expensive components such as ROM, by providing a low pass filter receiving an output of a matrix circuit. CONSTITUTION:The titled circuit consists of a 1:3 input subcarrier SC, an input burst flag BF, an NAND gate 5, shift registers 6-9, registors R1, R2, a low pass filter 10, and double subcarrier clock CL. The input subcarrier SC being 1:3 duty as shown in S1 is picked up in timing of existence of burst signals at the NAND gate. The signal is arranged for the clock period at the buffer 6 through shift registers 7-9, only the output of the registes 7 and 9 is inverted for the polarity at inverters 11, 12 and synthesized through a resistance matrix satisfying R1<R2, as shown in Fig. S8. The signal is as shown in broken lines through the low pass filter 10, allowing to obtain a signal equivalent to the color burst signal used for conventional color television signals.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color burst signal generation circuit in a color television signal processing device.

Conventionally, in general, this Yuzu burst signal generation circuit stores digital data obtained by sampling a burst signal in RUNl in advance, as shown in FIG. 1, and receives a subcarrier signal SC and a burst flag signal HF as input.
By inputting the address created by the i address control circuit 2 to the ROM 1, a digital burst signal is obtained, and this signal is sent to the tl)/A converter 3.
A burst signal is created by passing through a low-pass filter 4t which is converted into an analog signal. In this case, the component cost includes a part called ROM1 which is more expensive than other parts, which has the disadvantage of increasing the price. without using
An object of the present invention is to provide a low-cost and simple burst signal generation circuit.

The principle of the present invention will be explained with reference to FIG. 2. From the input subcarrier SC and the burst flag BP, only the timing portion where the color burst signal should exist is extracted from the signal AQ. In order to obtain the signal, the double subcarrier signal 0 is used as a link, and the signal AO is passed through the buffer Bu and the registers REGO to REGN, which are matched to the cycle of the link. Next, there is a group of inverters 1xJ that alternately inverts the polarity of each register output signal, and Rr<1m for averaging each register signal.
・Pass through the resistance matrix R1 to KN that satisfies <RN. Next, the combined output signal is passed through a low-pass filter LPF that limits the band.

Next, the present invention will be described in detail with reference to the drawings of an embodiment of the present invention. Referring to FIG. 3, the embodiment of the present invention is an embodiment in which the number of registers is limited to three, including an input subcarrier SC of 1:3 and an input bar, □.

the shift flag BP, the NAI'lJD gate 5, the shift transistors 6 to 9, the resistors R, , R, and the low-pass filter 1.
It includes a clock CL of 0 and 2 subcarriers.

'1 The input subcarrier SC is: Punishment, l: 1 due to the duty of 3, and is as shown in Fig. Take out the ζro] and it will look like M4 diagram Ss. Next, buffer 6
The outputs of registers 7 and 9 are reversed in polarity using inverters 1 and 12, and then synthesized through a resistor matrix that satisfies the condition Rx<R, 2. , FIG. 488
When the signal is passed through a four-pass filter 0 as shown by the broken line, a signal equivalent to the color burst signal used in ordinary color television signals is obtained. In Fig. 4, 82 indicates H F (P, point) which has passed through the inverter.
8 indicates the output of register 6 (point P4), 85 indicates the signal that passes through inverter 1 and attenuates the resistor tag. 11
point), S6 indicates the output of register 8 (point Pa), S,
indicates a signal that passes through the inverter 2t and is attenuated by the resistor.
Because it can be expressed, it is effective in reducing the price.

□・：、：．

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a conventional burst generation circuit, Fig. 2 is a diagram showing the principle of the present invention, Fig. 3 is a diagram showing an embodiment of the present invention, and Fig. 4 is a diagram showing the following circuit as shown in Fig. 1M3. FIG. Fig. 2 Fig. 3 Fig. m-”-top once once once-sto ℃-]l-1F-:・□
11 Shi1 Figure 4

Claims (1)

[Claims] A register group of (2n-1) stages that receives pulsed subcarriers driven at a wave number that is at least twice the subcarrier frequency, and n discrete outputs among the 2n output signals from the register group. an inverter that receives the output, a matrix circuit that combines n outputs from the inverter and the remaining n outputs from the register group, and a low-pass filter that receives the output of the matrix circuit. burst signal generation circuit.