JPS6310235A - Instruction decoder - Google Patents

Abstract

PURPOSE:To obtain a multi-instruction set decoder of a simple constitution by connecting an input signal line led to a decoding element to an instruction signal line via a switching element. CONSTITUTION:The decoding element input lines Na and Nb of a decoding element D are connected to instruction signal lines L1-L3 via a switching transistor and shift registers Ca and Cb consisting of FFTa1-Ta3, Fa1-Fa3, Tb1-Tb3 and Fb1-Fb3 which control said switching transistor. Both registers Ca and Cb are controlled by shift synchronizing signals Ka and Kb respectively. Then plural instruction sets of desired signal trains are selectively supplied to the element D via the signal lines L1-L3 and decoded. As a result, the decoding element, a multiplexer, etc. are not required for each instruction set. Thus it is possible to obtain a multi-instruction set of a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction decoder, and more particularly to a multi-instruction set decoder.

[Conventional technology]

Conventionally, for example, two types of instructions, )X,
In order to generate desired signal strings for Y, the instruction signal line to be decoded is decoded via the decoding element input signal line for each instruction set as shown in FIG. element Dx,
A multi-instruction decoder was realized by inputting the signal into DY and selecting the decoded signals ax and 8y using a multiplexer M.

[Problem that the invention seeks to solve]

The conventional configuration described above has the disadvantage that a decoding element is required for each instruction set, and a multiplexer for selecting a target signal train is required.

[Means for solving problems]

The instant decoder of the present invention connects an input signal line to a decoding element and an instruction signal line via a switching element, and controls this switching element to decode a selected instruction signal line. By doing so, it has the ability to generate desired signal sequences for multiple instruction sets.

The instruction decoder of the present invention is an instruction decoder that generates desired signal sequences for each of a plurality of instruction sets, in which a switching element and its control circuit are added to one decoding element. It is characterized by selecting a wired signal line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an n-channel FvlOS showing one embodiment of the present invention.
It is part of a multi-instruction, source, and decoder using technology. A transistor T, which is a switching element for selecting an input/straight signal line to be decoded; 1. . . 5Tl) &'s source and drain are the i/straxy sound signal line L1 corresponding to the subscript, respectively.
y Lt * L, , decode element input signal line N
Connect to a, Nb. Broken line C,.

Inside cb is a transistor control circuit, which in this embodiment is a flip-flop & 1 m Fafi e F.
& a... and Fbt t Fbt e Fbs I
. . . are connected in series, and the clock Ka
, Kb, and a shift register that shifts held data in synchronization with Kb. Decode element input signal @Na
Among the flip-flops connected to K, the output of the flip-flop F'at is 11", the other outputs are 0#, and the flip-flop connected to the decoding element input signal line Nb is If the output of the flip 70-tube Fbt is "1" and the other outputs are "Om", only the transistor T□*TM becomes conductive, and the instructor 1 signal line is decoded as Element input signal line N a v
Nb are logically connected to each other, and input stock signal signals mL1 . Can decode Lt. Also, if only the output of FRI, P-FLO, and F□*"bj is set to ``1'', and the output of the other FRI, P-FLOPS is set to ``mO'', the instruction signal line L
1 and L can be decoded by the decoding element.

Note that the switching elements may be connected to all the decoding element input signal lines and all the instructor 1 signal lines, respectively, or may be used only for some of them.

〔Effect of the invention〕

As explained above, according to the present invention, by adding a switching element and its control circuit to a single decoding element, the instruction signal line to be decoded can be made variable. It becomes possible to configure.

Further, since the switching elements are arranged regularly, layout design is facilitated.

In the embodiment, nMO8 technology is used as an example and an nMO8 transistor is used as a switching element, but the present invention is also applicable to other technologies.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a multi-instruction set decoder showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional multi-instruction set decoder. L, ,L, ,L, ,L, ,L, ,L・-
-----Instruction signal line, Ns, Nb, Nx
, NY...Decode element input signal line, T, ,
,T, ,T, ,Tb1. Tb, tTbs...
...Transistor, pat eFtll sF&a e
Ftll 511i'b! 5Pb3 ""...Fri, P-Flo, P, C,, Cb...Shift register, K,, Kb, -,,,, Shift synchronization signal, De
D X t D Y...Decode element, M.
...Multiplexer, SX. ay...Decode signal line. Agent: Susumu Uchihara, Puff≧
Sa/' MeZ Go

Claims (1)

[Claims] An instruction decoder that generates desired signal sequences for each of a plurality of instruction sets, characterized in that a switching element and its control circuit are added to one decoding element, and an instruction signal line to be decoded is selected. .