JPH07141146A - Burrel shifter - Google Patents

Abstract

PURPOSE:To shorten the delay time of a burrel shifter and to reduce its circuit area. CONSTITUTION:This burrel shifter is provided with a decoder 42 for inputting and decoding a shifted quantity signal SAO and outputting a 2-bit multiplexer control signal, a multiplexer 48 for outputting data output signals obtained by shifting data signals DO to D63 based upon the multiplexer control signal, a decoder 43 for inputting and decoding shifted quantity signals SA1 to SA2 and outputting a 4-bit multiplexer control signal, a multiplexer 49 for shifting data output signals based upon the multiplexer control signal, a decoder 44 for inputting and decoding shifted quantity signals SA3 to SA5 and outputting an 8-bit multiplexer control signal, and a multiplexer 50 for outputting data output signals O0 to O63 obtained by shifting data output signals based upon the multiplexer control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrel shifter,
General purpose microprocessors, microcontrollers,
Alternatively, it relates to that used for shifting digital signals in a digital signal processor or integrated circuit.

[0002]

2. Description of the Related Art A conventional 64-bit width barrel shifter will be described with reference to the drawings.

FIG. 4 shows an example of the structure of a conventional barrel shifter.

64-bit wide data signals D0 to D63 are input to the input buffer 16, amplified and output to the multiplexer 14.

Further, 6-bit shift amount signals SA0 to SA5 are input to the 6:64 decoder 12, decoded, and multiplexer control signals C0 to C63 are output to the multiplexer 14 via the multiplexer control line 13.

The multiplexer 14 has a structure in which switching elements composed of transistors are arranged in a 64 × 64 matrix. Then, the multiplexer 14 is driven by the multiplexer control signals C0 to C63, and the open / closed state of each switching element is set. This determines the shift amount and shifts the data signals D0 to D63. The shifted data signals O0-O63 are
After being amplified by the output buffer 15, it is output.

FIG. 5 shows the structure of another conventional barrel shifter. In this barrel shifter, the shift amount signals SA0 to S
A5 is decoded by six 1: 2 decoders 22 for each bit, and a multiplexer control signal is output from the multiplexer control line 23 to the multiplexers 24a to 24f.

The data signals D0 to D63 amplified by the input buffer 26 are input to the first stage multiplexer 24a. The multiplexers 24a to 24f are 64 × 2
The switching elements arranged in a matrix are divided into six stages and arranged. A 2-bit multiplexer control signal is applied to each of the six divided multiplexers 24a to 24f to determine the shift amount. The first-stage multiplexer 24a shifts by 0 or 1 bit in accordance with the multiplexer control signal. Two
The multiplexer 24b in the third stage shifts by 0 or 2 bits, and the multiplexer 24c in the third stage shifts by 0 or 4 bits. The multiplexer 24d in the fourth stage shifts 0 or 8 bits, the multiplexer 24e in the fifth stage shifts 0 or 16 bits, and the multiplexer 24f in the sixth stage shifts 0 or 32 bits. And 6
The finally shifted data signals O0 to O63 are output from the multiplexer 24f in the stage. The data signals O0 to O63 are amplified by the output buffer 25 and output to the outside.

In recent years, a barrel shifter as shown in FIG. 6 has also been proposed. Shift amount signal SA0-SA2
And the shift amount signals SA3 to SA5 are supplied to the decoder 3 respectively.
3 and the decoder 32, respectively, to be decoded. After being decoded, 8-bit multiplexer control signals are output from the multiplexer control lines 35 and 34.

The data signals D0 to D63 amplified by the input buffer 39 are input to the 64 × 8: 1 multiplexer 37 divided into two stages. A multiplexer control signal is input to each of the multiplexers 37 and 36 and shifted. 0 in the first-stage multiplexer 37
To 7 bits are set, and the multiplexer 36 sets any of 0 bits to 56 bits in byte steps. The shifted data signals O0 to O63 are finally output from the multiplexer 36, amplified by the output buffer 38, and then output to the outside.

[0011]

However, the conventional barrel shifter described above has the following problems.

The barrel shifter shown in FIG. 4 is based on the full decoding method, and although it is fast in terms of speed, it requires 64 bits for the multiplexer control line 13, and 64
There is a problem that the area of the x64: 1 multiplexer 14 is large. On the contrary, the barrel shifter shown in FIG. 5 is based on a bit decoding method in which the shift amount signals SA0 to SA5 are divided and decoded one bit at a time. You can However, in speed
It was slower than the barrel shifter shown in.

The barrel shifter shown in FIG. 6 employs a partial decoding system in which the shift amount signals SA0 to SA5 are decoded in two stages, and the full decoding system is speeded up and the bit decoding system is highly integrated. It is configured to combine the advantages of.

However, even the barrel shifter shown in FIG. 6 could not sufficiently improve the speed. In the barrel shifter, the shift operation in the first-stage multiplexer 37 has a large influence on the entire operation time. However, it takes time for the decoder 33 that generates the multiplexer control signal to be given to the first-stage multiplexer 37 to decode the 3-bit shift amount signals SA0 to SA2. In addition, this barrel shifter could not be sufficiently reduced in area.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a barrel shifter capable of reducing the delay time and the circuit area.

[0016]

A barrel shifter of the present invention is a barrel shifter which receives a data signal and a shift amount signal, shifts the data signal by a shift amount based on the shift amount signal, and outputs the shifted data signal. A first decoder that receives a first shift amount signal included in a signal, decodes the first shift amount signal, and outputs a first multiplexer control signal; and the first multiplexer control signal and the data signal. A first multiplexer that shifts the data signal based on the multiplexer control signal and outputs a first data output signal; and a second shift amount signal included in the shift amount signal that is input and decoded, and Second decoder for outputting the multiplexer control signal of the second multiplexer, the second multiplexer control signal and the first data A second multiplexer that receives a force signal and shifts the first data output signal based on the second multiplexer control signal to output a second data output signal; and a third multiplexer included in the shift amount signal. A third decoder for receiving and decoding a shift amount signal of the second multiplexer and outputting a third multiplexer control signal;
A third multiplexer that is provided with the multiplexer control signal and the second data output signal, shifts the second data output signal based on the third multiplexer control signal, and outputs the third data output signal. Equipped with
The first shift amount signal, the second shift amount signal, and the third shift amount signal are set such that the number of bits increases in order.

[0017]

Since the number of bits of the first shift amount signal input to and decoded by the first decoder is the smallest among the first, second and third decoders, the decoding time in this first decoder is the smallest. Short, first decoder to first
The time required until the multiplexer control signal of (1) is output is short, and the shift operation in the first multiplexer can be started quickly. In the second decoder in the second stage, the second shift amount signal having the second smallest number of bits is input and decoded, and the second multiplexer control signal is output and given to the second multiplexer. In the second multiplexer, the time required to give the first data output signal from the first multiplexer and the time required to give the second multiplexer control signal are substantially equal to each other, resulting in wasted time. do not do. Next, in the third decoder of the third stage, it takes time to decode the third shift amount signal having the largest number of bits, but the second multiplexer outputs the second data output signal and the third data is output. The time required for the third multiplexer to be supplied to the third multiplexer and the time required for the third decoder to supply the third multiplexer control signal to the third multiplexer are substantially the same, and the overall operation time can be shortened. You can

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The barrel shifter of this embodiment is characterized in that the multiplexer is divided into a plurality of stages and the number of bits to be shifted by each multiplexer is sequentially increased from the first stage. In the first-stage multiplexer, the 2: 1 multiplexer shifts so as to operate at high speed. Next, the second-stage multiplexer shifts with a 4: 1 multiplexer, which is slower than the first-stage multiplexer. This gives 2
The long decode time and drive time in the first stage multiplexer can overlap the short decode time and multiplex time in the first stage multiplexer, so no wasted time is generated. In this way, by increasing the shift amount toward the subsequent stage and increasing the decoding time in the decoder, the long decoding time and drive time in the latter stage are overlapped with the short decoding time and multiplex time in the preceding stage. Go.

Further, by setting the first-stage multiplexer to the shift of 2: 1, it is possible to form not the pass transistor used as the switching element but the logic gate. If the multiplexer is composed of pass transistors, the potential drops when passing through the pass transistors, so it is necessary to provide an input buffer on the input side for amplification. However, by configuring the multiplexer with logic gates, the input buffer becomes unnecessary,
Higher speed is possible.

FIG. 1 shows a specific construction of the barrel shifter having a 64-bit width according to this embodiment. This barrel shifter performs shift operation in three stages. 64 in the first stage
A × 2: 1 multiplexer / input buffer 48 is provided. As described above, by providing the 2: 1 multiplexer 48 in the first stage, the multiplexer 48 can be configured by the logic gate as shown in FIG. 2, for example, and it is not necessary to provide the input buffer in the input stage. .

The least significant 1-bit shift amount signal SA0 is applied to the decoder 42 and a 2-bit multiplexer control signal is applied to the multiplexer 48 from the multiplexer control line 45. The multiplexer control signal controls the driving of the multiplexer 48 and sets the shift amount to 0 or 1 bit. The shift in the multiplexer 48 is performed by the multiplexers 48 provided in three stages.
Among the 50, the shift amount is the smallest.

When the multiplexer 48 is constituted by NAND gates 60, 62 and 63 for each bit as shown in FIG. 2, a 1-bit complementary signal (/ shift signal and shift signal) and a data signal (data Bits N and N +
1) and 1 are input to the NAND gates 62 and 63, respectively, and the outputs thereof are input to the NAND gate 60 to obtain the shifted output N.

The second stage is a 64 × 4: 1 multiplexer 4
9 is provided. The shift amount in the multiplexer 49 is the 2-bit shift amount signals SA1 and SA2.
Is set to any of 0 to 6 bits in a 2-bit step based on the output from the decoder 43 that is input. The output from the first-stage multiplexer 48 is given via the data line 53, and the shifted output is supplied to the data line 54.
Output to the 64 × 8: 1 multiplexer 50 via.

The shift amount of the multiplexer 50 is set to any of 0 to 56 bits based on the result of decoding of the 3-bit shift amount signals SA3 to SA5 by the input decoder 44. The shift amount of the multiplexer 50 provided at the final stage is the largest and is performed in byte units. The data signals O0 to O63 shifted by the multiplexer 50 are supplied to the output buffer 51, amplified, and then output to the outside.

In the present embodiment, the shift operation in the first-stage 2: 1 multiplexer 48 is the fastest, and the decoder 42
Also has the shortest decoding time. Therefore, the data signals D0 to D63 that are input to the multiplexer 48 without passing through the input buffer can be shifted quickly without waiting.

The output shifted at high speed by the first-stage multiplexer 48 is input to the second-stage multiplexer 49. Here, before the output from the first-stage multiplexer 48 is input to the second-stage multiplexer 49, the decoding operation of the decoder 43 is completed. This decoder 4
3 receives the shift amount signals SA1 and SA2 having the second smallest number of bits, and thus has the second shortest decoding time. Therefore, the timing at which the shift operation in the multiplexer 49 is started and the timing at which the decoding result is output from the decoder 43 are substantially coincident with each other, and no wasted time is generated.

In the conventional barrel shifter described above, which is shown in FIG. 6 in which the shift operation is divided into a plurality of stages, the biggest problem is that the decode time of the decoder in the first stage and the shift time of the multiplexer are long. It was On the other hand, in the present embodiment, the decoding time and shift time of the first stage are the shortest, so that the influence on the entire operation is small.

The shift operation in the second stage multiplexer 49 is slower than that in the first stage. However, the decoding time in the decoder 44 is long because the 3-bit shift amount signals SA3 to SA5 are decoded, and the timing at which the shift result of the multiplexer 49 is given to the final stage multiplexer 50 and the decoding result of the decoder 44 are determined by the multiplexer 5.
The timing given to 0 almost coincides with the time, and no time is wasted.

In the present embodiment, an example having a 64-bit width is shown, but the present invention is not limited to this bit width.

FIG. 3 shows the shift amount for each stage when the present invention is applied to a barrel shifter having a shift width other than the 64-bit width. In the barrel shifter having a width of 128 bits, the shift amount is set to 1, 2, and 4 bits in order from the first stage. With a 256-bit wide barrel shifter,
Set to 1, 2, 5 or 1, 3, 4 bits. Similarly, for a 512 bit wide barrel shifter, set to 1, 3, 5 bits, and for a 1024 bit wide barrel shifter,
Set to 1, 2, 3, 4 bits. In this way, the number of bits to be shifted may be set to increase sequentially from the first stage.

As described above, according to this embodiment, the operation time can be shortened as compared with the conventional case. Further, the multiplexer control lines 45 to 47 connecting the decoders 42 to 44 and the multiplexers 48 to 50 need only 14 bits (= 2 + 4 + 8) in total. Conventionally, the barrel shifter shown in FIG. 4 required 64 bits,
The area can obviously be reduced. Further, in the barrel shifter shown in FIG. 5, the multiplexer control line is 12 bits, and in the barrel shifter shown in FIG. 6, the multiplexer control line is 16 bits. The area can be reduced as compared with the conventional one.

[0032]

According to the barrel shifter of the present invention, the decoder and the barrel shifter are divided into a plurality of stages, and the number of bits of the shift amount signal input to the decoder is set to increase sequentially from the first stage. The decode time of the first-stage decoder and the drive time of the multiplexer are the shortest, and the data signal input to this multiplexer can be shifted quickly, and the decode time of the decoder and the drive time of the multiplexer can be changed from the second stage onward. Are sequentially set to be longer, the overall operation time can be shortened, and the total number of bits of the multiplexer control signal output from the decoder can be reduced to reduce the area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a 64-bit width barrel shifter according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a first stage multiplexer in the barrel shifter.

FIG. 3 is an explanatory diagram showing shift amount bits for each stage when the present invention is applied to a barrel shifter having a width of 64 to 1024 bits.

FIG. 4 is a circuit diagram showing a configuration of a 64-bit width barrel shifter according to a conventional full decoding method.

FIG. 5 is a circuit diagram showing a configuration of a 64-bit width barrel shifter according to a conventional bit decoding method.

FIG. 6 is a circuit diagram showing a configuration of a 64-bit width barrel shifter according to a conventional partial decoding method.

[Explanation of symbols]

 42, 43, 44 Decoder 45, 46, 47 Multiplexer control line 48, 49, 50 Multiplexer 51 Output buffer 52, 53, 54, 55 Data line SA0-SA5 Shift amount signal

Claims (2)

[Claims] 1. A data signal and a shift amount signal are input,
In a barrel shifter that shifts and outputs the data signal by a shift amount based on the shift amount signal, a first shift amount signal included in the shift amount signal is input and decoded, and a first multiplexer control signal is output. A first decoder for providing the first multiplexer control signal and the data signal, and the first multiplexer outputs the first data output signal by shifting the data signal based on the first multiplexer control signal. A multiplexer, a second decoder which receives and decodes a second shift amount signal included in the shift amount signal, and outputs a second multiplexer control signal, the second multiplexer control signal and the first multiplexer A first data output signal based on the second multiplexer control signal. A second multiplexer for shifting and outputting a second data output signal; and a third decoder for receiving and decoding a third shift amount signal included in the shift amount signal and outputting a third multiplexer control signal. And the third multiplexer control signal and the second data output signal are given, and the second data output signal is shifted based on the third multiplexer control signal to output the third data output signal. And a third multiplexer, wherein the first shift amount signal, the second shift amount signal, and the third shift amount signal are set such that the number of bits increases in order. . 2. The first shift amount signal is 1 bit, the first multiplexer is configured by using a logic gate, and the data signal is 0 or 1 bit based on the first multiplexer control signal. The barrel shifter according to claim 1, wherein the barrel shifter shifts.