JPS6165623A - Cmos selector circuit - Google Patents

Abstract

PURPOSE:To decrease the number of buffers for unnecessary operation and to reduce power consumption by providing a switching for turning off all non- selection gates and bringing a non-selection CMOS buffer input to '1' or '0' fixed value. CONSTITUTION:A switching means Q [Pch transistor (TR)] to fix the level of an input of buffers A0-A3 to '1' is added. A 1/2 selector circuit of the front most column of a 1/8 selector circuit is controlled by three control lines for a connection/release signal S'0', an LSB(a0) and MSB(a2) of a selection control signal. That is, when S=0, the 1/8 selector circuit is released, the transfer gates of the front most stage are all turned off, and I0(0)-I7(0) data are not received. In this case, inputs A0-A3 are fixed to '1' by f1, f2. Thus, all inputs at points A0-A6 are fixed to '1' or '0', the power consumed by the A0-A6 is due to the leakage only and the power consumption is remarkably lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a CMOS selector circuit that is high speed and consumes little power.

(Prior art) In a 1/m selector circuit that selects (7) one out of m (m=zF'!M≧2) inputs, a 1/m selector circuit that selects one out of two inputs is used. It is common to use a plurality of 2 selector circuits. Figure 3 shows an example in which the selector is configured with a 1/2 selector circuit.The 1/8 selector circuit receives three control signals (Xo * X 1 + "2") and its inverted signal (ao * ax + &z). The data of one of the inputs I0 to I7 is transferred to Qj.That is, first, depending on the value of aO,
, In', I6) is (It.

I3 IIs , I7) is selected.

If the selected set is (Io, I2, I4, I6), then by al, either (IO, I4) or (I
2. I&) is selected. Subsequently, one of the two data is selected according to the value of A2, and finally only one data is selected.

Next, FIG. 4 shows a circuit diagram of the 1/2 selector circuit shown in FIG. 3. (A) and (B) show the case where a transfer gate and a buffer are used as the 1/2 selector circuit. An inverter is usually used as this buffer.

Note that a single transfer gate can serve as a 1/2 selector, but when multiple transfer gates are connected, the delay and distortion of the input signal are large, so a buffer is usually inserted to shape the waveform.

As this buffer, CMOS inverter, E/DMOS
An inverter can be considered, but from the perspective of low power consumption (A
), (B) CMOS inverter types are preferable.

FIG. 5 shows a conventional circuit diagram when the 1/8 selector circuit is configured with the 1/2 selector circuit shown in FIG. 4(B).
In the figure, R and -R2 are selection control signals (ao e A1) that determine which one of the eight inputs is selected.
+ A2), and D.

is the selection control signal input, CLKo is the clock signal that enters R0 to R2, and So is the connection state in which the 1/8 selector circuit selects any one of the 8 inputs.
Or, it is a signal indicating whether it is in a release state in which none of the eight inputs is selected. In Figure 5, D
It is assumed that after the values of A2 and aI + ao are input in series by CLK as o, both normal and inverted signals of each aO + al l A2 are output.
Of course, the selection control signals may be input in parallel.

(Problem to be solved by the invention) The problem that arises when a high-speed digital signal of several tens of MHz is input to this selector circuit does not become noticeable when dealing with low-speed digital signals because of the CMO3 configuration. This is an increase in power consumption. This is because in the conventional example shown in FIG. 5, buffers that normally do not need to operate operate, and dynamic power is consumed by a large number of buffers. In other words, AQ#A is used in the 1/8 selector circuit.
There are 7 buffers of 6. Now the control signal (ao.

If at, A2) is (o*'*'), IO is selected and output to Oo. At this time, buffer AO+
A4 + A& must operate according to the data of engineering ◇ (0), but AI, A2, A3
.

The buffer of A5 is also I2 (0) + l4 (o)
, I6 (0), and In (o).

An example of applying this selector circuit is a digital space switch LSI. Figure 5 shows the l/8 selector circuit.
This is an example of a digital space switch LSI with 8 incoming lines and 8 outgoing lines, where I0 to F are incoming lines, BU
are buffers SE0 to SE, are 1/8 selector circuit, Oo
~07 indicates the outgoing line. When this selector circuit is used in a digital space switch LSI, the number of incoming and outgoing lines increases, the number of buffers that operate in vain in the LSI also increases, and the incoming line 16 outgoing line increases. In the case of 18, 178 circuits, 3 input lines
In the case of 2 outputs & 132, the 812 circuits waste power. This wasted power is the incoming line 32 outgoing line 32
When a high-speed digital signal of about 30 MH is input to an LSI, the value reaches as much as 200 to 300 mW.
There was a problem that the low power consumption of 5 was impaired.

In order to eliminate these drawbacks, the present invention aims to reduce power consumption by reducing the number of buffers that perform unnecessary operations as much as possible while suppressing an increase in circuit scale in a selector circuit.

(Means for Solving the Problems) In order to achieve the above object, the present invention turns off all unselected gates and sets unselected CMOS buffer inputs to a fixed value of "L" or "O". A switching means (Q) is provided for this purpose.

(Function) Set unselected CMOS buffer input to “1’” or “0”
Since the power consumption within the CMO 3 is reduced by setting a fixed value of ``, a CMOS selector circuit with low power consumption as a whole can be obtained.

(Example) FIG. 1 shows an example of the present invention, and like FIG. 5, 1/1
8 selectors, R6 to l(2, Do
, So +CLK6 are the same as in FIG. Figure 5 shows that in Figure 1, the number of signals that control the transfer gate at the frontmost stage has been increased, and switching means (Q (Pch) transistor) has been added to fix the inputs of the buffers A0 to A3 to lp. This is a big difference. The logic of the control circuit in FIG. 1 is shown in FIG. 2. The 1/2 selector circuit in the front row of the 1/8 selector circuit in FIG.
o 9 selection system 1 signal LSB (ao) and MSB (A
2) It is controlled by three control lines.

That is, when S=O, the 1/8 selector circuit is in the open state, all the transfer gates at the front stage are turned off, and Io(0) to I? (0) data is not accepted. At this time, the inputs of A0 to A3 are "
This is because A0 to A3 are CMOS inverters, and if the gate input is in a high impedance state, it will be at an intermediate potential between VRoro and GND, and there is a risk that static current will flow in the inverter and consume power. This is to prevent this.By doing this,
All inputs at A and '-A6 are fixed values of "L" or °゛O'', and the power consumed at Ao#A is only due to leakage, resulting in a remarkable reduction in power consumption.Furthermore, the application of the selector circuit As an example, the space switch LS in Fig. 6
Considering I, the load capacity of the buffer (BU in Figure 6) driving Io(0) to l7(0) is conventionally A0 to
The gate capacitance of A3, the gate capacitance of the transfer gate, etc. were all the load capacitance of the buffer BU, but this capacitance can be reduced. The dynamic power of CMO5 is expressed as poc f CV" (P: power consumption, f: frequency, C: load capacity, V2 power supply voltage), and power consumption can be reduced in proportion to load capacity. On the other hand, 3
When =l, the ⅛ selector circuit shown in FIG. 1 is in a connected state and always selects one of the eight inputs. At this time, it has already been stated that all buffers A and -A6 do not need to operate, and the MSB (A2
), it is possible to keep about half of the devices inactive. That is, if a2=o, A6, AI, A4,
If A6 is in the operating state or A2゜A 3 s AS is in the inactive state and a2=1, then A2 e A3 + A
If s r A& is in the active state and A6°A I, A4 is in the inactive state, the dynamic power of the selector can be reduced to about half.

In Figure 1, the number of control circuits and control l lines increases, leading to an increase in the button area.However, since the operating frequency of the control circuit is generally lower than the frequency of data passing through the selector circuit, the power consumption by the control circuit is reduced. The increase is negligible.

Furthermore, since the scale of the control circuit excluding the selection control signal holding circuit remains constant even as the scale of the selector increases, the present invention is more effective for large-scale selector circuits such as 4B trees with 32 inputs. It becomes noticeable. In Figure 1, the transistor Q for fixing the input voltage of the buffer is P-ah)
Using a transistor, the output O0 in the open state is set to 0 in Figure 5.
The same polarity as 0 (“O” in this case) was used, but of course N-
ch transistor and the inverted signal f in Fig. 5 as a control signal.
, , f2 and adding one stage of inverter to the final stage can also achieve the same reduction in power consumption.

Further, although the example using FIG. 2(B) as the 1/2 selector circuit has been described, it goes without saying that the same effect can be achieved when the circuit of FIG. 4(A) is used.

(Effects of the Invention) As explained above, by applying the circuit described in this invention to a CMOS selector circuit, it is possible to reduce unnecessary buffer power. When realizing this, there are significant advantages in terms of operating speed and power consumption.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the selector circuit (1/8 selector circuit) of the present invention, Fig. 2 is a diagram showing the control logic of the selector circuit of the present invention, and Fig. 3 is a diagram showing one of the two selector circuits. Figure 4 is a 1/2 selector circuit, Figure 5 is a conventional selector circuit, and Figure 6 is a conventional selector circuit.
/8 selector circuits are used to create 8 incoming lines and 8 outgoing lines!
It is a diagram showing an example of configuring 18 space switches LS. lo-I,...input, Oj...output. 5ojNS6j...l12 selector. (ao l al I a2)...Control signal for selecting one of the eight transistors, Ql, Q2, Q4...N channel transistor (enhancement type), Q3, Qs, Q6...P channel Transistor (enhancement type), D...Output of 1/2 selector circuit, BU...Buffer that sends input line data to each selector. A0 to A6... Buffers used in the 1/2 selector circuit (A6 in Figure 3 is an AND circuit) S6... Control signals that determine connection or release of the 1/m selector, R0 to R2... 8 lines A circuit that holds a selector selection control signal for selecting one of the input lines, Do...Ro input signal, CLKo...R0 to R3 clock signal, SE0 to S
E,...1/8 selector circuit. BU: Sends incoming data to each selector. 0°~07: Output, b1~f,, b2~f2: Signal that controls the 1/2 selector in the front row.

Claims (1)

[Claims] 1 to select any one of m (a natural number of m≧4) inputs or to deselect all inputs.
/m In the selector circuit, the number of inputs is m=2^M (M≧2
), and the 1/2 selector circuit is expressed as (2^M
In a CMOS selector circuit in which the above 1/2 selector circuit is configured from two transfer gates and one CMOS buffer, 2^M^ in the front row
-^The 2^M transfer gates of one 1/2 selector circuit are connected to one first control signal (S_0) that determines the connection or release of the 1/m selector circuit, and one of the m inputs. Among the M selection control signals for selecting one line, one second selection control signal controls the 2^m^-^1 1/2 selector circuits in the front row (contents of R_0). and one third selector circuit that controls one 1/2 selector circuit in the last row.
Using three selection control signals (contents of R_2), if the first control signal indicates that the 1/m selector circuit is to be opened, all of the 2^M transfer gates are turned off. In addition to the state, 2^M^-^ in the front row
The CMOS buffer input of one 1/2 selector circuit is
1” or “0” as a fixed value, and the first control signal is 1.
/m selector circuit is indicated to be connected, 2^M of the 2^M transfer gates in the front row that do not belong to the path selected by the third selection control signal. ^-^ Switching in which all one transfer gate is turned off and the CMOS buffer inputs of the two 1/2 selector circuits in the front row are set to a fixed value of "1" or "0". The 2^M^-^1 transfer gates in the front row which have means (Q) and belong to the path selected by the third selection control signal are divided into one half by the second selection control signal. Control is performed to select one of the two inputs that enter the selector circuit, and the (2^M^-^1-1) 1/
1. A CMOS selector circuit characterized in that the 2-selector circuit is controlled by (M-1) selection control signals excluding a second control signal.