JPH09265782A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To gain setup margin and to enable high-frequency operation in a high-speed synchronous LSI such as memory circuits by speeding up internal address signals for internal clock signals. SOLUTION: The decoder having latch function 2 is composed integrally of a decode section and a latch section. While the decode section is formed of a NAND gate 7 and an inverter 8, the latch section is formed of first transmission gate groups 3, 4 and second transmission gate groups 5, 6. Each of the transmission gates 3-6 is composed of a PMOS and a NMOS and its on-off operation is controlled by supplying external clocks to the gate. Thus, two stages of the inverters for which the internal address system is used are eliminated to speed up the internal address signals and to secure the setup margin for the internal clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly to an LSI that operates in synchronization with a high-speed external clock.
The present invention relates to a decoder with a latch function or a register function used for, for example,

[0002]

2. Description of the Related Art In recent years, high-performance microprocessors (M
PU) has dramatically improved the performance of workstations and personal computers.
In the multimedia era that handles a huge amount of data such as voice, a computer with higher processing capability is required. Therefore, it is necessary to improve not only the performance of the MPU but also the access speed of peripheral LSIs such as a memory and a controller.

In order to realize such high-speed processing of the LSI, the rise (or fall) of the external clock
A pipeline method for synchronizing apparently with the edge of and speeding up the apparent access is widely adopted for MPU, memory, and the like.

First, an outline of the operation of the memory using the above-mentioned pipeline method will be described with reference to FIGS. 8 and 9.

FIG. 8 is a block diagram showing an example of a conventional high speed synchronous memory circuit. As shown in FIG. 8, in order to simplify the explanation, this memory circuit is omitted from the input of the control system, but comprises a data input section, an internal access section, and an output section. The input is external clock C
The LK input buffer 19 and the next-stage driving buffer 20 are provided with the address signal ADD input buffer 19 and the input register 26. The internal access unit decodes the address data from the input register 26.
14a, a second decoder 21 for further decoding based on the output of the first decoder 14a to determine a memory selection address, a memory cell 22, and small-amplitude data from the memory cell 22. And an output register 24 for temporarily holding the output of the sense amplifier / multiplexer 23 based on the external clock CLK, and a data of the output register 24. Is output to the memory output terminal OUT.

In such a memory circuit, in order to synchronize with the external clock CLK, the registers 26 and 24 are arranged in the subsequent stage of the input buffer 19 and the previous stage of the output buffer 25. External clock CLK
Address data A at the rising edge (or falling edge) of
DD is taken in and data is output at the rising (or falling) of the next cycle of the external clock.

Here, the read operations of the asynchronous and synchronous memories will be compared. In the asynchronous memory read operation, if address information is input, the data written in the memory cell is output as it is, so the access time is the time from address input to data output. On the other hand, in the case of the synchronous memory of FIG. 8 using the pipeline method, the data output comes after the next cycle of the external clock. However, since the data stored in the output register 24 is read at the rise (or fall) of the external clock, the access time becomes much faster than that of the asynchronous type. Therefore, when reading continuously,
The pipeline method has an overwhelmingly larger number of data read per unit time.

FIG. 9 is a block diagram showing another example of a conventional high speed synchronous memory circuit. As shown in FIG. 9, this memory circuit is different from the circuit of FIG.
The positions of a and the register 26 are exchanged. That is, in the circuit of FIG. 9, when the external address signal is input sufficiently before the external clock CLK, the address signal passes through the address input buffer 19 and the first decoder 14a by the time difference (setup time). Available in between. Therefore, as compared with the circuit of FIG. 8, the circuit of FIG. 9 has a smaller number of logic stages after the input register 26, so that the internal access time becomes shorter and high frequency operation becomes possible.

FIG. 10 is a circuit diagram of the decoder section and the register section in FIG. As shown in FIG. 10, this circuit is composed of a plurality of decoder units 14a and a plurality of register units 26, and each register unit 26 has a latch unit 28A, 2A.
It is composed of two stages of 8B.

First, the decoder section 14a inverts the output of the NAND gate 7 and the 2-input NAND gate 7 which inputs the address data from the address signal line (Q0, Q0 inversion, Q1, Q1 inversion) 1 in combination. It is composed of an inverter 27. The latch unit 28A in the previous stage of the register unit 26 inverts the output of the first transmission gate 15A that receives and transfers the output of the inverter 27 that is the output of the decoder unit 14a. Latch section 2 in the latter stage
Inverter 17A for outputting to 8B and inverter 17A
18A for inverting the output of the inverter and a second transmission gate 16A for receiving and transferring the output of the inverter 18A. Moreover, these first and second transmission gates 15A and 16A
Are composed of a pair of PMOS and NMOS, respectively, and their operations are controlled by the external clock CLK inversion together with the NMOS of the transmission gate 15A and the PMOS of the transmission gate 16A. Similarly, the operation of the PMOS of the transmission gate 15A and the NMOS of the transmission gate 16A is controlled by the external clock CLK. Further, the circuit configuration of the latch section 28B in the subsequent stage is similar to that of the latch section 28A in the previous stage, but the transmission gates 15B and 16B are provided.
The clock input for is reversed. The circuit operation is high active (high selection) for the memory cell 22, and when two inputs from the signal line 1 are both high (H), high (H) is output to the output DO. The other decoder section 14a and register section 26 have the same configuration and operation.

FIG. 11 is a timing chart for explaining the operation of the register section in FIG. As shown in FIG. 11, when the register unit 26 is arranged after the decoder unit 14a, the external input address ADD and the external input clock CL are
When the time difference of K is set as external setup and the time difference between the internal address input to the register section 26 and the internal clock input to the register section 26 is set as internal setup, the time at which the external input address signal reaches the register section 26 (address delay) And external clock CLK input buffer 1
The timing of the time (clock delay) when the internal clock signal obtained via 9 and 20 reaches the register unit 26 becomes a problem.

This is because when the internal address signal approaches the internal clock signal, that is, when the address delay increases, the latch portion 28, which is the preceding stage portion of the register portion 26, is detected.
Since A cannot capture (latch) the address signal, it is necessary to further delay the internal clock in order to reliably capture the address data.

[0013]

The conventional semiconductor integrated circuit described above, particularly a high-speed synchronous LSI such as a memory circuit, is
When the internal address signal approaches the internal clock, the internal setup becomes short, that is, there is no setup margin. Therefore, the internal clock must be delayed in order to reliably capture the data.

However, if the internal clock is delayed, the fetching of the address signal will be delayed, and the internal access will also be shifted later. For example, when considering the reading after writing in the SRAM, if the writing in the previous cycle is delayed, the recovery of the writing potential is also delayed, so that the reading in the next cycle is also delayed. Therefore, in order to keep the read time within the standard, it is necessary to lengthen the cycle of the external clock itself.

As described above, in the conventional semiconductor integrated circuit, the access time to the address signal register must be shortened in order to surely fetch the data such as the address and enable the high frequency operation. Since there are a large number of logic gate stages such as inverters, there is a drawback that internal setup cannot be taken sufficiently.

It is an object of the present invention to provide a semiconductor integrated circuit in a high-speed synchronous LSI such as such a memory circuit, which can speed up an internal address signal with respect to an internal clock signal to increase a setup margin and enable a high frequency operation. is there.

[0017]

The semiconductor integrated circuit of the present invention has a pair of PMs for transferring input data.
A first transmission gate group in which an OS transistor and an NMOS transistor are connected in parallel and whose on / off is controlled based on an external clock supplied to the gate, and an output of the first transmission gate group are input and NAND logic is input. Alternatively, by taking the NOR logic, the NAND gate or NOR which is the decoded output
A gate, an inverter for inverting the output of the NAND gate or the NOR gate, and a pair of PMOSs
A transistor and an NMOS transistor are connected in parallel, the external clock is supplied to the gate to control ON / OFF, the output of the inverter is input together, and each output is input to the NAND gate or NO.
It is configured to have a decoder with a latch function, the decoder having the same number of second transmission gate groups as the first transmission gate groups supplied to the input of the R gate.

In the decoder with a latch function according to the present invention, a decoder with a register function can be constructed by connecting a latch section consisting of a transmission gate and an inverter in a subsequent stage.

Furthermore, the decoder with a latch function and the decoder with a register function in the present invention can be applied to a logic decoder section of a synchronous LSI.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a decoder with a latch function showing an embodiment of the present invention. As shown in FIG.
The decoder circuit with a latch function in this embodiment is
This is a circuit for decoding a two-input address, and is to integrate the decoder unit 14a and the latch unit 28A in the conventional example of FIG. 10 described above.

Therefore, in this embodiment, in order to transfer the address input data input via the address signal line 1, a pair of PMOS transistors and NMOS transistors are connected in parallel and are supplied to the gates. Transmission gates 3 and 4 controlled to be turned on / off based on external clocks CLK and CLK inversion, a 2-input NAND gate 7 having two inputs to the outputs of these transmission gates 3 and 4, and an NA
An inverter 8 for inverting the output of the ND gate 7 and a pair of PMOS transistor and NMOS transistor are connected in parallel, and an external clock CLK and CLK inversion are supplied to the gate to control ON / OFF.
The same number of transmission gates 5 and 6 are provided to input the outputs of the inverters 8 and to supply the respective outputs to the inputs of the NAND gate 7.

In the concrete operation of the decoder 2 with the latch function, first, an input buffer (not shown) is used,
When Q0 and Q1 of the address signal line 1 become high, the external clock CLK becomes low (the CLK inversion is high) for the data.
, The transmission gates 3 and 4 are in the ON state,
Since the transmission gates 5 and 6 are turned off, the NAND gate 7 outputs low and the inverter 8 outputs high. Then, at the moment when CLK changes to high, the transmission gates 3 and 4 change to the off state and the transmission gates 5 and 6 change to the on state. At this time, a closed loop is formed between the transmission gates 5 and 6, the NAND gate 7, and the inverter 8,
Holds the low output of the NAND gate 7. Note that CLK
, The transmission gates 3 to 6 are turned on and off for a moment, but there is no problem because the output of the inverter 8 and the potentials of the two pairs of address lines Q0 and Q1 are both high. Therefore, the decoder 2 at this time outputs the row selection signal, and the other decoders 2 output high.

Next, when Q0 and Q1 of the signal line 1 become low, the NAND gate 7 outputs high and the inverter 8 outputs low. Also at this time, when the CLK is switched, the transmission gates 3 to 6 are turned on for a moment.
Although it is turned on, there is no problem because the outputs of the address lines Q0 and Q1 and the inverter 8 have the same low potential. At this time, the decoder 2 outputs the non-selection signal high.

On the other hand, when Q0 and Q1 of the signal line 1 are different from high and low, the NAND gate 7 outputs high and the inverter 8 outputs low. At this time, when the transmission gates 3 to 6 are on / on for a moment between the high level of the signal line Q0 and data, the data will collide. However, since the row of the signal line Q1 is taken in by one of the NAND gates 7, the output high of the NAND gate 7 does not change. That is, the output terminal DO normally holds the non-selection signal high.

The above is the operation of the decoder 2 with a latch function connected to the signal lines Q0 and Q1, but the other decoders 2 are also operating in any of the combinations described above. In short, the input from signal line 1 is high,
Only the decoders 2 in the combination of high output the selection signal low, the other decoders 2 output the non-selection signal high, and those signals are latched at the same time as the decoding.

As described above, this embodiment corresponds to the circuit excluding the latter-stage latch section 28B of the register section 26 of FIG. 10 described above, but it is clear by comparing this with the circuit of FIG. The number of logical stages can be reduced by two.

FIG. 2 is a circuit diagram of a decoder with a latch function showing another embodiment of the present invention. As shown in FIG. 2, this decoder circuit with a latch function 2 is typically 1
Only two circuits are shown and compared with the decoder circuit shown in FIG.
It is the same except that the R gate 9 is used. For this reason,
Logically, when the data from the address signal line 1 supplied to the transmission gates 3 and 4 are both low,
It is the same except that high is output (high selection) to the decoder output DO. For example, by using a NOR decoder, the number of logic stages is reduced, and the synchronous type L can be speeded up.
This circuit is effective for SI.

FIG. 3 is a circuit diagram of a decoder with a latch function showing another embodiment of the present invention. As shown in FIG. 3, the decoder circuit 2 with the latch function is also typically 1
Only one circuit is shown. Compared to the decoder circuit of FIG. 1 described above, a 3-input NA is used instead of the 2-input NAND gate 7.
Using the ND gate 12, the first transmission gate group for transferring address data from the address signal line 1 is provided with the gate 10 in addition to the gates 3 and 4, and the second transmission gate group is provided with the gates 5 and 6. It is a circuit to which a gate 11 is added, and is otherwise the same. Therefore, logically, when the data from the address signal line 1 supplied to the transmission gates 3, 4, and 10 are both high, a low is output to the decoder output DO (row selection), that is, 8 blocks not shown in the figure. Select only one block in the row.

FIG. 4 is a circuit diagram of a decoder with a latch function showing another embodiment of the present invention. As shown in FIG. 4, the decoder circuit 2 with the latch function is also represented by 1
Only two circuits are shown and compared with the decoder circuit of FIG. 3 described above, a 3-input N gate is used instead of the 3-input NAND gate 12.
It is the same except that the OR gate 13 is used. Logically, when the data from the address signal line 1 supplied to the transmission gates 3, 4, 10 are both low,
High is output to the decoder output DO (high selection), that is, only one of eight blocks (not shown) is selected high.

Up to this point, the decoder circuit 2 with a latch function has been described using the 2-input type and 3-input type NAND gates and NOR gates. However, the present embodiment is not limited to these, and as long as the operating voltage allows, NA of 4 or more inputs is used.
The same can be realized by using the ND gate and the NOR gate. Further, it goes without saying that the decoder circuit with a latch function 2 can be applied not only to the address decoder circuit but also to a circuit that needs to latch logically processed data.

FIG. 5 is a circuit diagram of a decoder with a register function showing another embodiment of the present invention. As shown in FIG. 5, the decoder with register function 14 includes transmission gates 15, 16 and an inverter 17, in addition to the latter stage of the decoder with ratter function 2 in FIG.
This is a circuit modified to have a register function by adding a latch unit formed from 18. Logically, the output of the circuit of Figure 1 is reversed. That is, when both inputs are high, a high level is output at the output DO.

FIG. 6 is a block diagram of a high speed synchronous memory circuit to which the decoder circuit shown in FIG. 5 is applied. As shown in FIG. 6, this memory circuit is the same as FIG. 9 described above except that the decoder 14 with a register function is used. Compared with the circuit of FIG. 10 described above, the number of inverter stages from the external address input to the register 14 can be reduced by two, so that the speed of the internal address signal can be increased.

FIG. 7 is a timing chart for explaining the operation of the register section in FIG. As shown in FIG.
By using the decoder with register function 14 as described above, the speed of the internal address signal can be increased, so that the setup for the internal clock can be increased and the input address signal can be reliably taken in.

On the other hand, if there is a margin in the setup originally, the internal address signal can be taken in faster by increasing the timing of the internal clock. This speeds up the internal access operation and speeds up the transition to the next cycle operation, so that high-frequency operation can be performed.

Although the decoder of FIG. 5 described above is an example using the 2-input NAND 7, as described above, a 2-input NOR gate may be used, and further, a 3-input or more NAND gate or It goes without saying that it is possible to use the NOR gate as well.

[0037]

As described above, the semiconductor integrated circuit of the present invention has the conventional structure in which the first-stage decoding circuit and the latch circuit or the register circuit are integrated in order to increase the speed of the synchronous LSI, especially the memory circuit. Compared with the separated circuit, the number of logic stages using the inverter can be reduced by two, the transfer speed of the internal address system can be increased, and the setup margin for the internal clock can be increased.

For example, the 0.5 μm CMOS process is
By reducing the number of gates by 2 stages, the speed is increased by about 0.3 ns, which is extremely effective in a high-speed synchronous LSI or the like having a severe setup margin.

Further, the present invention has an effect that if the setup margin is originally present, the high speed operation of the internal clock enables the high frequency operation, thereby sufficiently meeting the demand for further high speed in the future.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a decoder with a latch function showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a decoder with a latch function showing another embodiment of the present invention.

FIG. 3 is a circuit diagram of a decoder with a latch function showing another embodiment of the present invention.

FIG. 4 is a circuit diagram of a decoder with a latch function showing another embodiment of the present invention.

FIG. 5 is a circuit diagram of a decoder with register function showing another embodiment of the present invention.

6 is a block diagram of a high-speed synchronous memory circuit to which the decoder circuit shown in FIG. 5 is applied.

FIG. 7 is a timing diagram for explaining the operation of the register unit in FIG.

FIG. 8 is a block diagram showing an example of a conventional high-speed synchronous memory circuit.

FIG. 9 is a block diagram showing another example of a conventional high-speed synchronous memory circuit.

10 is a circuit diagram of a decoder unit and a register unit in FIG.

11 is a timing chart for explaining the operation of the register unit in FIG.

[Explanation of symbols]

1 Address Signal Line 2 Decoder with Latch Function 3 to 6, 10, 11, 15, 16 Transmission Gate 7 2 Input NAND Gate 8, 17, 18 Inverter 9 2 Input NOR Gate 12 3 Input NAND Gate 13 3 Input NOR Gate 14 Register Decoder with function 21 Decoder 22 Memory cell 23 Sense amplifier / multiplexer 24 Register DO Decoder output

Claims (3)

[Claims] 1. A first transmission gate group in which a pair of a PMOS transistor and an NMOS transistor are respectively connected in parallel to transfer input data and whose on / off is controlled based on an external clock supplied to the gate. , A NAND gate or a NOR gate for decoding output by inputting the output of the first transmission gate group and taking a NAND logic or a NOR logic, and the NAND gate or the NO gate.
An inverter for inverting the output of the R gate and a pair of a PMOS transistor and an NMOS transistor are connected in parallel, and the external clock is supplied to the gate to control ON / OFF, and the output of the inverter is input together and A latch-equipped decoder having the same number of second transmission gate groups as the first transmission gate groups for supplying the output of the above to the input of the NAND gate or NOR gate. 2. The semiconductor integrated circuit according to claim 1, wherein the decoder with a latch function is connected to a latch section including a transmission gate and an inverter in a subsequent stage to form a decoder with a register function. 3. The semiconductor integrated circuit according to claim 1, wherein the decoder with a latch function and the decoder with a register function are used in a logic decoder section of a synchronous LSI.