JPS58161447A - Reproducer for pcm signal - Google Patents

Abstract

PURPOSE:To execute the correction of a reproduced PCM signal with a very simple circuit constitution, by finding the difference between PCM signals having very close areas of ''1'' and ''0'' and obtaining a correction voltage based on this difference. CONSTITUTION:When a PCM signal 1' having distortion reproduced from a magnetic tape is inputted to a (-) terminal of a comparator Comp of a correction circuit 13 and an arbitrary correction voltage V+ is applied to a (+) terminal from an analog subtractor 9, a PCM signal 1 wave-shaping the aid PCM signal 1' is outputted from the comparator Comp. A specific area length detection circuit 10 detects the area of ''1'' or ''0'' having a specific length with data latched at a latch circuit 3. The latch data of latch circuits 4, 5 are given to the 1st and the 2nd D/A converters 6, 7 respectively and converted into an analog quantity. The circuit 13 determines the cross point with the PCM signal 1' having the said distortion given to the terminal (-) with this correction voltage V+ and demodulates the normal PC signal.

Description

[Detailed description of the invention] The present invention relates to a PCM signal reproducing device.

When a PCM signal recorded on a magnetic tape or magnetic disk is reproduced by a detector, a distorted PCM signal as shown in FIG. 1(a) is generally obtained.

In order to reproduce this as a correct PCM signal as shown in (b) of Fig. 1, the above signal (a) is generally introduced into the (to) pole of the comparator Comp of the correction circuit as shown in Fig. 2. and waveform adjustment is performed.

In short, the correction voltage ■+ is applied to the (G) pole of the comparator Comp.
This is an extremely important issue because the data error rate will change significantly depending on the adjustment of this value. On the other hand, in the reproduced PCM data, the times of "l" and "0" are generally not the same, and even if the two are averaged and matched, it is not necessarily well adjusted. Not exclusively. The present invention provides a reproducing circuit including a device that automatically adjusts this cross point, thereby improving the data error rate and stabilizing the PC.
This makes it possible to obtain an M reproducing device.

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a differentiator, 2 is a counter, 3°4.5 is a latch circuit, and 6.7 is a first... 2nd D/A converter, 8 is an analog switch, 9 is an analog subtracter that cuts off high frequencies,
10 is l′” or “0” of a certain length of the PCM signal
11 is an exclusive OR circuit, 12 is a Nants gate, and 13 is a comparator Comp which receives the reference voltage from the analog subtracter 9 at its (T) pole.
The (C) pole of the comparator Comp is configured to receive a distorted PCM signal reproduced from a magnetic tape, etc., and the (G) pole is configured to receive a constant voltage (based on +V, -V). ) is obtained.

Further, O8C is a clock oscillator that outputs a clock with a frequency that is multiple times the transfer frequency of the PCM signal (for example, if the transfer frequency is 3 pits + 8 times the frequency).

The present invention is constructed in a diagonal manner, and its operation will now be described with reference to the waveform diagram of FIG. 4.

Now, the amount of the distorted PCM signal reproduced from the magnetic tape is input to the comparator Comp (7) (to) pole of the correction circuit 13, and an arbitrary correction voltage is input from the analog subtracter 9 to the (a) pole. When + is applied, when the comparator Comp inputs the PCM signal amount obtained by shaping the waveform of each PCM signal, the PCM signal signal amount portion enters the differentiator l and becomes a differentiated pulse (2).

Further, the clock pulse (2) from the clock oscillator O8C is input to the frequency divider 2. This frequency divider 2 can repeat the frequency division operation of the clock pulse (2) every time the differential pulse (2) is input.

Also, the output of this frequency divider ■ and the above PCM signal ■ are the following first
The data is latched by the latch circuit 3 of the PCM signal chain, and the length of the "l" or "0" region in the PCM signal chain, and the data as to whether it is a "1" region or a "0" region. Become.

Next, based on the data latched by the first latch circuit 3, the specific area length detection circuit IO detects a specific length of "sl".
+ or “0” area is detected.

That is, the specific region length detection circuit 10 detects a region length of 0' or 0' in the PCM signal chain, which is set to 6 in this embodiment.

Further, from another output terminal of the first latch circuit 3, a signal ``15'' or ``O'' of the same PCM signal level is output, which is transmitted to the next second latch circuit 4 and the exclusive logic circuit. 11.

Now, when the first latch circuit 3 latches the region T' of "6" in the PCM signal chain (the part ■' in the signal ■), the specific region length detection circuit 10 detects it. Detects and outputs signal ■ (special d).

Then, at the same time as the output of this pulse ■, the Nant gate 12 outputs a transfer command pulse ■ (see especially) that is equal to the pulse width of the differential pulse ■. The third latch circuits 4 and 5 each receive and latch the previous stage latch data at the rising edge of this transfer command pulse (2). The data that was latched in (the part ■'' in the signal ■, the PCM signal amount data whose length of “0” corresponds to “6” is actually the value of “6” plus the deviation)
The second latch circuit 4 latches the first
The length of the PCM signal amount l'' just latched by the latch circuit 3 of is data regarding "6" (actually, the value is "6" plus the deviation).

And these second. The latched data of the third latch circuits 4.5 and 4.5 are respectively latched by the first . The signals are supplied to second D/A converters 6 and 7 and converted into analog quantities.

The next analog switch 8 switches its contact depending on whether the data latched in the second latch circuit 4 is in the '1' area or the '0' area. The data latched in the latch circuit 4 is “l”
”, the state as shown in the figure is taken, and therefore the analog value of the first D/A converter 6 is the same as that of the analog switch 8.
to the (+) pole of the amplifier of analog subtracter 9 via
The analog values of the second D/A converter 7 are supplied to the (-) pole of the amplifier of the analog subtracter 9 via the analog switch 8, respectively.

The analog subtracter 9 executes the subtraction operation of both inputs,
The output of the correction circuit 13 is based on the substantial difference in length between the latched "l" and "0" regions.
A correction voltage V+ (see waveform 2 in FIG. 4) is outputted to the (+) pole of the comparator COMP via the midpoint e(r).

The correction circuit 13 determines the crossing point with the PCM signal σ having the distortion given to the (-) pole by this correction voltage V+, and demodulates the normal PCM signal.

The present invention calculates the difference between the PCM signal in the "1" and "θ" regions, which are extremely close in length, as shown in the description above, and obtains a correction voltage based on this difference. Since it is designed to detect the cross point with the PCM signal and obtain a regular PCM signal, it can be reproduced with an extremely simple circuit configuration and
CM signal correction f: This is an excellent invention that can be implemented.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram explaining the relationship between a distorted PCM signal and a normal PCM signal, and Figure 2 is a diagram explaining the relationship between a distorted PCM signal and a regular PCM signal.
3 is an electric circuit diagram showing an embodiment of a PCM signal reproducing device according to the present invention; FIG. 4 is an output waveform diagram of each part of FIG. 3; FIG.

Claims (1)

[Claims] 1. A latch means that simultaneously latches a specific length consisting of the 'l'' and "0" areas in the PCM signal, and a latch means that simultaneously latches the 'tl+' area and the '0' area output from this latch means. A subtraction circuit means for detecting a substantial difference in length and obtaining a correction voltage from the difference, and a PC connected to one input terminal before correction.
A PCM signal reproducing device comprising comparison means for inputting an M signal and inputting a constant voltage plus the correction voltage to the other input terminal.