JPS58203635A - Data waveform shaping circuit - Google Patents

Abstract

PURPOSE:To perform data waveform shaping at an optimum slice level, by having an automatic control of the slice level while monitoring the data error factor and securing the follow-up not only to the attenuation of a high band due to a pickup but to the variation of the DC component owing to the disk variance. CONSTITUTION:An AC signal of 1-cycle/2-revolution is applied to an X input terminal of a synchronous wave detector; while a signal obtained by integrating an error flag is applied to a Y input terminal. If the voltage level is excessively high for the DC component of the slice level of a comparator 6, the error factor is increased and decreased with the rise and the fall of X respectively. As a result, the DC component of a product XY is positive. On the contrary, the error factor is decreased and increased with the rise and the fall of X respectively when the above-mentioned voltage value is excessively low. Thus the DC component of the product XY is negative. If the slice level is proper, the error factor is increased with the rise and the fall of X. Then the DC component of the XY approximates to 0.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data punching circuit, and more particularly, to providing a data punching circuit suitable for a reproducing apparatus that reproduces the entirety of a disc on which digital information signals are recorded.

Along with advances in digital signal processing technology, so-called digital recording and playback technology that digitizes and records and plays back audio signals has also progressed, and in the audio field, digital recording and playback devices such as digital audio disks (hereinafter abbreviated as DAD) have also made progress. is being put into practical use.DAD is an application of video disk technology and is characterized by extremely high recording density.

As a result of high-density recording, the recording wavelength becomes shorter, which poses a problem in waveform reproducibility during playback. This is due to the frequency band limitations of optical pickups and the like, and when a rectangular wave signal recorded as a digital signal is reproduced, its corners become rounded and the rectangular wave cannot be reproduced. For this reason, it has been conventional practice to perform complete waveform shaping using a level comparator, Schmitt trigger, etc. to reproduce the original waveform. This is what is called data punching, and here is a conventional example of it! 2.

FIG. 1(a) shows an example of a data punching circuit using a U-level comparator.

The reproduced signal A is applied as an input signal to the input terminal 2 of the level comparator 1, and it is compared in magnitude with the slice level B determined by the reference power supply 3, and the result is output as a rectangular wave digital output signal C. Output to terminal 4. The slice level C is generally also called a punching level or a reference voltage.

Figure 1(b) compares the input signal A, slice level B, and output signal C in Figure 1(a).The input signal A has a waveform with high frequency components attenuated due to the influence of the pickup. There is. As a result, it is no longer possible to reproduce the original waveform in high frequency parts.

In addition to the above-mentioned high-frequency attenuation, the original waveform may not be reproduced due to variations in the disc, and in particular, the DC component of the reproduced waveform may vary greatly depending on the exposure conditions when creating the master disc. Conventional data punching circuits are unable to follow such fluctuations, and therefore are unable to reproduce the original waveform, resulting in data errors.

The present invention takes the above-mentioned problems into account and provides a data punching circuit that changes the slice level accordingly while monitoring the correctness of data.An example of the present invention will be described below. explain.

FIG. 2 is a block diagram showing an example of a DAD reproducing device to which an embodiment of the data punching path of the present invention is applied. Machine 3 is installed coaxially. The information signal recorded on the disc 1 is detected by the pickup 4, amplified by the preamplifier 6, and then sent to the level comparator 6.
Enter the data punching circuit centered on . The digital signal restored to the original waveform is sent to a demodulator 7, an error detection circuit 8, and a D/A.
The signal is converted into an analog signal via the converter 9 and output to the output terminal 10.

Level converter, parator 6 slice level III K
A constantly changing voltage is applied from the two Id systems, and a feedback operation is performed by monitoring changes in the data error rate due to changes in the slice level. In the first system, the output signal of the frequency generator 3 is converted into a 1-cycle/2-rotation rectangular wave by the frequency divider 11, and its fundamental wave component is extracted by the low-pass filter 12. It is an alternating current signal with a frequency of one cycle per two rotations.

In the second system, the error flag signal, which is the output signal of the error detection circuit 8, is integrated by the integrator 13 and the above-mentioned 1 cycle/2 revolution AC signal is synchronously detected by the synchronous detector 14, and then a low-pass signal is detected. This is a signal from which high-frequency components have been removed by the filter 15.

The synchronous detector 14 can be configured using, for example, an analog multiplier, and for two analog input signals X and Y, the product XY is obtained as the output signal 2.

FIG. 3 is a waveform diagram of each part explaining the entire operation of the synchronous detector 14 in FIG. 2.

An AC signal of one cycle/two rotations is applied to the X input terminal of the synchronous detector, and a signal obtained by integrating the error flag is applied to the Y input terminal.

At this time, how the output 100 z (=xy) changes depending on the voltage value of the DC component of the slice level of the level comparator 6. Figure 3 shows how this happens when all slice levels are too high. Figure 3 (
In b), the case where the temperature is too low is shown in FIG. 3 fcl.

If too high, an increase in X will increase the error rate and
Since the fall in the error rate reduces the error rate, the DC component of the product xY becomes positive. Conversely, if it is too low, an increase in X will decrease the error rate, and a decrease in X will increase the error rate, so the DC component of the product XY will be negative. If the slice level is appropriate,
Whether X rises or falls, the error rate increases and the DC component of the product XY approaches zero.

If the output signal z20 of the synchronous detector 14 is smoothed by the pass filter 16 in this way, the following DC voltage will be obtained depending on the change in the slice level.

When it is too high...... Positive When it is optimal...... When it is too low...... Negative Therefore, before it is fed back to the level comparator 6 It is necessary to perform inertia reversal. Adder 1 in Figure 1
6 has one side closed as an inverting input.

With the above configuration, negative feedback is applied to the slice level of the level comparator 6, so that the data error rate always follows the minimum level.

In the above embodiment, the frequency of the AC signal superimposed on the slice level is set to 1 cycle/2 revolutions, so that the error rate can be compared between adjacent tracks even when there is a large scratch on the disk. This is because it has the advantage that it cancels out and has no effect.

As described above, the data punching circuit of the present invention automatically adjusts the slice level while monitoring the data error rate, so it eliminates the high frequency attenuation caused by the pickup and the DC component caused by disc variations. Follows changes,
Data punching can be performed at the optimal slice level,
Furthermore, it is less susceptible to scratches on the disc, which has great practical effects.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram of a conventional data punching circuit, FIG. 1(Φ) is a signal waveform diagram of each part of the conventional example, and FIG. 2 is a block diagram representing an embodiment of the data punching circuit of the present invention. 3 are signal waveform diagrams of various parts for explaining the operation of the synchronous detector of the above embodiment. 4... Pickup, 6... Level comparator, 7... Demodulator, 8... Error detection circuit, 11... Frequency divider , 12...
・Low pass filter, 13...Integrator, 14・
... Synchronous detector, 16 ... Low pass filter, 16 ... Adder.

Claims (1)

[Claims] means for reproducing a digital information signal recorded on a disk; comparing means for comparing the reproduced signal with a slice level and outputting a digital signal; and modulating the slice level with an alternating current signal having a frequency synchronized with the rotation of the disk. and synchronous detection means for detecting the correlation between the integral value of the data error detection signal in the digital signal and the alternating current signal, and the detection output signal of the synchronous detection means is used as the slice level to be sent to the comparison means. A data punching circuit characterized in that it returns data.