JPH02161662A - Signal processor - Google Patents

Abstract

PURPOSE:To prevent a burst error from occurring by providing a comparator, first and second reference signal generation circuits, and a reference signal switching means. CONSTITUTION:When the content of an input signal Si is changed to data leading data, the reference signal switching means 15 is switched, and the input signal Si is compared with first and second reference signals S,(A) and S,(B) by the comparator 11. When data is the one for clock generation, an accurate clock is generated based on the first reference signal S,(A) generated at fast response speed by the first reference signal generation circuit 13. Also, when it is reproducing data, the signal is converted to a stable digital reproducing signal So based on the second reference signal S,(B) generated at low response speed an not being influenced by a noise by the second reference signal generation circuit 14. In such a manner, it is possible to prevent the burst error from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a signal processing device for converting an analog signal read from a magneto-optical disk or the like into a digital signal.

<Prior Art> Conventionally, as a signal processing device for reading from a magneto-optical disk or converting an analog signal into a digital signal, there is a device shown in FIG. 3. The information recorded on the magneto-optical disk is read by the magneto-optical disk reader, and the analog input signal Si read from the magneto-optical disk is converted into a comparison circuit of the signal processing device! is input. At the same time, the - input signal Si is input to the reference signal generation circuit 2. Then, this reference signal generation circuit 2 generates a reference signal S based on the input signal Si inputted thereto.
This reference signal Ss is input to the comparator circuit l. The comparison circuit 1 compares the input signal Si inputted thereto with the reference signal Ss as shown in FIG. 4(a).

As shown in FIG. 4(b), when the input signal Si is larger than the reference signal Ss, it is "B", and when the input signal Si is smaller than the reference signal Ss, it is "0". A certain digital output signal So is output.

When the reference signal Ss is generated by the reference signal generation circuit 2, there are two methods: (A) which processes the input signal Si with a fast response speed as shown in FIG. 5(a);
As shown in b), there are two methods: method (B) in which the input signal Si is processed with a slow response speed. Here, Fig. 5 (
The input signal Sj in a) and FIG. 5(b) shows only the peak waveform. Further, the reference signal S8 is generated as a slice signal passing through the center of the peak value of the waveform consisting of the envelope of the waveform of the input signal Si, and based on the generated reference signal Ss and the input signal Si, the above-mentioned Thus, the output signal So, which is a digital signal, is generated.

Usually, the first part of the input signal S'I reproduced from the magneto-optical disk is used to generate a timing clock for reading the digital output signal So obtained by converting this input signal Si by a signal processing device. There is data for clock generation.

Generate a clock by processing this clock generation data 4
When moving, the input signal Si must be followed by a method (A) with a fast response speed in order to generate an accurate lock. On the other hand, when processing playback data to generate data at the beginning of the data, if the response speed is fast, it will react sensitively to noise components, so the data will become unreadable immediately after the noise occurs, making it easy to cause burst errors (continuous errors). . Therefore, when processing reproduced data, it is necessary to process the input signal Si using the slow response speed method (B) 1 to avoid the influence of noise.

Therefore, when actually generating the reference signal Ss, priority is given to clock generation, and the reference signal Ss is generated by slowing down the response speed as much as possible within the range that allows accurate lock generation. ing.

<Problems to be Solved by the Invention> As described above, in the conventional signal processing method described above, when generating the reference signal Ss based on the input signal Si from the magneto-optical disk, the input signal Si is The response speed is made as slow as possible while still being able to generate accurate locks from the data. However, in the conventional signal processing device described above, although the response speed is made as slow as possible within the range that allows accurate lock generation, the response speed is still too fast, making it susceptible to noise and prone to burst errors. There is.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a signal processing device that is less susceptible to noise and can generate a more accurate lock.

Means for Solving the Problems> In order to achieve the above object, the signal processing device of the present invention has the following features:
a comparison circuit that compares an input signal including clock generation data, data leading data, and reproduction data with a first or second reference signal and outputs a binary output signal based on the comparison result; and the input signal a first reference signal generation circuit that takes in the input signal and processes it at a fast response speed to generate the first reference signal; and a first reference signal generation circuit that takes in the input signal and processes it at a slow response speed to generate the second reference signal. and a second reference signal generation circuit that generates the first reference signal, and when the content of the input signal is clock generation data, the first reference signal from the first reference signal generation circuit is switched to the comparison circuit. The present invention is characterized by comprising reference signal switching means for inputting a second reference signal from a second reference signal generation circuit to the comparison circuit when the content of the input signal is reproduction data.

<Function> At the same time that an input signal including clock generation data, data start data, and reproduction data is input to the comparator circuit,
The signal is input to the first reference signal generation circuit and the second reference signal generation circuit. Then, the first reference signal generating circuit processes the input signal with a fast response speed to generate a first reference signal. Meanwhile, the second reference signal generation circuit processes the input signal with a slow response speed to generate a second reference signal.

When the content of the input signal is clock generation data, the first reference signal from the first reference signal generation circuit is input to the comparison circuit. When the content of the input signal changes to the data at the beginning of the data, the reference signal switching means is switched in the data at the beginning of the data, and when the content of the input signal is reproduction data, the reference signal switching means is switched from the second reference signal generation circuit to the data at the beginning of the data. A second reference signal is input to the comparison circuit. Then, the comparison circuit compares the L input signal with the first or second reference signal, and outputs a binary output signal based on the comparison result.

In other words, in the case of clock generation data, the first
Accurate locking is generated based on the first reference signal generated by the reference signal generation circuit with a fast response speed.

In the case of reproduced data, the digital reproduced signal I is stably converted based on a second reference signal which is not affected by noise generated by the second reference signal generation circuit at a slow response speed.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a block diagram of a signal processing device in a magneto-optical disk device of the present invention. This signal processing device converts an analog input signal Si having a frequency up to about IMIIZ read from a magneto-optical disk by a magneto-optical disk reading device (not shown) into a digital output signal So.

An allilog input signal Si read from the magneto-optical disk by the magneto-optical disk reader is input to one input terminal of the comparator circuit 11.

Also, the other input terminal of the comparison circuit 11 is connected to a reference signal generation circuit! The reference signal Ss generated by 2 is input. Then, the comparison circuit 11 compares the input signal Si and the reference signal Ss as shown in the fourth YgJ(a). As shown in FIG. 4(b), when the input signal Si is larger than the reference signal SS, the digital output is "B", and when the input signal Si is smaller than the reference signal Ss, the digital output is "0°". Signal S.

Output.

The reference signal generation circuit 12 is a first reference signal generation circuit of method (A) that processes the input signal Si with a fast response speed! 3 and a second reference signal generation circuit 14 of method (B) which processes the input signal Si with a slow response speed. First reference signal generation circuit using method (A) with fast response speed! 3 is composed of an envelope type slice detection circuit that operates depending on the magnitude of the envelope of the input signal Si. Then, when the input signal Si is processed by method (A), a reference signal 5s (A) having a frequency of usually 50 KHz = 1001 (Hz) is generated. On the other hand,
The second reference signal generation circuit 14 using the slow response speed method (B) is constituted by a low-pass slice detection circuit that operates based on the low frequency component of the input signal Si. Then, when the input signal Si is processed by the method (B), a reference signal S s (B ) having a frequency of usually 10 KHz is generated. That is, in order to generate the reference signal 5s(A) and the reference signal Ss(H) by the first reference signal generation circuit 13 and the second reference signal generation circuit 14, the reference signal generation circuits 13 and 14 are provided with the reference signal generation circuits 13 and 14, respectively. The input signal Si is inputted. One unit of data of the input signal Si is written for each sector on the magneto-optical disk. The switching of the response of the reference signal Ss is determined depending on whether or not the content of one unit of data of the input signal Si is at the beginning, as will be described in detail later. Further, the switching timing is controlled for each sector by a method not shown.

First reference signal generation circuit I3 and second reference signal generation circuit 14
Control of switching between them is performed by a reference signal changeover switch amount 5 controlled by a control signal DET. Control signal DET is generated by control signal generation circuit 16. This control signal generation circuit l6 has an output signal 'r3S, for example.
Time 1 when input signal Si is applied to input signal Si based on the clock of
．． It is composed of a timer or the like that starts measuring time at , and measures the time from time t to time t. Then, when the control signal generation circuit 16 starts measuring time at time t, the value of the control signal DET is set to "B", and at time tt, the value of the control signal DET is reset to "0°". be.

The reference signal changeover switch 15 switches to the first reference signal generation circuit I3 side of method (A) when the value of the control signal DET is "0", and switches to the method (A) when the value of the control signal DET is "0".
This is a switch that switches to the second reference signal generation circuit 14 side in B). That is, the reference signal changeover switch 15 selects the reference signal S s (A) from the first reference signal generation circuit 13 of method (A) and the method (H) based on the control signal DETJ from the control signal generation circuit 16. and the reference signal 5s(B) from the second reference signal generation circuit 14.
Comparison circuit! The reference signal Ss is output to l. Did you do that?
Time t is set at the beginning of the data section for clock generation in the input signal Si, while time t is set at the beginning data section of the data (see Figure 2). While data can be processed at a fast response speed, playback data can be processed at a slow response speed.

FIG. 2(a) shows the first basic signal generation circuit 13 of method (A).
Alternatively, the data format of the input signal Si input to the second reference signal generation circuit 14 of method (+3) is shown in FIG. This is the reference signal Ss (broken line).

Further, FIG. 2(C) shows the waveform of the control signal DET.

-1- The input signal Sl is 1.1 as shown in the data format of FIG. 2(a). 6. Clock generation data for generating a timing clock when reading the digital output signal SO converted by this signal processing device.
, data head data (■) representing the beginning of the reproduction data, and reproduction data (■) which reproduced information recorded on the magneto-optical disk. Therefore, when processing the clock generation data (2), the control signal DET is set to "B" at time t based on the operation of the control signal generation circuit 16, and the reference signal changeover switch 15 is set to a high response speed. At the same time as setting it to the first reference signal generation circuit 13 side of method (A), time measurement is started on the control signal generation circuit 16i. Processed with response speed,
A reference signal 5s(A) is generated.

Next, the input signal Si changes to the first data ■,
The measurement time in the control signal generation circuit 16 is (tz−t+
) When time t reaches time t, the control signal DET becomes "O" as described in -.Then, the reference signal selector switch 15 switches to the second type of slow response speed method (B). The signal generation circuit 14 side is switched to the signal generation circuit 14. Then, the next manually inputted reproduction data ■ is processed by the second reference signal generation circuit 14 of method (B), and the reference signal S s (B ) is processed.
is generated.

That is, in the case of the clock generation data (2), it is processed by the first reference signal generation circuit 13 of the fast response speed method (A) to generate the reference signal 5s(A). In addition, in the case of reproduced data ■, it is processed by the second reference signal generation circuit 14 of the slow response speed method (i()) to generate the reference signal S s (B). Since the data ■ is processed at a fast response speed and converted into a digital signal based on the generated reference signal 5s (A), accurate lock is generated.In addition, the reproduced data ■ is processed at a slow response speed. The reference signal Ss(+3) is converted into a digital signal based on the generated reference signal Ss(+3).
3) The digital output signal S does not respond sensitively to this noise and is affected by the noise.

Burst errors are less likely to occur when converting to .

In this way, the signal processing device of this embodiment changes the reference signal changeover switch 15 to the control signal DE when generating the reference signal.
The reference signal S s (
A), and in the case of reproduced data (2), it is processed at a slow response speed to generate a reference signal Ss(B). Therefore, accurate lock can be generated based on the reference signal 5s(A), and the reference signal S
Based on s(H), the influence of noise in reproduced data can be reduced.

The control signal generation circuit 16 in the above embodiment is constituted by a timer. However, the present invention is not limited to this, and may be configured with a data head data detection means that detects the output signal So based on the data head data (2).

The reference signal changeover switch I5 in the above embodiment is the first
Needless to say, the structure is not limited to the one shown in the figure, and may be formed of logic elements, for example.

<Effects of the Invention> As is clear from the above, the signal processing device of the present invention has the following effects:
A comparison circuit, a first reference signal generation circuit, a second reference signal generation circuit, and a reference signal switching means are provided, and the above-mentioned reference signal switching means is switched when the content of the input signal is the first data of the data. What if the input signal content is clock generation data? In this case, the first reference signal generated by processing at a fast response speed is input to the comparison circuit, while if the content of the input signal is reproduction data, the first reference signal is generated by processing at a slow response speed. Since the generated second reference signal is manually input to the comparison circuit, when the content of the input signal is the clock generation data, it is processed at a fast response speed and generated as the reference signal and -J2 input. When the content of the input signal is reproduction data, the input signal is compared with a reference signal generated by processing at a slow response speed.

Therefore, in the case of the above clock generation data, accurate lock is generated based on the reference signal processed at a fast response speed. Furthermore, in the case of reproduced data, a digital reproduced signal is stably generated based on a reference signal that is processed at a slow response speed and is less affected by noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the signal processing device of the present invention, FIG. 2 is an explanatory diagram of input/output signals related to the signal processing device, and FIG. 3 is a block diagram of a conventional signal processing device. 4
Figure (a) is an explanatory diagram of the comparison between the input signal and the reference signal in the comparison circuit, Figure 4 (b) is a waveform diagram of the output signal of the comparison circuit, and Figure 5 is the reference signal generation circuit of method (A). Method (B
) is an explanatory diagram of the operation of the reference signal generation circuit of FIG. 11... Comparison circuit, 12... Reference signal generation circuit, 13... First reference signal generation circuit, 14... Second reference signal generation circuit, +5... Reference signal changeover switch, 16...・Control signal generation circuit.

Claims (2)

[Claims] (1) a comparison circuit that compares an input signal including clock generation data, data start data, and reproduction data with a first or second reference signal and outputs a binary output signal based on the comparison result; a first reference signal generation circuit that takes in the input signal and processes it at a fast response speed to generate the first reference signal; a second reference signal generation circuit that generates a reference signal;
A first reference signal from a reference signal generation circuit is input to the comparison circuit, while a second reference signal from a second reference signal generation circuit is input to the comparison circuit when the content of the input signal is reproduction data. A signal processing device comprising a reference signal switching means. (2) The signal processing device according to claim 1, wherein the input signal input to the comparison circuit is an analog signal output from a magneto-optical disk reading device.