JPS58161111A - Data recording and reproducing device - Google Patents

Abstract

PURPOSE:To record and detect synchronizing information in data, by inserting a resynchronizing pattern for showing a delimiter on the way of the data, as well as synchronizing information for showing the start of the recording data. CONSTITUTION:A readout signal 61 from the head is converted to a signal 62 corresponding to a code word recorded by a read signal processing circuit 60. This signal is applied to a timing reproducing circuit 70, and a read clock 700 is obtained. The reproducing signal 62 is applied to a synchronizing signal detecting circuits 71, 72, too. The reproducing signal 62 and said 2 synchronizing signals are supplied to a decoding circuit 80, and are converted to a data word. In this regard, the read clock 700 is used for detecting synchronization in the synchronizing signal detecting circuit 71 and 72, decoding by the decoding circuit 80, and also processing by a read data reconstituting circuit 90.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for recording and detecting synchronization information in data in a device that records data serially, such as an optical disk device.

Figure 1 shows run-length limited variable length encoding (Run-length limited variable length encoding).
th-Lim ed variable -(, eng
thCoding) The above code will be abbreviated as ALL code in the text below. Data is encoded using this code (data @ is converted to code @), and as shown in FIG. 2, the case where information is recorded one-dimensionally (that is, serially) with respect to time t is handled. In FIG. 2, 1 (l) is a synchronization signal indicating the start of recording data.

20 is a data area in which codes encoded according to FIG. 1 are recorded. Located in the middle of the IIU data section 20,
This is a delimiter signal indicating a delimiter for each fixed unit of the data section. The decoder signal 11ri is also encoded according to the RLL code encoding rules shown in FIG. 1. At the time of data reproduction, the decoder (
It has the function of synchronizing the successive code words that enter the decoder). That is, when reproducing information recorded in the form shown in FIG.
Re-synchronization pulse 1104 synchronization pulse detected from 100
functions as a backup. That is, synchronization pulse 1
If a timing shift occurs in the decoder controlled by 00 due to noise or some other cause, all subsequent data will be erroneously decoded. To prevent this, even if a timing shift occurs in a location, the resynchronization pulse 110 returns the decoder timing to normal, thereby making it possible to limit the error due to the timing shift to only the specific section where it occurs. If the error is limited to a specific section, it becomes possible to correct the error using the error correction function attached to the code.

In order to obtain the above function, it is necessary to divide the data area into several parts and insert resynchronization buttons 11 into the divided parts for recording. By the way, in the RLL code shown in FIG. 1, when converting a data candy into a code word, the number of bits of data to be converted as a unit is not fixed because of variable word length encoding. That is, 2-bit, 3-bit, or 4-bit data is encoded as a unit when the data is pressed. Therefore, when data of a certain length is encoded, data bumps cause excesses and deficiencies at the end of the code word.

On the other hand, as a resynchronization button, it is always the same regardless of the data button, and the correct synchronization pulse is generated with the shortest possible length.In other words, the position and phase of the resynchronization pulse will not shift even if noise etc. occur in the reproduced signal. It is necessary. Conventionally, a highly reliable resynchronization button and its detection method for variable word length codes as described above have not been obtained.

The present invention inserts a variable word length code in the middle of data,
The purpose of the present invention is to obtain a resynchronization button that is independent of data and has high detection reliability, and a detection device thereof.

The present invention will be explained in detail below with reference to Examples. The above-mentioned state of excess or deficiency of candy divisions at the end of the code candy can be classified into the following six cases. That is, the following cases (1) to (2) apply.

■ If there is no excess or deficiency ■ If there is one bit left over, the data ends with 0.0 If there is one bit left over, the data ends with 1.■ If there are two bits left over, the data ends with 00.0 If there are two bits left over, the data ends with 01. Case■ If there are 3 bits left over, the data is 0.
If it ends with 01, it is impossible to obtain the same resynchronization pattern in the form of a code word for all of the above cases (■ to ■), but it is possible to create a different part in at least one place depending on each case. It can be done as follows. Furthermore, the data pattern following the resynchronization button must always be a delimiter between code words. There are 18 groups of bangs that satisfy this condition, but in order to improve the reliability of detection, the distance between symbols between normal timing and the bangs that occur at timings that deviate from normal must be large. Based on the above conditions, when the length of the resynchronization section is set to 1 byte, the best option would be a bang in which the data candy @10111010' is encoded according to the rules shown in FIG.

FIG. 3 shows what happens when the resynchronization button is pressed or in the cases ① to ① described above.

In FIG. 3, the symbol M indicates the place where the code words are separated. As is clear from the figure, two deviations occur in the converted recording pattern due to the previous data pattern. However, if you carefully consider this slam, it will always be the same as the one in Figure 3 e), except that the part marked with an X is uncertain. Furthermore, one of the two X parts is always 1. Therefore, as a reference or reference button, take the button in Figure 3 eJ and compare it with the read code word and the reference button above, and if at least one of the X-marked parts is "1", it is considered a match. , the verification result when the timing is shifted in the positive and negative directions with respect to the normal timing position Δ1=0 is as shown in FIG. In the figure, d in the vertical direction indicates the distance Im()/mink distance 11i) between the two slams, and the horizontal indicates the timing shift amount Δt. As is clear from the figure, the distance on both sides of the timing scattering point is large, so that even if a discrepancy occurs in the setting signal, a resynchronization pulse can be obtained only at the correct position. However, since similar bumps may occur in the data, a gate signal as shown in FIG. 4(b) is used to eliminate this. The gating signal originates from the previous synchronization signal or resynchronization signal.

FIG. 5 shows an example of the configuration of the resynchronization pattern generation circuit, and FIG. 6 shows an example of the configuration of the detection circuit.

In FIG. 5, 30V'i is write data and 31F'i is the write synchronization button (data word). The write data is stored in a predetermined series of data groups at 32, and sent to the encoder 40 with a resynchronization button added thereto.

The encoder 40 encodes this according to the rules shown in FIG. The code word 51 is applied to the write driver 50 and becomes a recording signal 61 to the disk. At this time, prior to data recording, a series of predetermined format information such as a synchronization signal is provided from the format signal generator 53. The result is recorded in the form shown in Figure 2 (a).

FIG. 6 is a block diagram of the reproducing apparatus, in which a read signal 61 from the head is converted by a read signal processing circuit 60 into a signal 62 corresponding to the recorded code word.

This signal is applied to a timing recovery circuit 70 to obtain a read clock 700. The reproduced signal 62 is also given to synchronization signal detection circuits 71 and 72.

71 is a detection circuit for a synchronization signal indicating the beginning corresponding to 10 in FIG. 2, and 72 is a detection circuit for a resynchronization signal corresponding to 11 in FIG. The reproduced signal 62 and the two synchronized signals 1g@ are supplied to a decoder circuit 80 and converted into data words. Note that the read clock 700 is used for synchronization detection in the synchronization signal detection circuits 71 and 72, a decoder in the decoder circuit 80, and processing in the read data reconfiguration circuit 90. After converting into data words in the decoder circuit 80, the resynchronization button is removed in the read data reconfiguration circuit 90 to obtain data 900 corresponding to the write data 30 in FIG. FIG. 7 shows an example of a specific configuration of the resynchronization signal detection circuit 72. 721t! 7 foot register, 723 is a match detection circuit for matching the button, 7
24ri reference batan source, 72611 and gate, 72
9 is an OR gate, and 730 is a timing generation circuit.

Read signal 62 is sent to shift register 721 by clock 70
The match detection circuit li & 723 compares the reference button with the reference button taken in at 0 and taken into the shift register, and when they match, a match signal 7 is generated, and a resynchronization pulse 720 = i is generated through the gate 726 and 729. Output. Here, the synchronization signal 710 and the resynchronization signal are supplied to a timing generation circuit 730 through an OR gate 729 to generate a gate signal 727 (FIG. 4(b)). Even if an error or the like occurs in the read signal and a resynchronization signal cannot be detected at a normal time, the timing generation circuit 730 generates a gate signal with the timing created by the previous synchronization signal.

As explained above, according to the present invention, the same synchronization button can always be used regardless of the data button while using a variable word length encoding code, and its generation and detection are easy. be.

Therefore, the influence of timing deviation due to some cause qi!
It is possible to improve the reliability of data playback by minimizing the damage. Since there is no limit to the length of data in carrying out the present invention, any format structure can be adopted as needed.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of the variable word length encoding method, Figure 2 is a diagram showing an example of the recording format of data recorded on an optical disk, etc., and Figure 3 is a diagram showing an example of the data word bang and resynchronization button parts. Diagram showing classification of created code words, 4th
Figure 5 shows the ability of the resynchronization button according to the embodiment of the present invention.
The figure is a circuit configuration diagram showing an example of a method for generating synchronization. FIG. 6 is a circuit configuration diagram showing an example of a synchronization detection method. mouth 3 64

Claims (1)

[Claims] In devices such as optical discs that encode recorded data using a variable word length encoding method and record it on a recording medium Ki array, resynchronization is performed to indicate a break in the middle of the data in addition to synchronization information indicating the start of the recorded data. 1. A data recording and reproducing apparatus comprising a synchronization detecting means for inserting a button and detecting the resynchronization information as well as the synchronization information separately from data, and reproducing recorded data using the synchronization information from the detection means.