JPS58169341A - Recording and detecting device of synchronous information in optical disc - Google Patents

Abstract

PURPOSE:To assure the detection of a correct synchronizing signal even if there is an error in a recording medium, by detecting the coincidence of a readout signal and the reference signal of a synchronizing pattern or combined synchronizing patterns and performing logical processing with majority decision. CONSTITUTION:A signal 50 read out from a disc is inputted to a shift register 6 of the same number of steps as the number of symbols forming the combined synchronizing patterns controlled with a reproducing clock 51. The output of the register 6 is decoded with a decoder 7 according to whether said output coincides with the reference signal forming the pattern of the combined synchronizing patterns in a symbol unit. The decoded output is inputted to a majority decision logical circuit 8. When the majority decision wherein the number of coincidence is a prescribed number or above is held, the circuit 8 generates a detection signal which is outputted as a synchronizing detection signal through an AND gate 90 controlled by a gate signal 91 and the clock phase signal 93 corresponding to the specific phase generated by the synchronizing signal. Even if there is an error in the recording medium, the detection of the correct synchornizing signal is assured by such constitution which performs the logical processing with majority decision.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for recording and detecting synchronization information in an optical disk device, and more particularly to a device for achieving high reliability.

FIG. 1 shows an example of a format for recording data on an optical disc. The data recording unit is hereinafter referred to as a sector. That is, FIG. 1 shows the sector format. The data is coded and modulated in a format suitable for the optical disc, and is recorded, including access to recorded data, floating rung, rounded data such as synchronization 1, as well as synchronization signals, addresses, and clocks.

Various! - records etc. according to a prescribed format.

In Figure 1, 1 is a mark indicating the start of the sector 9, 40 is address information, and 41 is data.
0.21 and 30.31 are recorded. The area for clocking 20.21 operates a 7-axis lock loop (PLL) during this time and generates the clock for reading 40 and 41. The synchronization signal 30.31 is that,
This indicates the starting point of recorded information 40.41.

A format similar to that shown in Figure 1 is used in conventional magnetic recording devices, etc.
However, the percentage characteristics of the recording medium are fundamentally different between magnetic recording and optical disks. Although the formats shown in Figure 1 are similar, the recorded contents themselves are completely different. In particular, optical disk media have a high recording density, so the error rate is 1 higher than that of magnetic media! There is a problem called II, -4. Therefore, in the above-mentioned format, the specific recording methods and detection methods such as 20.21 and 30.31 must take into consideration the conditions unique to bare optical discs, unlike the conventional methods.

Several methods can be considered as encoding and modulation methods for optical discs, but the data word is converted into a code word at a ratio of 9 o'clock, that is, the recording on the disc is performed by forming bits in the @l'' part of the code word. If the bit frequency of the data is f, then the frequency of the code word is 2f.Therefore, in data reproduction, the 2nd from 9th codeword is
The clock frequency of f is recovered and reverse conversion or decoding from the code word to data is performed. Since the reproduced data has a clock frequency of f, it is necessary to convert 117 to f in the decoding process.

When the circuit rotates, ff1cFi2 output phases are generated, and for correct decoding, the correct phase must be selected from among these two. That is, it is necessary for decoding and it is necessary to determine the Cooke phase. A specific synchronization button is also recorded for the rounded synchronization signal that knows the starting point of the recorded data, but the detection is repeated one after another. It is used as a synchronous signal. Therefore, if there is a KIND during the synchronization slam, for example 1
Even if there is a bit error, normal synchronization detection cannot be performed. However, the error rate of optical disk media is high, and the system must be constructed with a tolerance of 10-1 to 10411 degrees of bit error. Now, if the bit t14b rate is t9 and the length of the synchronization pattern is B bits, then 1 during the synchronization button.
The probability that more than one error is included is approximately Bp. This value is unacceptable in relation to the error rate of data recorded on the disc. For example, the data error rate is 10-1.
When trying to achieve quality such as 0 to 1o-11, it is possible to reduce errors in the round shape in proportion to fppa by adding an error p correction code to the data part K)-. However, if the synchronization signal is proportional to p and has a good value, the processing in the data section becomes completely meaningless. This is because the data portion O1 & salt is established on the premise that the clock signal and synchronization signal are accurate. Since the error rate of the optical disc is as high as described above, there is a problem in that the conventional method of synchronization detection cannot reproduce data with high accuracy.

SUMMARY OF THE INVENTION An object of the present invention is to provide an optical disk device that can guarantee correct synchronization signal detection within a predetermined range even if there is an error in the recording medium.

The synchronization pattern in the present invention has a peak in its autocorrelation function, and has a small number of autocorrelation outside of the correct synchronization timing, and majority logic, i.e. n
A synchronization signal is output when m or more (m<n) of the synchronization detection outputs are detected.

The present invention will be explained in detail by way of Examples below. There are several possible data recording modulation methods, but the synchronization pattern is also the same as the data modulation rules. This condition requires the use of the same reproduction circuit and detection circuit as for the data. FIG. 2 shows the encoding rules in an embodiment of the invention. The data is recorded on the disc by forming bits in the 11" part of the code word. Therefore, the read signal is only the 11# part of the code word, and these clocks and data are reproduced. The synchronization signal button is also This shall not conflict with the rules in Figure 2.

FIG. 3U) is an example of a synchronous pattern/at the beginning @. Friend symbols A, B, and C are each person = (100G)
, B-(010G), C=(0010). The length of the synchronous button in this embodiment is 3 bytes, but other lengths are also possible.

For detection, the 3-byte pattern shown in FIG. 3(B) is used as a reference button, and the level of the start-up button and the reference button are compared to check the extent of the stroke. Figure 4 is A.

B and C are each increased by one symbol, and the degree of coincidence shown in each successive pattern and reference button symbol by symbol is investigated with respect to timing deviation. That is, in Fig. 4 (0), the time of t-O is expanded to show one synchronization timing, t (Q is expanded, and ``>O'' is the time before, and ``>O'' is after.) It is in bit units.If l=Q, 3 byte bits (i.e. 1211
symbols) all match, but the number of matches between t and O is small.

Therefore, for example, if the number of symbols is 8 or more, if the synchronization signal 8YNC pulse (shown in Figure 4 (b)) is output, the synchronization signal will be detected correctly even if an error occurs in any four symbols in the synchronization meta. can do.

Please be careful not to make mistakes due to similar bumps in the data etc.
As shown in FIG. 4, the synchronization detection gate signal chain f→ is used. This gate signal is generated from the detection signal of the sector mark 1 in FIG. 1, but it is not particularly difficult and will be omitted here. An embodiment of the swAa synchronization signal detection circuit is shown. A signal corresponding to code 11" in Fig. 2 of Signal Co., Ltd., which is successively outputted from the disk, is taken into the shift register 6 by this readout signal sO Hiro reproduction clock 151. It has a number of stages that can handle information in terms of code word rate.The output 60 of the shift register 6 is decoded by the decoder 7 in units of symbols.The decoding is performed by comparing it with the reference button in Figure 118 (b).
Specifically, each symbol is as shown in Figure 6! It can be realized under configuration. Output of decoder 7? (l number of symbols (121
1) leads to the majority logic diagram 48. Here, it is detected that m or more out of n (man) is established, that is, an output 89t- is output for the input m m+1 of the combination of ('')+('')+...+(n), ? - output is gate signal 91
(Fig. 4 r1) is gated by an AND gate 90 and output as a synchronization signal 92 (Fig. 4 (b) in 11).
□Data recovery! It is used as a time reference point in

The signal 93 that enters the gate 90 of the aS diagram at Jin, Jin, is routed by the phase information of Kurotsuta. That is, since the synchronization signal is generated at a specific clock phase, the purpose is to prevent output from occurring at other phases and further reduce the probability of occurrence of 1lu). That is, in the part marked with "cloudy-○" in Figure 1, the shiftpol synchronization! timing (4--tobit) is detected along with the clock regeneration.By using this as the clock phase information @93, the error occurrence probability can be determined. Figure 7 shows the synchronization
For two to nine cases, such as synchronization without missing a large medium (even if the entire button is erased, the correct synchronization signal can be detected with either one of the two synchronization buttons) The marks in Figure 1 show an example of the format, and the marks in Figure 1 (B) and (C)
is the synchronization detection gate signal. FIG. 8 shows a detection circuit in this case, and it is only necessary to add a bar and game) 902, a predetermined time delay circuit 94, and an OR game) 95t to FIG. 6, and newly provide 912 as a gate signal.

The detection reliability of the synchronization signal according to the present invention will be explained below. In FIG. 4, the probability that the number of matching symbols is reduced by m when pt=O due to the occurrence of error p is considered to be approximately P,(m). P and 轡 are the probability of occurrence of m-symbol length parse) l1. On the other hand, the probability of increasing the number of matching symbols at the point t to O is approximately P, (P-). However, in Pt, there is a probability that one symbol will be mistaken for another symbol. Majority decision for synchronization signal detection! 1 circuit threshold is M than the number of matches at t=Q
In the case where the number of moths is smaller than the number of large matches between t and O and the K individual V% value is the same (in the example of FIG. 4, if the above threshold value is set to 8, then M==4), then a,'= The probability that a synchronization pulse does not occur at O is -P, (5)t, and the probability that a false synchronization pulse occurs at t+O is -P J4)Ps'. If ti is duplicated as shown in Figure 8, the probability of error at t=0 is ~(P, (
M+1))”=(P, (5))” Or worse -P
, (2(M+1))-P, (1G) or less.

The false 9 rate is greatly improved compared to -fl in the conventional method. The above evaluation of the WA rate is based on nine evaluations in which the disc is treated as a burst channel. If the error is random, the trout is sufficiently small compared to the above evaluation results.

As explained above, according to the present invention, the W of the disk medium is
A] Enable synchronization signal detection with sufficiently high reliability by allowing a certain degree of occurrence rate. Conventional method synchronization signal @]
For the probability of occurrence (4B 9 ), p = 10”'~1G-
'No matter how high-performance and complex WA9 revisions are applied to the data department, no matter how high-performance and complex WA9 revisions are applied to Cheng Taka's media quality level, high reliability a
Direct data recording and reproduction cannot be realized. Therefore, the present invention makes it possible to realize data recording and reproduction at a practical reliability level for the first time, and its effects are very large.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of the recording #l format on an optical disc, Figure 2 is a diagram showing an example of data encoding, and Figure 3 is a diagram showing an example of data encoding.
FIG. 4 is a diagram showing the synchronization pattern in the embodiment of the present invention, and FIG. 4 is a diagram showing the characteristics when detecting the synchronization pulse in the embodiment of the present invention.
Figure 6 shows an example of the decoder circuit shown in Figure 6. Figure 7 shows an example of recording a synchronization pattern different from that shown in Figure 1. , Figure 8 is rattan ¥3 1 Figure lAZ Figure ¥J 3rd WOtko ILI Day 4 (A) JIJ5 Figure ¥J 3 Figure 5ρ vi 6 Figure ■ 7 Figure

Claims (1)

[Claims] In an apparatus for recording and reproducing data on an optical disk, a sync signal consisting of a plurality of bits is used as a synchronization signal indicating the base point of recording data. The above-mentioned button φ is a combination of patterns, and the nine patterns are used as a reference button, means for detecting coincidence of the readout signal and the reference button, and a plurality of outputs from the nuclear detection means. Detection of recording of synchronization information on an optical disk, characterized in that it is equipped with a majority logic circuit for detecting occurrence of a match output equal to or greater than a predetermined prime number, and generates a synchronization pulse based on the output of the majority logic circuit. Device.