JPS58159356A - Package for semiconductor element - Google Patents

Abstract

PURPOSE:To enable to obtain the titled package, having excellent heat radiating property and an electrostatic capacity in the neighborhood of that of the package heretofore in use, which can be used as the package for elements such as a high-speed logical LSI and the like by a method wherein a wiring is provided between the internal connecting terminal and the external lead on the insulative layer of a carborundum substrate having an insulative layer on the surface. CONSTITUTION:An insulative layer 10 is provided at least on one face of an SiC substrate 9, and an internal electrode 5 and a wiring 6, between the internal electrode of the external lead 7 and the external lead, are provided on the insulative layer. An SiO2 film can be most uniformly adhered to the insulating layer constructed as above by performing an oxidizing method on SiC in a high temperature O2 atmosphere or H2O atmosphere. A lead pin 7 is constructed in such a manner that it is provided on the metal wiring layer 6 which is provided on the insulative layer 10 located on the surface of the substrate, and the construction wherein the lead pin is buried in the substrate or penetrating the substrate is not used. In the construction wherein the external lead is attached to the side face of the substrate, an electrostatic capacity larger than that of the construction indicated in the diagram exists between the external lead 7 and the wiring 6, and therefore, the construction having the internal electrode 5, the wiring 6 and the external lead 7 on the same plane surface is advantageous over the construction having the external lead provided on the side face of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a package for a semiconductor device, and more particularly to the structure of a package for a semiconductor device using aspect ratio silicon (8iC) as a substrate.

Conventional packages of this kind are made of Alina ceramic and are made of multiple layers of cells 1, 2.3, as shown in Figures 111 and 512, and are made of Alina ceramic. The connection between the internal connection terminal 5 and the external lead 7 around the ceramic layer 4 was made through a through hole 8 passing through the metallization 6 or the ceramic layer 3 provided between the ceramic layers 2.3.

However, in recent years, materials with high thermal conductivity have been required for substrates in order to mount large power consuming elements such as LSIs.

The present invention was made to meet these demands, and is intended to apply silicon carbide (8iC), which has a thermal conductivity 5 times l1WL compared to A, to a package substrate. ζLOGA8IC has an electrical resistivity of 10iQI at room temperature compared to the conventional substrate material Arunna.
Because it is as low as 11 degrees (alumina is more than 1 o 14 Ω), it is the first
It is not possible to use a structure in which the wiring 416 between the external lead 7 and the internal conductor &5 is embedded in the substrate material 112*3 as in the case of the nine package using the alumina substrate shown in FIGS.

That is, the present invention uses silicon carbide (
8iC) Internal connection terminals and external lead pipes are provided on the insulator layer of the substrate around the semiconductor element mounting portion and the semiconductor element placement, and wiring between the internal connection terminals and the external leads is provided on the insulator layer. This is a package for a semiconductor device characterized by the following. In addition, this semiconductor element mounting part, internal connection terminals,
External leads and wiring can be on the same plane. Further, at least 4-fields of the insulating layer may be silicon oxide (8 iom) obtained by 5tcl oxidation.

As shown in FIG. 5 and FIG. 6, the 8iC substrate according to the present invention has an insulating layer 10f provided on at least one surface of the 8iC substrate 9, and internal electrodes 5 on the outer insulating layer.
, the inner electrode of the external lead 7 and the outer electrode.For the ninth insulator layer to realize such a structure, there are two methods: forming 8i0sjl on an 8iC substrate by vapor deposition, or printing and firing powdered glass. Although it is possible to form the shrimp using a method of oxidizing it in a high-temperature Os atmosphere or H2O atmosphere, the shrimp can be uniformly formed with 840% oxidation. It is possible to apply a membrane. Therefore, when mounting devices used at low voltage, this oxidized at
Only nine settings are required. However, 5jO obtained by this method
Since the a-film is thin, printing high voltage may cause dielectric breakdown, so in cases like this, powdered glass is printed on top of the 840m and fired to form a multi-layered thick insulator. Let's form a layer.

By applying an insulating layer to the SiC surface in this way, 8
The problem regarding the insulation resistance of the iC substrate is solved.

Next, compared to alumina, 8iC is used as a material for package substrates.
This is a problem with the capacitance between the wires of the physical hackage, which has inferior properties.

The dielectric constant of alumina is 10 at room temperature and JMHg, but 8
In 10, 30-501! It has become a degree. Therefore, even if the same wiring pattern is used, a SiC package will have 3 to 5 times more capacitance between the wires than a solid alumina package. Including this meaning, the structure in which the wiring 6 is placed in the board materials 1, 2, and 3 as shown in the JIEI diagram and Fig. 2 is disadvantageous for the 8iC package. Therefore, when attaching leads to the board, Also in Figure 3.

It is also undesirable to have a structure in which the lead pins penetrate the substrate as shown in FIG. 4. In the conventional alumina package, the substrate 9 is connected to the lead pin
Even if the 8iC
Figure 9 JIK3.

In the package having the structure shown in FIG. 184, the electrostatic capacitance between the lead bins becomes negligible. Therefore, in the 8iC package according to the present invention, as shown in FIG.
The lead pin has a structure in which the lead pin 7 is provided on the metal wiring layer 6 provided on the insulator layer IO on the surface of the board, and the lead pin is not embedded in the board or penetrated through the board. Comparing the two structures shown in Fig. 5 and Fig. 6 in consideration of capacitance, in the structure where the external lead is attached to the side of the board as shown in the JIS drawing, the structure shown in Fig. 6 is between the external lead 7 and the wiring 6. Since there is a capacitance p larger than the structure, the internal capacitance &
5. A structure having wiring 6 and external leads 7 is more advantageous. The present invention is manufactured as follows.

After forming the substrate 9 by a powder pressing method and firing, 840z 1O is formed on one surface of the substrate in an HzO atmosphere. Then, print gold-paste on the 5ill and put N-paste on it.
A wiring pattern 6 was provided by applying I plating and Au plating. By soldering the external leads to one end of the nine substrates produced in this way with high melting point solder, a PSTC package is produced.

The 810 package with this structure has excellent heat dissipation characteristics and has a capacitance similar to that used for conventional semiconductor devices.
12), and can be used as a package for elements such as high-speed logic LSI.

[Brief explanation of the drawing]

Figures 1 and J1!2 are cross-sectional views of a package using a conventional aluminum board, Figures jI3 and #I4 are round cross-sectional views showing enlarged external lead connections of the package, and Figures 5 and ! s6
The figure is a cross-sectional view of a package according to an embodiment of the invention. In addition, in the figure, 1... Alumina ceramic first layer, 2... Alumina ceramic second layer, 3 - Arunna Ceramic JI 3 layer, 4... Element mounting part, 5 ...Internal electrode, 6...Wiring, 7.
...External lead. 8...Through hole, 9...8iC1
siK, so... Insulator layer. Agent Patent Attorney fLiI Figure 1, Figure 2, Figure 3, Figure 4, S /θ Figure S, Figure 6

Claims (3)

[Claims] (1) On the insulator layer of a silicon oxide substrate having an insulator layer on the surface, internal connection terminals and external leads are provided around the semiconductor element mounting part and the scissor semiconductor element mounting area, and on the insulator layer. A package for a semiconductor element, characterized in that a wiring 1laf is provided between an internal connection terminal and an external lead. (2) The package for a semiconductor device according to claim (1), wherein the semiconductor device mounting portion, internal connection terminals, external leads, and wiring are on the same plane. (3) The semiconductor according to claim 1, item 4 or item 2, characterized in that at least one of the insulating layers is silicon oxide obtained by oxidizing a silicon carbide tube. Package for element.