JPS58158955A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS58158955A
JPS58158955A JP57040141A JP4014182A JPS58158955A JP S58158955 A JPS58158955 A JP S58158955A JP 57040141 A JP57040141 A JP 57040141A JP 4014182 A JP4014182 A JP 4014182A JP S58158955 A JPS58158955 A JP S58158955A
Authority
JP
Japan
Prior art keywords
package
holes
lead
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57040141A
Other languages
Japanese (ja)
Inventor
Yoshimasa Kudo
工藤　好正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57040141A priority Critical patent/JPS58158955A/en
Publication of JPS58158955A publication Critical patent/JPS58158955A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to readily and accurately mount in high density by forming holes at suitable positions of a lead terminal projected from a package. CONSTITUTION:When round holes 3a are opened on a lead 2a projected from a package 1a and the package is clamped to a substrate with screws through insulators and heat sink by utilizing the holes 3a, it can be accurately positioned. Or, holes 3b are opened at the prescribed leads, the mounting is rationalized to match the holes of the substrate, or the end of the lead 2c' of the package 1c' can be inserted into the hole 3c of the lead 2c of the package 1c, two ICs are connected directly, conducting resistance can be reduced, and the mounting density can be improved.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係り、特にリード端子に孔を設け
た半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit device in which lead terminals are provided with holes.

〔発明の技術的背景〕[Technical background of the invention]

一般にパッケージングされた半導体集積回路素子（以下
ＩＣと称す）は、その外形からデュアルインライン（Ｄ
ＩＰ）型とフラットパック（ＦＰ）型がある。ＤＩＰ型
はそのリード端子が２列（８本、１０本、・・・）に並
んでおシ、外形が大きくリード端子の強度も大きいので
超小型化をそれ＃１ど重視しない時にはプリント板への
実装に適し、リード間隔もプリント板の穴ピッチに合わ
せである。そして、例えばマイクロコンピュータシステ
ムにおいてＣＰＵにメモリを抱き合わせる場合等はピギ
ーバック用のソケットが一般に用いられている。また、
ＦＰ型はその本体が薄型（フラット）でＩＪ−ド端子が
横方向に突出しているもので、超小型化できる一方取や
扱いや実装の点で小さすぎる場合もあり、小型化の利点
をあｔシ生かさないＩＣでは外形寸法を少し大きくして
いる。そして、ＦＰ型のＩＣを基板に実装する場合はガ
イド等を用いて位置を決めていた。さらに、ＤＩＰ、Ｆ
Ｐ型ＩＣハ共ニそのパッケージおよびリード端子が放熱
の役割をしているのが一般的である。Generally, packaged semiconductor integrated circuit elements (hereinafter referred to as ICs) are dual-in-line (Dual-in-line) devices due to their external shape.
There are two types: IP) type and flat pack (FP) type. The DIP type has lead terminals lined up in two rows (8, 10, etc.), and has a large exterior and strong lead terminals, so if miniaturization is not a priority, it can be used on a printed board. It is suitable for mounting, and the lead spacing matches the hole pitch of the printed circuit board. For example, a piggyback socket is generally used when a memory is attached to a CPU in a microcomputer system. Also,
The FP type has a thin (flat) main body with the IJ-do terminal protruding laterally, and while it can be made ultra-compact, it may also be too small in terms of handling and mounting, so it does not have the advantage of miniaturization. The external dimensions of ICs that do not take full advantage of this feature are slightly larger. When mounting an FP type IC on a board, a guide or the like is used to determine the position. Furthermore, DIP, F
Generally, the package and lead terminals of a P-type IC play the role of heat radiation.

〔背景技術の問題点〕[Problems with background technology]

ＩＣのパッケージはプリント板や他の部品との絶縁体（
プラスチック、セラミック岬）になっており、このパッ
ケージやリード端子が放熱の役割をしている。しかし、
特にＦＰ型のＩＣは小型化のため放熱が悪く特別にヒー
トシンクが必要なことがあるが、その形状が小型という
ことからヒートシンクの取り付けが難しくプリント基板
へ取シ付ける際の位置決めが離しいという難点がある。The IC package is an insulator (
The package and lead terminals play a role in heat dissipation. but,
In particular, FP type ICs have poor heat dissipation due to their miniaturization and may require a special heat sink, but because of their small size, it is difficult to attach a heat sink and the positioning when attaching to a printed circuit board is difficult. There is.

また、比較的大きい容量のＩＣでも特別にヒートシンク
が必要なこともあり、この場合も位置決めが難しいとい
う難点がある。さらにまた、マイクロコンピュータシス
テムにおける２個のＩＣ間を接続−ｔ−る場合ピギーバ
ック用のソケットが必要で、そのソケットによる導通抵
抗が大きくなるという難点があった。Further, even an IC with a relatively large capacity may require a special heat sink, and in this case as well, there is a problem in that positioning is difficult. Furthermore, when connecting two ICs in a microcomputer system, a piggyback socket is required, and there is a problem in that the conduction resistance due to the socket becomes large.

〔発明の目的〕[Purpose of the invention]

本発明は上記従来の難点に鑑みなされたもので、ＩＣの
リード端子に、その適宜箇所に孔を設けることによシ、
ヒートシンクや絶縁物を挟着させて基板との゛係合ネジ
等で装着することによりガイドを用いずに正確な取付は
位置を決めることができ、さらに２個のＩＣ間または他
の電子部品のリード端子の接続における導通抵抗を低下
せしめることができる半導体集積回路装置を提供するも
のである。The present invention was made in view of the above-mentioned conventional difficulties, and it is possible to achieve this by providing holes at appropriate locations in the lead terminals of the IC.
By sandwiching a heat sink or insulator and attaching it to the board using screws, etc., accurate mounting can be determined without using a guide, and it can also be mounted between two ICs or between other electronic components. The present invention provides a semiconductor integrated circuit device that can reduce conduction resistance in connection of lead terminals.

〔発明の概要〕[Summary of the invention]

本発明はリード端子を有するパッケージングされ九半導
体集積回路素子において、パッケージから突出されたリ
ード端子の適宜箇所に孔を設けて他の電子部品の端子等
を装着できるようにした半導体集積回路装置である。The present invention relates to a packaged semiconductor integrated circuit device having lead terminals, and a semiconductor integrated circuit device in which holes are provided at appropriate locations on the lead terminals protruding from the package so that terminals of other electronic components can be attached thereto. be.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.

ＤＩＰ型ＩＣでは、第１図に示すように、プラスチック
およびセラミック等でパッケージングされたパッケージ
１ａより２列に突出されたリード端子２ａ上に丸孔３ａ
を１個あるいは複数個設けたもので、比較的大きい容量
のＩＣの場合との丸孔を用いてパッケージ１ａで絶縁物
やヒートシンク（図示せず）等を挟装して基板に保合ネ
ジ等で装着すると共に、基板の孔と挟装された物の正確
な位置決めをすることができる。また、ＦＰ型ＩＣでは
第２図に示すように、その外形上実装にはガイド等が必
要であったのがパッケージ１ｂより突出されたリード端
子２ｂにおける所定リード端子の適宜箇所に設けた孔３
ｂを基板の孔に合わせることによって簡単にそして正・
確に位童出しができ実装が谷理的となシ、さらに孔３ｂ
を設けたリード端子２ｂを増して前述のＤＩＰ型ＩＣに
用いたようにヒートシンク等を挟装することによって従
来放熱に不利であったＦＰ型ＩＣの放熱効果を上けるこ
とができる。そして、第３図に示すように、マイクロコ
ンピュータの２個の集積回路素子（ＤＩＰ型）を接続す
る場合、パッケージ１Ｃから突出されたリード端子２Ｃ
の突出方向にパッケージ１　ｃ／から突出されたリード
端子２　ｃ　／の先端が嵌脱できる孔３Ｃを設けること
によって、パッケージ１ｃｏＩＣにパッケージ１０′の
ＩＣを嵌挿せしめて接続できるように孔３Ｃを設はソケ
ット孔とすることによｆｉ、ＩＣ間の接続は直接付けか
り能とｅＤピギーバック用のソケットが不用となるため
導通抵抗を低下せしめることができ、゛またこうするこ
とによって部品の高密度実装が可能となる。In a DIP type IC, as shown in FIG. 1, round holes 3a are formed on lead terminals 2a that protrude in two rows from a package 1a made of plastic, ceramic, etc.
Insulators, heat sinks (not shown), etc. are sandwiched in the package 1a using round holes similar to those for relatively large capacity ICs, and retaining screws, etc. are attached to the board. At the same time, it is possible to accurately position the sandwiched object with the hole in the board. Furthermore, as shown in FIG. 2, in the case of FP type ICs, guides and the like are required for mounting due to the external shape.
By aligning b with the hole in the board, you can easily and positively
It is possible to accurately put out the Ido, and the implementation is logical, and also hole 3b
By increasing the number of lead terminals 2b provided with and sandwiching a heat sink or the like as used in the above-mentioned DIP type IC, it is possible to improve the heat dissipation effect of the FP type IC, which has conventionally been disadvantageous in terms of heat dissipation. As shown in FIG. 3, when connecting two integrated circuit elements (DIP type) of a microcomputer, lead terminals 2C protruding from the package 1C
By providing a hole 3C in the protruding direction of the package 1c/ into which the tip of the lead terminal 2c/ protruding from the package 1c/ can be inserted and removed, the hole 3C is provided so that the IC of the package 10' can be inserted and connected to the package 1coIC. By using a socket hole, the connection between ICs can be made directly and the conduction resistance can be lowered since a socket for eD piggyback is not required. Implementation becomes possible.

以上実施例では丸孔を示したが、大きさ、形状は必要に
応じて任意に決めることができ、また孔の数または位置
等も任意に定めることができる。Although round holes are shown in the above embodiments, the size and shape can be arbitrarily determined as required, and the number and position of the holes can also be determined arbitrarily.

〔発明の効果〕〔Effect of the invention〕

上記実施例からも明らかなように、本発明はパツケニジ
から突出されたリード端子における任意のリード端子の
適宜箇所に、必要に応じた形状の孔を任意数設けること
により、基板との保合ネジ等で装着の際正確な位置決め
ができ、かつヒートシンクや絶縁物等を挟着せしめるこ
とができ、さらにＩＣ間および他の電子部品のリード端
子接続用のソケット孔として用いることによ、９　ＩＣ
等の電子部品の実装が容易でしかも高密度実装が可能で
ある。As is clear from the above embodiments, the present invention provides an arbitrary number of holes of a shape according to necessity at an appropriate location of an arbitrary lead terminal in the lead terminal protruding from the package. It is possible to accurately position the 9 ICs when mounting them, and also to sandwich heat sinks, insulators, etc., and also to use them as socket holes for connecting lead terminals between ICs and other electronic components.
It is easy to mount electronic components such as, and high-density mounting is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はＤＩＰ型ＩＣのリード端子に孔を設けた斜視図
、第２図はＦＰＷＩＩＩＣのリード端子に孔を設けた斜
視図、第３図は・ＩＣ間接続を本発明によって行なった
ときの斜視図である。 １　ａｓ　１　ｂ）　１　ｃｓ、　ｌ　ｃ’・・・パッ
ケージ７ａ、　２ｂ、　２ｃ、　２ｃ／、・・リード端
子３ａ、　３ｂ、　３ｃ　　−−−・一孔（７３１７）
代理人　弁理士　則　近　憲　佑（ほか１名）Fig. 1 is a perspective view of a lead terminal of a DIP type IC with a hole provided, Fig. 2 is a perspective view of a lead terminal of an FPWIIIC with a hole provided, and Fig. 3 is a perspective view of a DIP type IC with a hole provided in the lead terminal. FIG. 1 as 1 b) 1 cs, lc'...Package 7a, 2b, 2c, 2c/...Lead terminal 3a, 3b, 3c----One hole (7317)
Agent: Patent attorney Kensuke Chika (and 1 other person)

Claims (1)

【特許請求の範囲】[Claims] パッケージからリード端子を突出されると共に該リード
端子の適宜箇所に１個又は２個以上の孔−を穿設したこ
とを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device, characterized in that lead terminals are protruded from a package, and one or more holes are bored at appropriate locations in the lead terminals.
JP57040141A 1982-03-16 1982-03-16 Semiconductor integrated circuit device Pending JPS58158955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57040141A JPS58158955A (en) 1982-03-16 1982-03-16 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57040141A JPS58158955A (en) 1982-03-16 1982-03-16 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS58158955A true JPS58158955A (en) 1983-09-21

Family

ID=12572494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57040141A Pending JPS58158955A (en) 1982-03-16 1982-03-16 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58158955A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251U (en) * 1984-06-07 1986-01-06 株式会社東芝 electronic components
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
EP3133643A3 (en) * 2015-01-12 2017-03-29 Micronas GmbH Integrated circuit housing

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251U (en) * 1984-06-07 1986-01-06 株式会社東芝 electronic components
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
EP3133643A3 (en) * 2015-01-12 2017-03-29 Micronas GmbH Integrated circuit housing
US9893005B2 (en) 2015-01-12 2018-02-13 Tdk-Micronas Gmbh IC package
US10026684B2 (en) 2015-01-12 2018-07-17 Tdk-Micronas Gmbh IC package

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