JPS58155762A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form timing pulse wiring in a single layer by utilizing space by diffusion resistors for limiting currents, and to simplify the manufacture of a shift register by continuously forming the diffusion resistors into each emitter region constituting a unijunction transistor. CONSTITUTION:The P type resistance layers 21A-24A for limiting currents are formed continuously to the emitters 21-24 of the unijunction transistors 1-4, and each connected to the wiring 101-103 for timing pulse wires through the insulating film windows 5a-5d of end sections by utilizing sections among the windows 5a-5d and the insulating film windows 5e-5h of collector layers 41- 44. A base 11 is disposed on both sides in a pectinate shape. When timing pulses are applied to the wiring 103 and the unijunction element 3 by the N layer 23, a P layer 33 and the N layer 43 is at ON, the resistor 23A controls emitter currents. When pulse voltage applied to the wiring 101 is selected properly, holes are injected only to the emitter 24, the unijunction element 4 is at ON, and transfer operation is allowed. An adverse effect by pulse voltage in case of transfer is prevented by the pectinate structure of the base 11. According to the constitution, processes are simplified, and yield is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a plasma-coupled semiconductor device in which single-junction transistors are successively arranged in close proximity to each other as plasma-coupled devices (hereinafter referred to as PCDs), particularly on a semiconductor substrate. The present invention relates to a shift register configured to perform one transfer operation using coupling between single junction transistors by solid plasma.

An overview of a conventional three-phase clock drive shift register of this type is shown in FIG. 1, and FIG. 1 shows a partial plan view of the shift register.
A case in which four single junction transistors are configured is shown. In the figure, reference numeral 10 denotes a semiconductor substrate made of silicon having Nm as a conductive layer, and on this semiconductor substrate 10, four single junction transistors 1 to 4 are arranged in a line in close proximity to each other. These single junction transistors 1~
4 is from a common base region 11 formed by impurity diffusion on the Nll semiconductor substrate 10 and consisting of a high concentration diffusion region of fcN wrinkles, and a pm diffusion region formed separately between this base region 11. emitter regions 21-2
4 and Pjl diffusion regions 31-3 as hook regions
N-type height 11 formed overlappingly in 4 by impurity diffusion
11IL diffusion region and collector regions 41 to 44 (7
It is composed of two rectors.

And the hooks for each single junction transistors 1 to 4! 1:I
Plasma sensors s1 to s4 are arranged corresponding to the rectors, and these seven plasma sensors tS1 to 54 are N
It consists of a high, concentrated, diffused region of ll. Further, @1 to 64 are connected to each of the emitter regions 21 to 24, respectively, and are first layer wirings as a four-pulse line, and @71 to 14 are connected to each of the plasma lines fit-54, and are connected to 111 as a nine output line. Layer wiring and wiring are each of the collector regions 41 to 4.
4 are commonly connected, and -1 to Ss are connected in correspondence with the first layer wirings @1 to 64, respectively, and are 0@2 layer wirings as nine clock pulse lines.

Note that S-51 is a hole in the insulating film between each diffusion part of each single-junction transistor 1-4 and wiring, @a-lid Fi
This is the hole-drilled portion of the insulating film (interlayer insulating film) between the i1 layer wirings 61 to -4 and the second layer arrangements 1 to -3. Also, base area 1
One side of the transistor 1 is formed into a comb shape, and has a structure in which each part separates the collectors of the seven collectors J1 between the single junction transistors 1 to 4 and the plasma sensors s1 to s4, respectively.

Next, the transfer operation of the above configuration will be explained. Here, the first layer m8 is grounded, and a positive base voltage is applied to the base region 11. Then, state clock pulses φ1 to φS are applied to the second layer weights m1ll to ml13, respectively, from a three-phase lock generator (not shown). Now, suppose s2 layer arrangement 8
A clock voltage is applied to 9, emitter region 23. Board 1
0. It is assumed that the single junction transistor 3 having a PNPN II structure (also referred to as a silicon risk structure) consisting of a diffusion region 33 and a collector region 43 is turned on. At this time,
Said PIi expansion area 33. Kl directly below the collector area 43
A ji1-body plasma is generated, and its potential Fi drops to near the ground potential. Next, when a clock voltage is applied to the second layer wiring 111, the emitter region 2 of the single-junction transistor 4
4, the P-type diffusion region s3. Since it is closer to the collector region 43, the emitter region 24 is more influenced by the solid plasma, and the emitter region 24 feels a lower voltage than the emitter region 21.

By this, if the voltage of the second layer arrangement 1~ is appropriately selected,
The on-state mt of the single-junction transistor 3 can be transferred to the adjacent single-junction transistor 4.

However, in the conventional structure described above, since the clock pulse line uses a two-layer wiring of the first layer wiring and the second layer wiring, the manufacturing process requires an interlayer insulating film and a #I two-layer wiring process. , and is concerned about the complication of the knee.

119. When using a single-junction transistor as a PCD, a current-limiting resistor (Entsuta resistor) is installed on the clock pulse line to control the excessive current that flows when it is turned on.
It is necessary to connect the resistors in series, but conventionally, this resistor is formed separately in other parts of the chip.

The present invention has been made based on this point, and by forming a diffused resistor for current limiting continuously in each emitter region constituting a single junction transistor, the space created by this diffused resistor is utilized. The object of the present invention is to provide a shift register which is possible with an arrangement for clock pulses.

Embodiments of the present invention will be described below with reference to the drawings.

#I2 is a schematic partial plan view of a shift register showing an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts. The true point with FIG. 1 is that each entrant region 21 to
Diffused resistors 21A to 24A for current limiting, which are made of Pijl diffusion regions, are provided in succession to 24 in the same diffusion. Then, the four insulating film holes sSa to 5d at the ends of these diffused resistors 21A to 24A and the collector region holes 41 to
Using the space (interval) with the insulating film hole portions se to 5h of 44, the ends of each of the diffused resistors 21A to 24A are
This is because they are connected to the M1 layer stacks 101 to 103 for the black pulse line through the perforated portions 5a to 5d, respectively. In this case, the diffused resistors 21A, 24A
Fi first wiring 101, diffused resistor 22A to first layer wiring 102, diffused resistor 23A to first layer weight m1gl5K
Each of them is followed by II. Note that the base region 11 has a horizontal lid structure on both sides.

Next, the operation of the above embodiment will be explained. Here, now, tI
A clock pulse is applied to the i1 layer wiring 103, and the emitter region 23. It is assumed that the single junction transistor 3 consisting of the substrate 10, the Pal diffusion region 3s, and the collector region 43 is on. At this time, the current flowing between the emitter and base regions is limited by the current limiting diffused resistor 23A connected continuously to the emitter region 23.

Next, a K clock pulse voltage is applied to the first layer wiring 101. Then, a voltage is simultaneously applied to each emitter region 21 and 24 through each diffused resistor 21A, 24A.

At this time, the P type diffusion region 33. The area where the effect of the solid plasma immediately below the collector area of the collector area 43 is felt most strongly is in the emitter region 24 rather than in the emitter region 21. Therefore, if the above p-pulse voltage is adjusted appropriately,
Holes are injected only into the nitrate region 24, and the nitrate region 24, the substrate 10. The single junction transistor 4 consisting of the P-type diffusion region 34 and the collector region 44 is on. With this, the transfer operation of the shift register can be performed in the same manner as before. However, if the clock pulse voltage is set high during this transfer, the entrant region 21 injects holes.
~24 part is easy to spread. In this situation, the injected holes may have an effect on the adjacent single junction transistor, but this effect can be suppressed by forming both sides of the base region 11 into the Kushimaro structure shown in FIG.

In this way, according to the above embodiment, the single junction transistor 1
By providing the Ik resistors 21A to 24A for current limiting continuously in the eight point regions 21 to 24 of 4, the clock pulse path can be formed by further wiring using the space created by the diffused resistors. This simplifies the manufacturing process of the shift register for single shift drive, and improves manufacturing efficiency.

In the above description, the collector structure of a single-junction transistor is a composite structure including a collector region of KNII within a P11 diffusion region, but the present invention is not limited to this, and the present invention is not limited to this. Various modifications can be made, such as a single structure having a collector region of the same type, or in which each region is reversed depending on the conductivity of the semiconductor substrate.

As described above, according to the present invention, the clock pulse line can be formed using only 17-bit wiring, which simplifies the manufacturing process for manufacturing a shift register and improves yield.

[Brief explanation of drawings]

FIG. 1 is a schematic partial plan view of a shift register showing a conventional example, and FIG. 2 is a schematic partial plan view of a shift register showing an embodiment of the present invention. 1 to 4...φ single junction transistor, 10@...semiconductor substrate, 11th race...base region, 21 to 24...
Niotsuta area, 21A-24m...kai diffusion/resistance, 31-34...-P! ! ! Diffusion area, 41-44-
... Φ collector area, 61~! 4.71~74,8...
...91 layer wiring, 101~IN-@--jl1 layer wiring,
51~5Je*mm Insulating film hole drilling part. Patent applicant Hitachi Electronics Co., Ltd. Agent Masaki Yamakawa (one person) Figure 1 Figure 2

Claims (1)

[Claims] Single junction transistors are arranged close to each other in sequence on a semiconductor substrate, and each of these single junction transistors has a base region made of the same conductivity as the armpit substrate formed on the semiconductor substrate, and a base region formed for the base region. In a semiconductor device comprising an entrant region of the opposite conductivity type to the semiconductor substrate and a collector region of the same conductivity type as the semiconductor substrate, a diffused resistor for current limiting is formed in continuity with each of the emitter regions. A semiconductor device characterized in that the ends of these diffused resistors are respectively connected to the wiring for the clock path helix, so that these wirings can be formed in one layer.