JPH01112762A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01112762A JPH01112762A JP26930487A JP26930487A JPH01112762A JP H01112762 A JPH01112762 A JP H01112762A JP 26930487 A JP26930487 A JP 26930487A JP 26930487 A JP26930487 A JP 26930487A JP H01112762 A JPH01112762 A JP H01112762A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input protection
- input
- film
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000013039 cover film Substances 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract 3
- 230000001052 transient effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
入力保護回路の熱により破壊しやすい抵抗部分の熱拡散
を改善することにより、人力保護回路の入力耐圧が強化
された半導体装置に関し、半導体集積回路の入力保護回
路において、本来の抵抗の断面積はそのままで表面面積
を大にし擬似的に熱容量を増加させた半導体装置を提供
することを目的とし、
半導体基板上の入力パッドに接続された入力保護抵抗と
、該入力保護抵抗を含む基板上に形成された絶縁膜と、
該絶縁膜をバターニングして形成された前記入力保護抵
抗に達する開口と、該開口を介して該入力保護抵抗にの
み接続され放熱板として作用する金属層とを具備するこ
とを特徴とする半導体装置の製造方法を含み構成する。[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor device in which the input withstand voltage of a human power protection circuit is strengthened by improving the thermal diffusion of a resistor portion that is easily destroyed by heat in the input protection circuit. In a circuit, the purpose is to provide a semiconductor device that increases the surface area and pseudo-increases the heat capacity while maintaining the original cross-sectional area of the resistor. an insulating film formed on a substrate including the input protection resistor;
A semiconductor comprising an opening formed by patterning the insulating film and reaching the input protection resistor, and a metal layer connected only to the input protection resistor through the opening and functioning as a heat sink. Contains and constitutes a method for manufacturing the device.
本発明は入力保護回路の熱により破壊しやすい抵抗部分
の熱拡散を改善することにより、入力保護回路の入力耐
圧が強化された半導体装置に関する。The present invention relates to a semiconductor device in which the input withstand voltage of an input protection circuit is strengthened by improving thermal diffusion of a resistive portion of the input protection circuit that is easily destroyed by heat.
半導体集積回路のための入力保護回路は第3図の回路図
に示され、図中、21は入力パッド、22は入力保護抵
抗、23はダイオードで、入力信号は図示の回路を経て
内部回路の初段バッファに入力されるもので、図におい
て、破線の左の部分は入力保護回路、右の部分は内部回
路である。ダイオード23とトランジスタ24とが同図
布の下方に示されるように組み合わされることもある。An input protection circuit for a semiconductor integrated circuit is shown in the circuit diagram of FIG. 3, in which 21 is an input pad, 22 is an input protection resistor, and 23 is a diode, and the input signal passes through the illustrated circuit to the internal circuit. This is input to the first stage buffer, and in the figure, the part to the left of the broken line is the input protection circuit, and the part to the right is the internal circuit. A diode 23 and a transistor 24 may be combined as shown at the bottom of the figure.
このような入力保護回路によって入力パッドに接続され
た入力ビンに突発的な過渡電圧、電流(静電気、電源の
0N10FF時)から内部回路が守られている。Such an input protection circuit protects the internal circuit from sudden transient voltages and currents (static electricity, when the power supply is 0N10FF) in the input bin connected to the input pad.
上記した従来の入力保護回路において、過渡電圧、電流
が印加された場合、一番はじめに入力保護抵抗22がヒ
ユーズの場合の如くに焼き切れた状態になり、破壊され
ることが経験された。このため、入力ビンの電圧、電流
耐圧は入力保護抵抗22の耐圧と同様になり、トランジ
スタやダイオードを組み合わせて構成した入力保護回路
本体が十分に活用されない問題がある。In the conventional input protection circuit described above, when a transient voltage or current is applied, it has been experienced that the input protection resistor 22 is first burnt out and destroyed like a fuse. Therefore, the voltage and current withstand voltage of the input bin becomes the same as the withstand voltage of the input protection resistor 22, and there is a problem that the main body of the input protection circuit configured by combining transistors and diodes is not fully utilized.
入力保護抵抗22が焼き切れる理由は、過渡電流が流れ
る時に発生する熱によるものである。これσ
該抵抗の幅、高さ、長さである。The reason why the input protection resistor 22 burns out is due to the heat generated when a transient current flows. This σ is the width, height, and length of the resistor.
抵抗の断面積(bXh)を大きくすれば、熱容量が大き
くなり耐圧が増加する。しかし、抵抗の絶対値が小さく
なり、鋭い人力パルスが人力されたとき入力保護抵抗で
十分なまらせることができなくなり、入力保護回路のト
ランジスタやダイオードが動作する前に内部回路に入力
され、内部回路が破壊される。Increasing the cross-sectional area (bXh) of the resistor increases the heat capacity and the breakdown voltage. However, the absolute value of the resistance becomes small, and when a sharp manual pulse is applied, the input protection resistor cannot sufficiently dampen it, and the input protection circuit is input to the internal circuit before the transistors and diodes operate, and the internal circuit is destroyed.
絶対値を大きくすればよいのだが 、入力保護回路部分
の面積が大きくなり、大規模集積回路の集積度を高める
について障害となる。以上に説明したように、入力保護
回路の耐圧を上げるには、抵抗の大きさ(Rの絶対値)
を変えず、熱容量かまたは抵抗の断面積を大にする必要
がある。Although it is possible to increase the absolute value, the area of the input protection circuit increases, which becomes an obstacle to increasing the degree of integration of large-scale integrated circuits. As explained above, in order to increase the withstand voltage of the input protection circuit, the size of the resistance (absolute value of R)
It is necessary to increase the heat capacity or the cross-sectional area of the resistance without changing the current.
そこで本発明は、半導体集積回路の入力保護回路におい
て、本来の抵抗の断面積はそのままで表面面積を大にし
擬似的に熱容量を増加させた半導体装置を提供すること
を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in an input protection circuit for a semiconductor integrated circuit, in which the surface area of the resistor is increased while keeping the original cross-sectional area of the resistor unchanged, thereby increasing the heat capacity in a pseudo manner.
上記問題点は、半導体基板上の入力パッドに接続された
入力保護抵抗と該入力保護抵抗を含む基板上に形成され
た絶縁膜と該絶縁膜をバターニングして形成された前記
入力保護抵抗に達する開口と、該開口を介して該入力保
護抵抗のみに接続され放熱板として作用する金属層とを
具備することを特徴とする半導体装置によって解決され
る。The above problem is caused by an input protection resistor connected to an input pad on a semiconductor substrate, an insulating film formed on the substrate including the input protection resistor, and the input protection resistor formed by patterning the insulating film. The present invention is solved by a semiconductor device characterized by comprising an opening that reaches the input protection resistor, and a metal layer that is connected only to the input protection resistor through the opening and acts as a heat sink.
前記した放熱板は、絶縁膜の穴の部分を埋め込んだ熱を
伝えやすい八2でポリシリコンの抵抗と接続しており、
その上方部分は拡がっているので、抵抗に発生した熱は
^2の放熱板によって3次元的に拡散され、そのことは
抵抗の熱容量が増大することになるので、入力保護抵抗
の熱による破壊が防止され、人力保護回路が正常に作動
し、突発的な過渡電圧、電流から内部回路が守られるの
である。The heat dissipation plate described above is connected to a polysilicon resistor with a hole in the insulating film filled with a hole that is easy to conduct heat.
Since the upper part of the resistor is expanding, the heat generated in the resistor is three-dimensionally diffused by the heat sink ^2, which increases the heat capacity of the resistor and prevents the input protection resistor from being destroyed by heat. The human power protection circuit operates normally, and the internal circuits are protected from sudden transient voltages and currents.
以下、本発明を図示の実施例により具体的に説明する。 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.
第1図(a)と(b)は本発明実施例の断面図と平面図
で、図中、11は半導体基板(例えばシリコン基板)、
12は絶縁膜(Sin、膜)、13はポリシリコンで形
成した抵抗、14は絶縁膜(例えばPSG膜)、15は
ANの放熱板、16は例えばPSGのカバー膜で、Al
パターンのうちの左の接続用パターン17aは入力パッ
ドへ、また右のAnの接続用パターン17bは内部回路
の前に配置される入力保護回路を構成するダイオードや
ダイオードとトランジスタとの組み合わせ部へそれぞれ
接続される。FIGS. 1(a) and 1(b) are a cross-sectional view and a plan view of an embodiment of the present invention, in which 11 is a semiconductor substrate (for example, a silicon substrate);
12 is an insulating film (Sin, film), 13 is a resistor formed of polysilicon, 14 is an insulating film (for example, PSG film), 15 is an AN heat sink, 16 is a cover film of, for example, PSG, and
Among the patterns, the left connection pattern 17a is connected to the input pad, and the right connection pattern 17b is connected to a diode or a combination of a diode and a transistor that constitutes an input protection circuit placed in front of the internal circuit. Connected.
過渡電圧、電流がパッドに印加されると、電圧、電流は
パッドから接続用パターン17aを経て抵抗13に、次
いで接続用パターン17bを経てダイオードやダイオー
ドとトランジスタとの組み合わせを経て内部回路に印加
される。この時抵抗13に発生する熱は、煙突状に形成
された放熱板15に拡散され、放熱板15の上方は拡が
っているので、抵抗に発生した熱は3次元的に拡散され
、抵抗の破壊が防止される。When a transient voltage or current is applied to the pad, the voltage or current is applied from the pad through the connection pattern 17a to the resistor 13, then through the connection pattern 17b to the diode or a combination of a diode and a transistor, and then to the internal circuit. Ru. At this time, the heat generated in the resistor 13 is diffused to the heat sink 15 formed in the shape of a chimney, and since the upper part of the heat sink 15 is expanding, the heat generated in the resistor is diffused three-dimensionally, and the resistor is destroyed. is prevented.
なお、抵抗13はポリシリコンの他にFP (P形の拡
散Iり、PM (N形の拡散N)などで、また放熱板1
5はA2の他に熱伝導度の高い材料で形成することがで
きる。In addition to polysilicon, the resistor 13 is made of FP (P type diffusion I), PM (N type diffusion N), etc., and the heat sink 1
5 can be formed of a material with high thermal conductivity in addition to A2.
次に第2図を参照にして本発明の方法の工程を説明する
。The steps of the method of the invention will now be described with reference to FIG.
第2図(a)参照:
半導体基板11の5iOz膜12上にポリシリコンを堆
積し、それを通常の技術でパターニングして抵抗13を
形成し、その上にPSGを堆積してPSG膜14を作る
。Refer to FIG. 2(a): Polysilicon is deposited on the 5iOz film 12 of the semiconductor substrate 11, and it is patterned using a conventional technique to form the resistor 13, and PSG is deposited on it to form the PSG film 14. make.
第2図ら)参照:
次いでPSG膜14をパターニングして開口(穴)14
a、 14b、 14cを形成する。穴14aと14b
は後述するAlの接続用パターンのためのものであり、
穴14aと14bの間の穴14cはiの放熱板15を作
るためである。 第2図(C)参照:
全面にAnを付着し、それをパターニングして接続用パ
ターン17a、 17bおよび放熱板15を形成する、
このAffiは半導体集積回路製造の一工程として付着
され、パターニングされるのであるから、本発明の方法
は通常の半導体集積回路製造工程で実施されるものであ
り、特別の工程を必要とするものではない。See Figure 2, etc.: Next, the PSG film 14 is patterned to form openings (holes) 14.
a, 14b, and 14c are formed. Holes 14a and 14b
is for the Al connection pattern described later,
The hole 14c between the holes 14a and 14b is for making the heat sink 15 of i. Refer to FIG. 2(C): Depositing An on the entire surface and patterning it to form connection patterns 17a, 17b and heat sink 15.
Since this Affi is deposited and patterned as part of the semiconductor integrated circuit manufacturing process, the method of the present invention is carried out in the normal semiconductor integrated circuit manufacturing process and does not require any special process. do not have.
最後にカバー膜16を堆積し、第1図に示した入力保護
抵抗を形成する。Finally, a cover film 16 is deposited to form the input protection resistor shown in FIG.
以上のように本発明によれば、抵抗による耐圧限界が改
善され、入力耐圧が向上し、従来の抵抗と同じ面積で前
記効果が得られ、プロセス工程は増加せず、コストに影
響しない利点がある。As described above, according to the present invention, the withstand voltage limit due to the resistor is improved, the input withstand voltage is improved, the above effects can be obtained with the same area as the conventional resistor, the process steps are not increased, and the cost is not affected. be.
第1図は本発明実施例の図で、その(a)は断面図、ら
)は平面図、
第2図(a)〜(C)は本発明実施例の工程の断面図、
第3図は入力保護回路の図である。
図中、
11は半導体基板、
12はSiO□膜、
13は抵抗、
14はPSG膜、
14a、 14b、 14cは穴、
15は放熱板、
16はカバー膜、
17a、 17bは接続用パターン
を示す。
特許出願人 富士通株式会社
代理人弁理士 久木元 彰
岑)f!明丈庶例の工程め釘面国
第2図
11 斗!J一体幕極
12 SiO2膜
14 PSG膿
14a、14b、14c欠
15 a替玉
16 カへ°−謄FIG. 1 is a diagram of an embodiment of the present invention, in which (a) is a sectional view, FIG. 2 (a) to (C) are sectional views of steps in the embodiment of the present invention,
FIG. 3 is a diagram of the input protection circuit. In the figure, 11 is a semiconductor substrate, 12 is a SiO□ film, 13 is a resistor, 14 is a PSG film, 14a, 14b, and 14c are holes, 15 is a heat sink, 16 is a cover film, and 17a and 17b are connection patterns. . Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akimoto Kuki) f! Meijo general process Megumenkuni Figure 2 11 Do! J single curtain pole 12 SiO2 film 14 PSG pus 14a, 14b, 14c missing 15 a spare ball 16
Claims (1)
保護抵抗(13)と、 該入力保護抵抗(13)を含む基板(11)上に形成さ
れた絶縁膜(14)と、該絶縁膜をパターニングして形
成された前記入力保護抵抗(13)に達する開口(14
a、14b、14c)と、 該開口を介して該入力保護抵抗のみに接続され放熱板(
15)として作用する金属層とを具備することを特徴と
する半導体装置。[Claims] An input protection resistor (13) connected to an input pad on a semiconductor substrate (11), and an insulating film (14) formed on the substrate (11) including the input protection resistor (13). and an opening (14) reaching the input protection resistor (13) formed by patterning the insulating film.
a, 14b, 14c), and a heat sink connected only to the input protection resistor through the opening (
15) A semiconductor device characterized by comprising a metal layer acting as a metal layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26930487A JPH01112762A (en) | 1987-10-27 | 1987-10-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26930487A JPH01112762A (en) | 1987-10-27 | 1987-10-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01112762A true JPH01112762A (en) | 1989-05-01 |
Family
ID=17470478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26930487A Pending JPH01112762A (en) | 1987-10-27 | 1987-10-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01112762A (en) |
-
1987
- 1987-10-27 JP JP26930487A patent/JPH01112762A/en active Pending
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