JPS58155437A - Separation type direct memory accessing circuit - Google Patents

Abstract

PURPOSE:To separate a control system from a system to be controlled to install them, by dividing a direct memory accessing circuit into two, and inserting a line driver/receiver circuit into each divided surface. CONSTITUTION:A direct memory accessing (DMA) circuit is separated into a control part side circuit 1 and a controlled part side circuit 2. The control part side DMA 1 consists of a memory circuit 3, an address selector circuit 5, a latching circuit 4 and line drivers/receivers 6, 7. The controlled part side DMA 2 consists of line drivers/receivers 8, 9 and a latching circuit 10. In this way, the data tranmission delay is covered, and a transmission line which is strong against a noise can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access (DMA) circuit, and in particular to a direct memory access (DMA) circuit that operates according to instructions from a control unit, is located between a controlled unit, and has the role of data transmission.
In a memory access (hereinafter referred to as DMA) circuit,
The present invention relates to a DMA circuit in which the circuit is divided into a control section side circuit and a controlled section side circuit, which are connected to a line driver/receiver by a cable, and a data preemption mechanism is provided.

Conventionally, by interfacing the control system and the controlled system,
When performing MA operation, a relay D is connected to either system.
When an MA circuit is installed and data is transmitted from the control system to the controlled system using a data recognition response signal from the transmission control system, the connection between the control unit, DMA circuit, and controlled unit may be difficult due to noise or transmission delay time constraints. had to be established. Therefore, it is impossible to install the control system device and the controlled system device side by side, and there is a drawback that the floor layout is limited.

The present invention divides a DMA circuit into two parts, and inserts a line e-driver/receiver circuit into each of the divided surfaces to implement the two electrically terminated separate and independent circuits in the control system and the controlled system. The above disadvantages are solved by creating a structure in which cables are connected between the three parties, and by providing a data prefetching mechanism to avoid delays between the cables. Separate type DM that is resistant to noise and covers data transmission delay in DMA operation
A circuit is provided.

That is, according to the present invention, a latch circuit that holds data input/output from a memory circuit accessed by an address selector circuit, and a line driver/
Leno-3 circuit 7, a circuit group comprising another driver/receiver circuit that relays control signals for accessing the address selector circuit, and data and control signals that are input/output to and from this circuit group by cable connection. Relay line/
It consists of a circuit group that includes a driver/receiver circuit and a latch circuit for holding data, and a connection cable that connects the two circuit groups.

By arranging the two circuit groups in the control system and the controlled system, respectively, a separate type DMA circuit is obtained, which is characterized in that the control system and the controlled system can be installed separately.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to the diagram illustrating a DMA circuit according to the invention, an embodiment of the invention includes a memory circuit 3 and an address selector circuit 5.
, a latch circuit 4 that inputs and outputs to and from this memory circuit 3, and the address selector circuit 5 and the latch circuit WP! 4 and a line driver/receiver circuit 6.7 for interfacing with the control unit side circuit 1 and the data and control lines that input and output the control unit side circuit 1. receiver circuit 8119;
A latch circuit 1 that exchanges data with the latch circuit 4
0, and a cable 1 for connecting the control unit side circuit l and the controlled unit side circuit 2.
1.

Next, the operation of the present invention will be explained with reference to the drawings. Delays in data transmission become a problem when a DMA operation is performed from the control system to the controlled system using a data recognition response signal from the controlled system, as in the example shown in Figure 1. In particular, we will focus on data transmission from the control system to the controlled system.

First, a DMA start command from the control section is transmitted to the multi-control section side DMA circuit 1 through the DMA control command line 18, and immediately the address selector circuit 5 accesses the O address of the memory circuit 3 via the address select line 17. The resulting data at address 0 is stored in the latch circuit 4 via the latch control line 16, and then sent to the DMA circuit 2 on the controlled unit side through the line driver/receiver circuit 6 and connection cable 11.
transmitted to. At the same time, the DMA start command is transmitted to the controlled unit side DMA circuit 2 through the line driver/receiver circuit 7 and the connection cable 11.

Next, in the controlled part@DMA circuit 2, the data at address θ received by the line driver/receiver circuit 8 is sent to the latch circuit through the latch control line 19 by the DMA start command received by the line driver/receiver circuit 9. It is held to 10.

Furthermore, the DMA start command is transmitted to the controlled section through the DMA control command line 20, and the controlled section that receives the command prepares for DMA.

Next, when the controlled section completes the DMA preparation, the latch circuit 1
It reads the data at address 0, which has been kept at 0, and sends a response signal to the data recognition response line 21.
) is transmitted to the address selector circuit 5 of the control section side DMA circuit l through the line driver/receiver circuit 7,
Address selector circuit 5 selects the next address (titM)
is selected and the memory circuit 3 is accessed via the address/select line 17, and the data at address 1 is sent to the controlled unit lllllDMA circuit 2 in the same manner as the data at address θ described above, and is transferred to the latch circuit lO, where the data at address θ is transferred to the latch circuit lO. Wait for the department to read it. By repeating this process, a predetermined amount of data is sequentially sent to the controlled unit.

As explained above, in the present invention, when a data recognition response signal from a controlled system is used as a timing pulse to perform a DMA operation between a control system and a controlled system, a signal is divided into two by a line driver/receiver circuit. By configuring a DMA circuit with a data prefetch mechanism that sends data to the controlled system in advance, it not only covers data transmission delays, but also secures a transmission path that is resistant to noise. This has the advantage of being able to be installed separately and independently.

[Brief explanation of drawings]

The figure is an example of a separate DMA circuit according to the present invention.

Claims (1)

[Claims] A latch circuit that holds data input and output from a memory circuit accessed by the address selector circuit, a line driver/receiver circuit that follows this, and a line driver/receiver circuit that relays control signals that access the address selector circuit. A circuit group comprising a receiver circuit, a line driver/receiver circuit that relays data and control signals to be input/output through a cable connection to this circuit group, and a latch circuit for holding data. , and a connection cable that connects the two circuit groups, and by placing the two circuit groups in the control system and the controlled system, respectively, the control system and the controlled system can be installed separately. A separate direct memory access circuit featuring: