JPS6214160B2 - - Google Patents
Info
- Publication number
- JPS6214160B2 JPS6214160B2 JP55025310A JP2531080A JPS6214160B2 JP S6214160 B2 JPS6214160 B2 JP S6214160B2 JP 55025310 A JP55025310 A JP 55025310A JP 2531080 A JP2531080 A JP 2531080A JP S6214160 B2 JPS6214160 B2 JP S6214160B2
- Authority
- JP
- Japan
- Prior art keywords
- control
- processor
- communication
- communication path
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004891 communication Methods 0.000 claims description 31
- 238000012545 processing Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Exchange Systems With Centralized Control (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Description
【発明の詳細な説明】
本発明は、機能負荷分散方式マルチプロセツサ
交換処理システムにおける通話路制御方式に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication path control method in a multiprocessor switching processing system with functional load distribution.
従来この種の通話路制御方式は第１図に示すよ
うに、時分割通話路にくくりつけられた通話路制
御プロセツサ（NP）３により行われていた。第
１図において、１は交換接続制御プロセツサ
（CPp〜CＰo）、２は共通メモリ（CM）、３は通話
路制御プロセツサ（NPp〜NPn）、４はデイジタ
ル信号処理装置（DSGEp〜DSGEn）、５は時分割
通話路装置（NWp〜NWn）、６はプロセツサ間通
信制御装置（IPC）である。この方式は、通話パ
スの選択を終了した後、交換接続制御プロセツサ
例えばCPp１から通話路制御プロセツサ例えば
NPp３へプロセツサ間通信制御装置（IPC）６を
介して制御を指示し、通話路制御プロセツサ
（NPp）３が通話路制御オーダを作成し、対応す
る通話路（NWp）５を駆動するという方式であ
る。またこの通話路制御プロセツサ（NPp）３は
同様に（CPp）１からの制御指示によりトランク
制御オーダを作成し、対応するデイジタル信号処
理装置（DSGEp）４の制御を行なつている。こ
のため、通話路制御プロセツサ（NP）３の内部
処理遅延により通話路駆動時間が延びるという問
題があつた。特に通話路制御プロセツサ（NP）
３が高負荷時には、該（NP）３に制御されてい
た呼びの通話路制御が遅延するという交換機のサ
ービス低下をまねく欠点もあつた。 Conventionally, this type of channel control system has been carried out by a channel control processor (NP) 3 attached to a time-division channel, as shown in FIG. In FIG. 1, 1 is a switching connection control processor (CP p to CP o ), 2 is a common memory (CM), 3 is a communication path control processor (NP p to NP n ), and 4 is a digital signal processing device (DSGE). p to DSGE n ), 5 is a time division channel device (NW p to NW n ), and 6 is an interprocessor communication control device (IPC). In this method, after completing the selection of the call path, the switching connection control processor, e.g.
Control is instructed to NP p 3 via the interprocessor communication controller (IPC) 6, and the channel control processor (NP p ) 3 creates a channel control order and drives the corresponding channel (NW p ) 5. The method is to do so. Similarly, this communication path control processor (NP p ) 3 creates a trunk control order based on control instructions from (CP p ) 1, and controls the corresponding digital signal processing device (DSGE p ) 4. Therefore, there was a problem in that the communication path driving time was extended due to the internal processing delay of the communication path control processor (NP) 3. Especially the call path control processor (NP)
When NP 3 is under high load, the control of the call path controlled by NP 3 is delayed, resulting in a deterioration in the service of the exchange.
また、交換接続制御プロセツサ（CP）１で
は、プロセツサ間通信を用いるため、固定分＋ト
ランク制御情報＋通話路制御情報等、数ワードの
オーダ編集をしなければならなかつた。さらにト
ランク制御と通話路制御のためにプロセツサ
（NP）が共用されるため、融通性に欠ける面があ
つた。 Furthermore, since the exchange connection control processor (CP) 1 uses inter-processor communication, several words of fixed information, trunk control information, call path control information, etc. had to be edited in an orderly manner. Furthermore, because the processor (NP) was shared for trunk control and call path control, there was a lack of flexibility.
本発明の目的は、上記した従来方式の欠点をな
くし、通話路駆動までの処理時間を短縮すると共
にオーダ編集を簡略化し、融通性の高い通話路制
御方式を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a highly flexible communication path control system that eliminates the drawbacks of the conventional system described above, shortens the processing time required to drive the communication path, and simplifies order editing.
このため本発明は、機能負荷分散形マルチプロ
セツサ方式時分割電話交換システムにおいて、デ
イジタル通話路の制御駆動時間の高速性を活か
し、交換接続制御プロセツサから、交換接続制御
プロセツサで実行する１命令実行時間（μsec単
位）とほぼ同じ時間単位での通話路駆動を行なわ
せるために、該プロセツサに通話路直接制御命令
を具備させることにより直接該プロセツサから通
話路へ、通話路駆動オーダの送出を可能とするも
のである。また、トランク制御は専用のトランク
制御プロセツサを設け、そのプロセツサにてトラ
ンク制御を自律的に行なわせることで、融通性を
持たせるものである。 For this reason, the present invention utilizes the high-speed control driving time of digital communication channels in a functional load distributed multiprocessor type time-division telephone switching system to execute a single instruction executed by the switching connection control processor from the switching connection control processor. In order to drive the channel in approximately the same time unit as time (μsec), by equipping the processor with a channel direct control command, it is possible to send the channel drive order directly from the processor to the channel. That is. Further, trunk control is provided with a dedicated trunk control processor and is made to perform trunk control autonomously, thereby providing flexibility.
以下、本発明を図に従つて詳細に説明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第２図は本発明による機能分散形マルチプロセ
ツサ方式時分割電話交換システムの１実施例を示
す図である。第２図において、１１は交換処理の
接続制御、サービス制御等を行なう交換接続制御
プロセツサ（CPp〜CPi）で、タスク単位即ち呼
制御上で最小単位で負荷分散されている。１２は
プロセツサ（CPp〜CPi）から読み書き可能な共
通メモリ（CM）、１３はトランクなどのデイジ
タル信号処理装置（DSGE）の制御を行なうトラ
ンク制御プロセツサ（TKPp〜TKPj）で規模分
散されている。１４は（TKPp〜TKPj）１３に
対応して設置され、夫々回線の監視及び信号送受
機能をもつ複数のトランクなどからなるデイジタ
ル信号処理装置（DSGEp〜DSGEj）、１５は時分
割スイツチなどにより構成され、夫々複数の回線
を収容する通話路装置（NWp〜NWk）、１６は
（CPp〜CPi）１１と（TKPp〜TKPj）１３及び
（NWp〜NWk）１５間の通信を行なう通信制御装
置であり、これら装置間のデータ転送制御とプロ
セツサ間バスアクセス競合の制御を自律的に行な
うものである。 FIG. 2 is a diagram showing an embodiment of a function-distributed multiprocessor type time-division telephone switching system according to the present invention. In FIG. 2, reference numeral 11 denotes exchange connection control processors (CP p to CP i ) that perform connection control, service control, etc. of exchange processing, and the load is distributed in units of tasks, that is, in minimum units in call control. 12 is a common memory (CM) that can be read and written from processors (CP p to CP i ), and 13 is a trunk control processor (TKP p to TKP j ) that controls digital signal processing equipment (DSGE) such as trunks, which are distributed in scale. ing. 14 is a digital signal processing device (DSGE p to DSGE j ) which is installed corresponding to (TKP p to TKP j ) 13 and consists of a plurality of trunks each having a line monitoring and signal transmission/reception function, and 15 is a time division switch. communication path devices ( NW p to NW k ) each accommodating a plurality of lines ; This is a communication control device that performs communication between 15 and 15, and autonomously controls data transfer between these devices and controls bus access contention between processors.
今、通話路装置（NWp）１５に収容される回
線から送られてきた場合は、その信号は
（NWp）１５を介して例えばデイジタル信号処理
装置（DSGEp）１４のトランクに引き込まれ、
受信される。この受信結果は定期監視を行なつて
いるトランク制御プロセツサ（TKPp）１３に送
られる。TKPp）１３で信号の変化を検出する
と、それを分析し、論理信号の形で通信装置
（IPC）１６を介して、例えば交換接続制御プロ
セツサ（CPp）１１では、接続制御、サービス制
御等を行なうが、通話路の接続動作を行なうとき
は、（CPp）１１により（NWp）１５を駆動する
通話路駆動オーダを作成する。このオーダは、第
１図に示す方式ではプロセツサ間通信を用いるた
め、固定分＋トランク情報＋通話路情報等、数ワ
ードの編集をしなければならないが、本方式では
通話路の制御のみであるため、１ワードのオーダ
編集で済む。（CPp）１１により作成されたオー
ダは、（IPC）１６を介して直接（NWp）１５に
送出される。（NWp）１５がこのオーダを受信す
ると、直ちに該オーダに従つて自通話路の開閉駆
動を行なう。しかる後、（NWp）１５で該オーダ
の実行が終了すると、（IPC）１６を介して
（CPp）１１に対し、実行終了の報告を行なう。
（CPp）１１ではオーダ送出後、実行終了報告待
ちとなるが、この報告を受信することで、
（NWp）１５の駆動が終了したこととなり、次処
理へ制御が渡る。 Now, if the signal is sent from a line accommodated in the communication channel device (NW p ) 15, the signal is drawn into the trunk of the digital signal processing device (DSGE p ) 14 via the (NW p ) 15, for example, and
Received. This reception result is sent to the trunk control processor (TKP p ) 13 which performs periodic monitoring. When a change in the signal is detected in the TKP p ) 13, it is analyzed and transmitted in the form of a logical signal to the communication device (IPC) 16, for example in the switching connection control processor (CP p ) 11 for connection control, service control, etc. However, when performing a communication path connection operation, a communication path drive order for driving (NW p ) 15 by (CP p ) 11 is created. This order uses interprocessor communication in the method shown in Figure 1, so it is necessary to edit several words such as fixed portion + trunk information + call path information, but in this method, only control of the call path is required. Therefore, you only need to edit one word to order. The order created by (CP p ) 11 is sent directly to (NW p ) 15 via (IPC) 16 . When the (NW p ) 15 receives this order, it immediately opens and closes its own channel according to the order. Thereafter, when the execution of the order is completed at (NW p ) 15, the execution completion is reported to (CP p ) 11 via (IPC) 16.
(CP p ) In 11, after sending the order, it waits for the execution completion report, but by receiving this report,
(NW p ) 15 has been driven, and control is passed to the next process.
一方、（CPp）１１から（TKPp）１３へ通信す
るときも論理信号がデータとして（IPC）１６を
介して送られる。（TKPp）１３では送られてき
た信号を分析し、（DSGEp）１４を制御して信号
を通話路経由で回線へ送る。 On the other hand, when communicating from (CP p ) 11 to (TKP p ) 13, logic signals are also sent as data via (IPC) 16. (TKP p ) 13 analyzes the sent signal, controls (DSGE p ) 14, and sends the signal to the line via the communication path.
以上説明したように本発明は、デイジタル通話
路の制御駆動時間の高速性を活かし、交換接続制
御プロセツサより通話路を直接駆動することによ
り、通話路駆動処理時間の短縮化をはかることが
でき、システム全体の通話路駆動処理時間が平均
化され、安定したサービスの提供ができる。ま
た、交換接続制御プロセツサ内でのオーダの編集
が簡略化される利点もある。さらに、トランク制
御が専用のトランク制御プロセツサにて自律的に
行なわれるため、ソフトウエアの負担が軽減さ
れ、局規模や機能拡張に容易に対処できる等融通
性の高いシステムが構成できる。 As explained above, the present invention takes advantage of the high-speed control driving time of digital communication paths, and by directly driving the communication paths from the exchange connection control processor, it is possible to shorten the communication path drive processing time. The communication path drive processing time for the entire system is averaged, making it possible to provide stable services. There is also the advantage that editing of orders within the exchange connection control processor is simplified. Furthermore, since trunk control is carried out autonomously by a dedicated trunk control processor, the burden on software is reduced, and a highly flexible system can be constructed that can easily cope with station scale and function expansion.
第１図は従来方式のシステム構成図、第２図は
本発明の１実施例によるシステム構成図である。
１，１１……交換接続制御プロセツサ（CP）、
２，１２……共通メモリ（CM）、３……通話路
制御プロセツサ（NP）、１３……トランク制御プ
ロセツサ（TKP）、４，１４……デイジタル信号
処理装置（DSGE）、５，１５……時分割通話路
装置（NW）、６，１６……プロセツサ間通信制
御装置（IPC）。
FIG. 1 is a system configuration diagram of a conventional system, and FIG. 2 is a system configuration diagram according to an embodiment of the present invention. 1, 11...exchange connection control processor (CP),
2, 12... Common memory (CM), 3... Channel control processor (NP), 13... Trunk control processor (TKP), 4, 14... Digital signal processing device (DSGE), 5, 15... Time division channel device (NW), 6, 16...Interprocessor communication control device (IPC).
Claims (1)
構成されるマルチプロセツサ方式の交換システム
において、夫々複数の回線を収容する通話路装置
群と、回線の監視及び信号送受機能をもつトラン
クの制御を行なうトランク制御用の第１のプロセ
ツサ群と、交換処理の接続制御を行なう交換接続
制御用の第２のプロセツサ群とを有し、第１のプ
ロセツサ群と第２のプロセツサ群と通話路装置群
を、それら装置間のデータ転送制御を行なうプロ
セツサ間通信装置で相互に結合し、トランク制御
は前記第１プロセツサにて自律的に行ない、通話
路制御は前記通信装置を介して前記第２のプロセ
ツサ群のプロセツサにて直接行なうことを特徴と
する通話路直接制御方式。1. In a multiprocessor type switching system consisting of multiple processors with different processing functions, control is performed on a group of communication line devices each accommodating multiple lines, and on trunks that have line monitoring and signal sending/receiving functions. It has a first processor group for trunk control and a second processor group for switching connection control that performs connection control for switching processing, and the first processor group, the second processor group, and the communication path device group are connected to each other. , are interconnected by an interprocessor communication device that controls data transfer between these devices, trunk control is autonomously performed by the first processor, and communication path control is performed by the second processor group via the communication device. A communication path direct control method characterized by direct control by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2531080A JPS56122587A (en) | 1980-03-03 | 1980-03-03 | Direct channel control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2531080A JPS56122587A (en) | 1980-03-03 | 1980-03-03 | Direct channel control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56122587A JPS56122587A (en) | 1981-09-26 |
| JPS6214160B2 true JPS6214160B2 (en) | 1987-03-31 |
Family
ID=12162420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2531080A Granted JPS56122587A (en) | 1980-03-03 | 1980-03-03 | Direct channel control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56122587A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0650916B2 (en) * | 1987-04-09 | 1994-06-29 | 日本電気株式会社 | Distributed exchange trunk selection method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54124906A (en) * | 1978-03-22 | 1979-09-28 | Nec Corp | Channel control system of automatic switchboard |
-
1980
- 1980-03-03 JP JP2531080A patent/JPS56122587A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54124906A (en) * | 1978-03-22 | 1979-09-28 | Nec Corp | Channel control system of automatic switchboard |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56122587A (en) | 1981-09-26 |
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