JPS58153429A - Phase locking device - Google Patents

Abstract

PURPOSE:To expand a pull-in range of PLL equivalently without changing the pull-in range actually in spite of the offset of the frequency of an incoming input signal. CONSTITUTION:A multiplier 5 for video detection synchronously detects an intermediate frequency signal from an input terminal (a) by a carrier signal component reproduced by a voltage controlling oscillator 3, to reproduce a video signal at an output terminal (b). A frequency detecting means 6 is connected to the input terminal (a). The frequency detecting means 6 is provided with a frequency discriminator and a discriminated frequency controlling means to vary the intermediate frequency of the discriminator by the output signal voltage of the discriminator. The output voltage (d) of the frequency detecting means 6 is used as a control signal to follow the free-running frequency of a voltage controlling oscillator 3 to the frequency of the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronization device suitable for application to an amplitude synchronized detector.

The so-called amplitude synchronous detection has a voltage controlled oscillator (hereinafter abbreviated as VCO in the present invention), synchronizes this oscillator with an incoming input signal to regenerate a carrier signal, and obtains a modulated signal by multiplicative detection with the input signal. In known super-hetero gain receivers, if the pull-in range of the phase-locked loop (hereinafter abbreviated as PLL) that controls the oscillator is narrow, the incoming input signal frequency is offset or converted to an intermediate frequency by a local oscillator. If the frequency differs from the standard frequency due to instability of the oscillator, the detection operation cannot be maintained, so the detection distortion and PL of the synchronous detector
It is impossible to set the L pull-in range separately. In a receiver, for example a television, the oscillation frequency of the local oscillator is varied from the standard frequency by several hundred KH2 to several MH2 to eliminate reception interference caused by interference signals or to improve reception sensitivity when receiving weak signals. This is necessary due to the close-up of Therefore, when the video detector is configured with a synchronous detector, the phase-locked loop that controls the voltage-controlled oscillator requires a significantly wide pull-in range, while the frequency selection range of the PLL is required to ensure good video detection characteristics. Conventionally, in order to selectively control the operating conditions of these essentially different PLLs, in the asynchronous state, the loop filter is widened or a sweep voltage is generated to sweep vCO, and in the synchronous state Various methods have been proposed, such as narrowing the loop filter to improve the detection characteristics.
In both cases, the tracking synchronization mechanism for the incoming input signal frequency is PLL.
This method requires a significant increase in the loop gain due to the holding characteristics of the video detector, which not only has the disadvantage of instability, but also causes distortion in the video detector when synchronizing to a frequency offset signal of several MHz. It has extremely large practical drawbacks.

The present invention provides a PL
The purpose is to expand the drawing range of L in an equally economical way without making any substantial change.

According to the present invention, the phase synchronizer has a PLL that synchronizes the VCO with an incoming input signal converted to a predetermined intermediate frequency, and the VCO uses a frequency detection means to detect the carrier frequency of the intermediate frequency signal to detect the carrier frequency of the intermediate frequency signal. It is possible to control the free-running oscillation frequency to approximately follow the carrier wave frequency of the signal. For this purpose, the detection means is configured such that the output voltage changes approximately linearly within a predetermined range with respect to changes in the frequency of the intermediate frequency signal. However, it is also possible to generate an automatic synchronization signal voltage for stabilizing the operation of known local oscillators. The present invention will be described in detail below with reference to the drawings, but for convenience, a television receiver suitable for application of the present invention will be described as an example.

FIG. 1 is a block diagram showing the configuration of a video detector using a general PLL. Phase comparator 1LPF2, V
A PLL consisting of a phase shifter 4 of CO3, π/2 (rad) applies vCO to the carrier wave of the video intermediate frequency signal at the signal input terminal a.
3, but since this operating mechanism is known, detailed explanation will be omitted.

The multiplier 6 for video detection performs synchronous detection of the carrier wave reproduced by the VCO 3 from the video intermediate frequency signal at the signal input terminal a using the signal component, and reproduces the video signal at the signal output terminal. The present invention always maintains the detection phase of the multiplier 6 in an optimum state by making the free-running oscillation frequency of the carrier wave recovery V and CO3 for video detection follow the carrier wave frequency of the intermediate frequency signal at the terminal a. High performance by
It is intended to realize a highly stable device, and for this purpose, in the device of the present invention, as shown in FIG. be done. For example, as already shown in FIG. 4, this detection means detects changes in the carrier frequency of the incoming input signal within a predetermined range (in the figure, fo and Δf).

fo is the standard intermediate frequency), but ideally the VCOs described above are configured so that their output voltage changes approximately linearly.
It is desirable to match the voltage-frequency conversion characteristics of . The output signal voltage of the frequency detection means is sent to terminal d, and PL
The oscillation frequency of the VCO 3 is controlled either directly with the output signal component of the L phase comparator 1 or as shown in the figure (added with the output of the LPF 2).
If the characteristics are as shown in the figure, the VCO 3 is selected so that its oscillation frequency decreases linearly as the control voltage increases1, and if the control sensitivity and controlled sensitivity match, the incoming input The free-running oscillation frequency of the VCO perfectly follows the frequency change of the signal. Therefore, the center frequency of PLL pull-in is variable, and the frequency difference between the incoming input signal frequency and the free-running oscillation frequency of the VCO becomes zero, so generation of an extremely small control voltage for phase control is sufficient. Therefore, it is possible to reduce the DC loop gain. Furthermore, even when the pull-in range of the PLL basic loop is narrow, ro+△f(
The pull-in range is expanded to the effective operating range of the ΔfM frequency detection means. Needless to say, the output signal of the frequency detection means is independently input to the VC without passing through the adder.
The ability to control O, the placement of the adder between the phase comparator 1 and the LPF 2, etc. may be selected as appropriate in implementing the present invention.

Next, a configuration example of the frequency detection means arranged in the present invention will be explained. In FIG. 2 above, π/
A frequency discriminator including a 2 (rad) phase shifter 61 and a multiplier 62 is shown to be controlled by the output of an LPF 63 which obtains a substantially DC signal voltage from the output signal of the multiplier 62. The phase shifter 61 has a variable frequency configuration that provides a phase shift amount of π/2 (rad). Therefore, the discrimination frequency changes in accordance with changes in the input signal frequency, and the LPF
The output signal voltage 63 has a frequency discrimination characteristic that matches the voltage-phase shift amount conversion characteristic of the phase shifter 61. The discrimination frequency control mechanism included in the frequency detection means suitable for carrying out the present invention will be described in more detail with reference to FIG. This third
The figure shows a specific circuit configuration of the π/2 (rad) phase shifter 61. A tuned circuit including a capacitor 610 and an inductance 611 connected in parallel, and a capacitor 612 connected in series between this circuit and the input terminal C are a π/2 (rad) phase shifter that resonates in series at the road sign rate intermediate frequency. Form. The coupling capacitor 613 and the voltage-to-capacitance conversion element 614 are used to vary the tuning frequency of the tuning circuit, that is, the series resonance frequency, by a control voltage supplied through the resistor 616.

If the phase control feedback voltage from the LPF 63 is cut off by the switch 64 and the control voltage is supplied from the voltage source 10 as shown by the broken line in the figure, the output terminal of L P Fe2 will have a voltage as shown by al in Fig. 4 a. A known frequency detection characteristic in which the discrimination center frequency is set to fO is obtained. Since the cathode of the voltage-to-capacitance conversion element 614 is connected to the positive voltage source VCC, as the control voltage across the resistor 615 increases, its capacitance increases, thus shifting the series resonant frequency to the lower side. The decrease in the -force control voltage changes its resonant frequency towards the higher side. If the output signal voltage of the LP 163 is set as the control voltage of the voltage-capacitance conversion element by switching the switch 64 to the solid line side, the same effect will occur if the carrier frequency of the intermediate frequency signal changes to a lower side as shown in FIG. 4a. If the center frequency of the frequency discrimination characteristic changes to a lower direction as shown in FIG. a2, and if the carrier wave frequency changes to a higher direction, the discrimination center frequency is moved to a higher direction as shown by a3 in the same figure.

Straight line a4 is π/2(r
ad) Voltage-phase shift amount conversion characteristics of the phase shifter, LPF
The output signal voltage of 63 becomes stable at the intersection of these discrimination characteristics and conversion characteristics (indicated by black dots), and therefore, the frequency discrimination characteristics shown in the same figure correspond to the frequency change of the video intermediate frequency signal of input terminal C. , and a VCO control voltage that varies approximately linearly within a variation range of +Δf centered around the standard frequency fo is obtained. In FIG. 3, switch e6 linked to switch 64 numbered 10 is LP.
It is arranged between Fe3 and the new signal output terminal e.

These switch arrangements are particularly suitable for applications in equipment such as television receivers. If the switches 64 and 65 are connected to the side indicated by the dashed line, the frequency detection means 6 automatically control the local oscillator to oscillate at the standard frequency, and the terminal d is then set to a fixed bias by the voltage source EO. Therefore, the voltage-to-capacitance conversion element 614 is fixed and controlled only by the vcoFi phase comparator of the PLL. On the other hand, when these switches are connected to the solid line side, the terminal e outputs the bias voltage of the voltage source KO, and therefore the local oscillator can offset the oscillation frequency. In this state, the output signal of the LPF 63 is output to the terminal d. Since voltage is supplied, the PLL's vCo follows changes in the intermediate frequency. These are significant practical advantages that allow the receiver to operate stably under various operating conditions.

As explained above, the present invention allows the free-running frequency of the VCO to follow the frequency change of the incoming input signal with an extremely inexpensive configuration, making it possible to substantially or completely match the frequency change of the incoming input signal.
Not only can the stability of an amplitude synchronous detector using LL be significantly improved, but also the detection phase can always be maintained in a predetermined and suitable state. Needless to say, PL
It is also possible to combine known methods such as switching the time constant of a sweep or loop filter for expanding the pull-in range of L, and the present invention also provides a method for controlling the discrimination frequency in the frequency detection means whose specific configuration is shown. The present invention is not limited to this embodiment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an amplitude synchronized detector using a general PLL, and FIG. 2 is a block diagram showing the basic configuration of a phase synchronization device in an embodiment of the present invention. Further, FIG. 3 is a circuit diagram including a partial specific configuration of a frequency detection circuit suitable for implementing the present invention, and FIG. 4 is a characteristic diagram used for explaining the present invention. 1... Phase comparator, 2... LPF, 3
...VCO. 4... Phase shifter, 6... Multiplier, 6...
... Frequency detection means, 61 ... Phase shifter, 6
3...LPF, 62...8 multiplier. Figure 1 Figure 4

Claims (1)

[Claims] (1) A phase-locked loop 1 including a voltage-controlled oscillator and a phase comparator for synchronizing this oscillator with an incoming input signal, and a frequency at which the output voltage changes depending on the frequency of the input signal. The frequency detecting means includes a frequency discriminator and discrimination frequency control means for varying the center frequency of the discriminator by the output signal voltage of the discriminator, and the frequency detecting means includes an output signal voltage of the frequency detecting means, A phase synchronization device characterized in that the free-running frequency of a voltage controlled oscillator is used as a control signal to approximately follow the input signal frequency. (2) The phase synchronization device according to claim 1, wherein the output signal voltage of the phase comparator and the output of the frequency detection means are added, and the added output signal voltage is used as the control voltage of the voltage controlled oscillator. (3) Discriminative frequency control in which the frequency detection means is comprised of a voltage-side variable phase shifter that shifts the phase of the incoming input signal and this signal by approximately π/2 (rad) within a predetermined frequency range. 2. A phase synchronizer according to claim 1, further comprising a multiplier to which the output signal of the means is supplied. (4) The variable phase shifter includes a parallel tuned circuit including at least a first capacitor and an inductance, a second capacitor that supplies an incoming input signal component to the parallel tuned circuit, and a tuning frequency of the parallel tuned circuit that is variable. Claim 3 constituted by a voltage controlled variable capacitance element of the same type.
Phase synchronization device as described in section. (6) first signal selection means for controlling the discrimination frequency control means by either the output signal voltage of the frequency detection means or a predetermined first reference DC voltage; a second signal selection means for controlling the local oscillation means for setting the incoming input signal frequency by one of the second reference DC voltages, at least the discrimination frequency control means and the local oscillation means; 2. The phase synchronization device according to claim 1, wherein either one of the oscillation means is always controlled by the output signal voltage of the frequency detection means. (6) The phase synchronizer according to claim 5, wherein the first and second reference DC voltages are supplied by a single DC voltage source.