JPS58151771A - Converter of pictur element density - Google Patents

Abstract

PURPOSE:To make the contraction and enlargement of a picture of a high- speed projecting method efficient and to reduce the memory capacity, by discriminating the region of a center position of a converted picture element, and discriminating the picture element based on the relational equation between the signal of preset original picture element and the signal of the converted picture element at each split region in advance. CONSTITUTION:An input counter 312 and an input line counter 314 are connected to an RAM311 of an input buffer 31 via an address multiplexer 316, and a picture signal for main and subscanning line's share is stored in the RAM311. The RAM311 is connected with a timing forming circuit 330, which is connected to a picture element location operating section 34 calculating the picture element location after conversion in an original picture plane based on the conversion magnification. The operating section 34 is connected with a region deciding section 35 deciding the center location of the calculated conversion picture element. A picture element section 32 connected to the deciding section 35 and a demultiplexer 315 of the RAM311 decides the picture element of the signal of the preset original picture element and the signal of the conversion picture element at each split region in advance, allowing to contract and enlarge the picture efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a density conversion device that enlarges or JLJ-images to an arbitrary magnification by pixel density conversion, and more specifically, it easily performs artist density conversion using a projection method.
The present invention relates to the constructed pixel density conversion device.

Now, in intelligent copiers that have an editing function, etc., the image information is transmitted through electrical signals.
Recording, etc. is performed, but when placing the whole or a part of it in another predetermined position, the 1tir is recorded at an arbitrary magnification.
*It becomes necessary to enlarge or reduce the whole or a part thereof, that is, to perform a scaling operation.

In addition, in the IIII transmission system, due to differences in scanning line density between input and output devices, the size of the Miji image and the recorded image after transmission may differ, and in order to correct this, pixel density conversion is required. is required.

As specific methods for this scaling operation, the SPC method and the 9-division WiJ density conversion method have been proposed.
In the law, there is a noticeable "missing" (lack of black art ethics) in the reduced 1-rin,
In the 9-division method, there was a problem with the capital where the line became thicker in both expanded 1 rin and reduced ij rin.

Therefore, a projection method, which is a pixel density conversion that belongs to so-called geometric mode conversion, has been proposed, and is known to provide better image quality than the above two methods. In this projection method, the density of transformation 1 and original 3 is equal to V, and it is a method that causes few changes in connection and separation of graphic components due to increase or decrease in front black lines. However, this required a large amount of calculation processing and a complicated hardware configuration.

The present invention is based on a patent application filed on December 4, 1997, entitled ``Mis scaling method using pixel density conversion,'' which was proposed in order to solve the problems of the projection method. We propose a highly efficient device.

Conventionally, in Tanu's device that converts pixel density, each
It is necessary to store all the relational expressions for calculating the converted pixel from the M volume in the hardware configuration or in the memory, which inevitably increases the memory capacity. In addition, the concept of the projection method itself was new and a specific implementation device had not yet been disclosed.

The present invention provides a pixel position calculation unit that calculates a converted m* position within an original pixel plane that performs pixel density conversion using a projection method;
an area determination unit that determines the area in which the center of the transformation '#i' calculated by the pixel position calculation unit is located; This is accomplished by a single-kick density conversion device having a pixel determination unit that calculates based on a relational expression of the image quality signal of the converted pixel.

Further, in order to make the processing more efficient, the storage unit is configured to store one line signal input for three scanning lines, and among the storage means for each three scanning lines, the original m11! By configuring the buffer section to form a plane, and during the timing when pixel density conversion processing is being performed on the j The next original pixel information is input and stored in the storage means of the original pixel plane, and the pixel determination section is
ii) By configuring a logic circuit that outputs an image quality based on the relational expression for each region divided into eight regions based on a projection method, and by storing a code indicating the region in the region determination section. Further, the area determining section stores a line indicating a boundary dividing an area in at least one quadrant of the original pixel plane into two, and the data in the storage means is used as a reference input. A comparison circuit may be provided, and the area determination unit may determine the area determination unit for two areas within a specific quadrant of the area based on the value of the fractional part of the converted pixel position calculated by the pixel position calculation unit. There is a means for region determination, and the determination is made in correspondence with two regions within the other quadrant R (and, accordingly, the input information of the converted pixel position is converted to the specified V by an inverting circuit).

That's all for f! A will be specifically explained by showing examples.

Now, enlargement/reduction of the image by the above-mentioned IIfii density conversion
Based on the projection method (hereinafter simply referred to as high-speed projection method) K, only the case of expansion (equal expansion) in which the horizontal and vertical conversion magnifications p and q are 1 or more will be explained. Even in the case of reducing in both other directions, enlarging in one direction and reducing in the other direction, and in which case the m* flaw signal is binary, this can be achieved by simply modifying the device of the present invention. .

The Sat diagram shows the original iij bulk surfaces A, B, C, D, (■, ■, 0
．． 0. Ryo II! Ii Sober A, B, C, D
The figure shows a state in which the converted pixel R (@ indicates the center of the converted pixel) 1 is superimposed on, or projected onto, the converted pixel R (@ indicates the center of the converted pixel). From the relationship between the original image and the converted pixel in FIG. 1, the converted pixel center point ■ is within the plane consisting of A, B, C, and D of the original image. ■.

In order to calculate the rfiIg11 signal output of iji element 8 after conversion depending on where it exists in the square area surrounded by The original picture said Lun signal! A
, B, C, and D. A relational expression (consisting of logical expressions) is prepared in advance for calculation from the one-way signals (information) of B, C, and D. However, #! FIG. 2 shows an example of the X, Y coordinates of the square area surrounded by the squares (■, ■, ■, ■) divided into eight as described above. Here, ■, ■, ■ are X.

2nd quadrant, 3rd quadrant, 4th quadrant, ugliness on the Y coordinate respectively
It exists in the quadrant. Set the coordinates at 5 and divide it into the 8 sections mentioned above.■
Of the divided areas indicated by ■, the boundaries separating the divided areas ■ and ■, ■ and ■, ■ and ■, and ■ and ■, excluding the linear boundaries of It is determined by the curve shown by the equation (b) and r-L).

(Shi Oath - PX) (Shi Oath + (IF)”
Shi oath ... ... ... (a) (S4- px
) (shi1-qy)s:I shi(・・・・・・・・・
... (b) (i+pri (i9y); No....
... (c) (No. 10 pri (No. + qy) = No....
) According to the high-speed projection method, when the center point (■) of the converted pixel is located, for example, in the divided area (2), the image information signal lR of the converted pixel R is IRW IA (IB+IO+ID)+IB-IO- I
It is supposed to be given by the relational expression D.

(However, * means logical product, + means logical sum.)
Similarly, relational expressions such as the first surface force are shown for each of the eight divided regions K.

In Table 1, that is, in the high-speed projection method, the relational expressions listed in Table 1111 are stored in the preliminary storage means, and depending on where the converted pixel R is located, the 1-Run signal lR of the corresponding converted pixel is determined.
and original pixel 1 line signal (IA, Ill, IO.

The pixel signal I of the converted pixel is calculated based on the relational expression with
Get East.

Now, FIG. 3 shows an example in which the apparatus of the present invention is implemented.

Here, suppose that the original picture is made up of a matrix with W pixels in the width direction and T pixels in the vertical direction, and when converting one picture after conversion so that it is made up of a Wo X Lo pixel matrix, the main scanning direction (
The conversion magnifications in the X direction) and the sub-scanning direction (Y direction) are p=wo/w and 11 W LO/L, respectively.

Now, the storage section 311 in the input buffer section 31 of this device is divided into three RAMs (random access memories) 311A,
Consisting of 3LIB and 311C, 1 for selecting each RAM, for inputting and storing the Tanu signal and the Ganji image signal to the Isata RAM, for setting the address, for counting pixels in the main scanning and sub-scanning directions. Input counter 312, input i'y
', a counter 314, and an Akita counter 313 that provides timing for sequentially outputting the stored contents to a multiplexer 315.

Here, the input counter 312 and the read counter 313 are set to W at the start, and the input row counter jt4 is set to L.
At the same time, the output counter 33! is set to the force 1 kund value in the main scanning direction and the sub-scanning direction at the start of the pixel after conversion. and output line counter 332K
Set it as Wo and Lo.

Also, the output of clock signals to the input/output counters,
Timing generation circuit 3 that outputs other timing signals
30 to address multiplexer 315-'\(n cell signal (s,, s@) + ("()"-'
The ready signal (low active) indicating that the pixel density conversion device of the present invention may output the converted image signal to an external device is set to 101, and the output of the input enable terminal is set to 11. Set it to .

Furthermore, the latch A provided in the 1iii elementary position calculation section A
, 341 and latch 1%, 342 are X adders 343,
Before inputting the coordinate position output from the Y adder 344, it is cleared for a while and the output signal to the area determination unit 35 is set to (0
, 0).

Hereinafter, the operation of the circuit shown in Fig. 3 of the present invention for calculating the converted image output for the converted image iiig11 will be explained.

Here, the output from the input counter 312 is '%VAO-
11 and is input to the address multiplexers 3 to 6 as a write signal, and is also input to the timing generation circuit 330 as an input end signal for one line.

Further, the output from the read counter 313 is inputted to the address multiplexers 3 to 6 as Rm0-IJ.

RAM as storage means, attm, RAM8.31
1B.

RAMC, 311 (address multiplexer 3 for 4
Seven signals are outputted from 16 to signal cams 0-11 for address designation, and to signal cam W for selecting and designating the RAM to be written to and for writing timing. For example, a write strobe signal is input from the timing generation circuit 330 to the designated RAM fl W via the address multiplexer 316.

Furthermore, input data to each RAM is input to the DI terminal, and a signal is output from the DO terminal of each RAM 17' to the data multiplexer 315.

Now, in the initial state 11jJ, S, , So are IQI
, sQ lightning, RAM is data write, RA
MB and RAMC are set to K for no reading, and the other states of each RAM are 1st! ! It is specified as follows.

Table 2 f) Il (S, , S, ) is (1,1)! ! lI stop h-C
6゜Now, the input data is inputted 1iii elements at a time to each RAM, but W is input for each picture element.
The input counter 3!2 is activated by the CLK signal! Since the number decreases step by step, information for one line (Wij volume) is stored at one address from address W in RAMA. The ready signal becomes "!" (HLGH) when one pixel is inputted. When the input counter 312 becomes 0, an 1 line input end signal is generated, and the timing generation circuit detects this and presets the input counter 312 to WK while decrementing the input row counter 314 by 1. At the same time, K(
it-8o) will be connected to (0,1'') and 3118 K@.

After this, the ready signal becomes '0' (Low) K, 2
It becomes possible to input the W pixel in the row. The input data is RAM8.3118K at the same timing as the input on the first line.
input and stored.

Now, when the input data on the second line is input, the connection is established.

After this, the ready signal becomes IQI jc, and when the input data on the third row can be input, the K RAMA is activated at the same time.

311A and RAM8.3118K are stored.

Pixel density conversion processing is performed using the information in the first and second rows.

First, when (81+go) is (1,0), the output of read counter 3!3 is RAMA, 311A, and RAMII.
, 3111 K are connected, and each output terminal DO
The pixel information of the first row and the first column of the J142nd row are output as data output signals DA and DB, respectively.

The UID^ and DB flaw signals are output via the data multiplexer 315 as D1+D1 signals, respectively.

Here, the Ds and Dt are connected to the flip-flop F/F by a shift clock from the timing generation circuit 330.
L, F/F2 K-L, K at the same time as CH RCLK
Output a signal to subtract 1 from the value in the read counter 313, and output the second column pixel data from RAMA, 311A and RAMB, 311B.

After this, 7 more clocks are inserted into the flip-flop F/
Fl -F/F'4 Is the Vc ratio output the pixel data of the 1st column? Flip 70 knob F/F3. F/F4 K is transferred and latched, and 7 lip-flops F/Fl,
F/F2 is made to latch m* data in the second column. At this time, the reading output f) counter 313 decreases l. This is the first 4
Now that the pixel data of the points are complete, they are sequentially input to the pixel determination unit.

Here, the outputs DA, DB and DC from each RAM of the storage unit 3''1 and the outputs D8 and a of the data multiplexer 315
The relationship is as shown in Table 11112.

Table 1 to 3 (81, go) is sequentially (0
,1).

(1,0), (0,0), (0,l)...
・This is repeatedly output.

In this embodiment, the circuit shown in FIG. 4 is used as the address multiplexer 316 and the data multiplexer 315.

Now, when the second shift clock is output, the latch 341 and the latch l in the position calculation section A are activated.

Since the output of 342 is up to 00, the decimal part is originally KO.
It is. Therefore, in the area determination unit word, based on the Xd@c1mml signal and Yd@ciml signal from the pixel position calculation unit tone, when the decimal part of each input is (0,0), the determination area S [0,0, 1).

As mentioned above, the eight divided areas in the original pixel plane (square area consisting of four points at the center of the Jliii element) by the high-speed projection method are 3
It can be expressed in bits.

At the same time as the second shift clock, the timing generation circuit 330 outputs the latch A clock, and
Latch pit (o, o, t) with latch C, 351K. From the PC, data of Jjii in the area where the converted pixel in the first column is located and in the original pixel plane surrounding this pixel are simultaneously inputted to inputs iA, IB, IO, and IDK of the pixel determination unit Atsushi. Based on this, the converted ij pixel data is immediately output from the pixel determining unit, an output strobe is output from the timing generation circuit 330, and the value of the output counter 331 is decremented by one.

By the way, the operation in the pixel position calculation unit U is then performed by the latch A.
Latch A, 3 which was previously 0 due to clock output
41 Kl/ is output. (x adder 343,
In the initial state of the Y adder 344, the KA+B output is 0. ) The second conversion process differs depending on the value of the integer part of 1/.

1) When the integer part of '/ is O, the converted pixel of ta2 is still located between the first and second columns of the original pixels, so the shift clock, R
CLK signal is not output (that is, one original pixel data, IB
, IO, and ID do not change), only the latch A clock is output, and the converted pixel of m2 is determined.

If) When the integer part of l/p is 1, the second converted pixel is located between the second and third columns of the original image. Therefore, the original image is also shifted by 1 bit and the latch A clock is also output. Then, 12 converted pixels are determined.

1it) When the integer part of '/ is 2 or more (=Otori), then the second converted pixel exists in the third column or later of the original image.

So, after shifting the original picture by (n-1) bits, I shifted it further by 1 bit and at the same time turned on the latch? Output and determine the converted pixel @2.

Now, the adder 343 uses the decimal part of the output of latch A and
Since this is a circuit that adds /p, the integer part of the calculation result indicates how many pixels K must be shifted from the original image to the next converted pixel. Therefore, the converted pixels from the third column of llA onwards are also converted using the above algorithm.

The output counter counts down each time a converted pixel is output, so when the output counter reaches 0, it means that only the amount of pixels has been output. Therefore, an l line output end signal is output.

The timing generation circuit 330 is on the third line! When both the line human power end signal and the l line output end signal are input, the latch B clock is output to latch BK1/q, and at the same time, the output row counter is decremented by 1. The processing is different depending on the integer part of 1/0.1.2.

1) When the integer part to 1 is 0, the second line of the converted picture line is between the first and second lines of the original picture ◎Therefore, < S, * S, ) Output do.

H) When the integer part of 1/ is 1 The second line of Conversion 1 Lun is at the junction between the second and third lines of the original painting.

Therefore, (S, s,) is (0,0) K 1. te, RAM
B. Pixel density conversion processing is performed on the pixel information on the second and third lines in the RAMC.

l1l) The integer part of 1/ is 2 or more (s=m)
F) The second line of the time conversion picture is after the third line of the original picture. Therefore, (S+, So) is (0,0)−+(0,1)−
+(1, 0) → (0, 0) → . . . , and input one row each for a total of (m-1) rows. Then, when the ready signal goes low, the second line is converted at the same time as the first line is input.

When the input row counter reaches 0 while performing pixel density conversion using this method, there is no more information to input, but the input enable is set to Low K! until the output is completed. ,, As if the input signal becomes O, an output end signal is outputted from the timing generation circuit 330K.

The timing generation circuit 330 ends all processing when both the input end signal and the output end signal are input.

To describe the area determination unit 1'lK in more detail, i
Output from the position calculation part X d@eimml,
Y d@c1mml (decimal part) is as below, Xd@citnal = Xdl・(%) +Xd*
・(3A)”10−−−+Xdk・(H)kYd@e1m
ml = Ydl・(H) +Ydl・(H)”+ −
It is expressed in bits as −”・+Ydk−(M)k,
Here, the value of k represents the n degree of the coordinate, that is, the precision of the enlargement/reduction ratio. It is the number ζ to increase.

Therefore, in order to maintain high precision in enlarging/reducing and not increase memory capacity, the inventors took advantage of the fact that the divided areas (shown in Figure 2) are symmetrical about the X-axis and the X-axis, respectively. I configured the circuit as follows. ! R5 figure) is the divided area curve stored in the storage means 352 in the area determination unit word when the magnification is -6 and the magnification is p=q=os.

■～■ means the area number, and the 6 attached to the X and Y coordinate axes
A binary number of bits indicates a coordinate, and the leftmost bit of the Y-axis coordinate value is MSB, and the uppermost bit of the X-axis coordinate value is MOB.

Now, in the logical projection method, (Xdl, Ydl)0(0,0)
, (1,0).

As mentioned earlier, the four regions (0, 1) and (1, 1) are symmetrical with respect to the line that divides them, so for example, points in regions n, m, and rv are Projecting it onto a point on a symmetrical region I, it is possible to determine in which region the point is located in eight different regions depending on whether it is located in K or ■.

! With Figure I5 (a) (Xd@cimml + Yd@c
The symmetrical point on ■ of the point m (101100+000111) is (010011).

ooo t t t ). Therefore, if we know that this point belongs to ■, then (X4+Y4) W (t, o)
Using , we can see that it belongs to ■.

In practice, this can be achieved, for example, by a circuit configuration as shown in FIG. 45(b)K. In this circuit, the data in the memory 352, for example, corresponds to
01 wo, ■ [Just put 11- in the corresponding address.

For example, if the decimal part of the output of the X adder 343 and the X adder 344 is (101100,000111), and the area of
d! ~Xd, signal line Exelusl MA/OR game)
The inputs A4 to AOK of the memory 352A are inverted by K, and since Yd is 0, Yd, to Yd, are transmitted to the inputs A9 to M5 in their momme state. So the address (001L lt.

alt) Since the corresponding data corresponds to the area Il@, that is, the region ◯, 1=1 is output from the output DO.

Considering Xd, l Yd, l f as a set, [Xd
,,Yd,,f] is sent to the pixel determination section 32 via the rack q-C351.

Here, as a method to further reduce the memory capacity of the storage means required for the area determination circuit, in the X and Y coordinates where the divided area is set, the Y coordinate of the boundary line between ■ and ■ is memorized with respect to the X coordinate. Based on the magnitude relationship between the actual Y-coordinate and the Y-coordinate of the boundary line, it is possible to determine the area of the force/■, and compare the value of the Y-coordinate of the rough circuit point with the comparator 35.
3 and outputs a judgment output f.

The memory capacity of the storage means required for each of the above three configuration examples of the area determination section is (assuming the accuracy is 6). ×3c = 4096
)) is 21@-IXI
WH becomes 160 bits.

Table 3 K shows an example of the internal force data in Memo I7352 B (Figure 5 (C)) with the configuration of mackerel 3.

! [Table 4] Now, the 3-bit data of 0 (4-Ydt*') from the area determination section and the 4-bit output data from the input cover sofa section through four flip-flop circuits form a 5nt image.
This is input into the ty section. Specifically, this pixel determination unit uses the converted pixel values shown in Table 1! IA, IB, and IC from the Oita buffer section.
, ID manual power is included in a predetermined relational expression between E, III, IO, ID and lR corresponding to the 3-bit data from the area array section to obtain an lR ratio output. Table 4 shows the logical formula in the pixel determination section.

Table 5 FIG. 6 shows an example of the circuit configuration of the ii-me determination section that achieves the relational expressions shown in Table 5. 321 is a 3-person decoder with 8 outputs.

As explained above, it has become possible to provide a device that is very efficient and has a small memory capacity for enlarging and reducing m-densities by m-bulk density conversion, particularly by high-speed projection. Of course, when it comes to different configurations of the device, various modifications based on the above-mentioned embodiments can be easily made. ! J! It is something that can be done.

[Brief explanation of drawings]

The #EL diagram is a diagram showing the positional relationship of converted pixels in the original pixel plane used to explain the projection method, and Figure 2 shows the division state of the area formed on the original pixel element plane used in the projection method. This is a diagram. Figure 3 is an example of the implementation configuration of the present invention, and Figure 4 is an example of the configuration of the address and data multiplexer in Figure M3. 5.5(a) shows the state of the area division data stored in the storage means in the area determination unit, and FIG. 5(b) and 5.
Figure (el) shows an example of the configuration of the peripheral circuit of the storage means in the area determination unit. Figure 6 is an example of the circuit configuration of the pixel determination unit. 31... Input buffer unit 311... °°・
Storage parts 31tA, 311B, 311C...RA
M312...Input counter 313...
・Reading counter 314...Input line counter 315...Data multiplexer 316...
... Address multiplexer ℃ ... Pixel judgment section 330 ... Timing generation circuit A ...
...Pixel position calculation unit 341.342.351...Latch 343.3
44... Adder Song... Area Judgment Department Agent Yoshimi Kuwabara! II! 1 Figure 2 Figure 4 Figure 512] (b) Box Figure 5 (C)

Claims (1)

[Scope of Claims] (In a pixel density conversion device that performs image volume density conversion using the 11 projection method, a storage unit having storage means for storing TIIR-signals for at least two scanning lines; a pixel position calculation unit that calculates the pixel position after conversion within the pixel plane; a region determination unit that determines the region in which the center of the converted pixel calculated by the pixel position calculation unit is located; A pixel density conversion device having a pixel density determination unit that calculates a relational expression VC & of a yA-pixel pixel density signal preset for each region and a 1iiiI signal of a converted pixel. The first aspect of the present invention is a manual buffer section configured to memorize the input of the image pause signal, and to sequentially form the original pixel element surface every two scanning lines among the storage means for every three scanning lines. Pixel density conversion device as described in Section 3. (3) Original pixel plane formed by the image signal for the two scanning lines<m*K during the timing when the density conversion process is being performed, storage means for the scanning line. The pixel density conversion device according to claim 92, wherein the pixel density conversion device is configured to input and store the next original*suga information. 1l according to Claims B (1) to (3) comprising a logic circuit that outputs iiiIg11 based on the relational expression in the projection method and the area divided into eight parts;
iii Density conversion device. (5) Claims in which the area determining section includes a storage means for storing a code indicating the area! The pixel density conversion device described in Items 11111 to 4. (6) The area determining section includes a storage means that stores a curve indicating a boundary dividing an area in at least one quadrant of the original pixel plane into two, and a comparison circuit that uses data in the storage means as a reference human power. A pixel density conversion device according to claims #/41 to 114. (7) The area determination unit determines the value of two areas within a specific quadrant of the area based on the value of the decimal part of the converted im* position calculated by the pre-distribution bulk position shadow calculation unit. The invention further comprises means for region determination, and for other quadrants, the input information of the converted pixel position is determined by an inverting circuit by making it correspond to two regions within the specific quadrant. Section 5 or i or I [iii. The density conversion device described in Section 6.