JPS58148674A - Controller for pwm inverter - Google Patents

Abstract

PURPOSE:To improve the efficiency of a PWM inverter by comparing a pulse- width modulated input signal with a signal delayed from the input signal, removing only the pulse having the time width shorter than the prescribed value and controlling the inverter, thereby securing the minimum pulse width. CONSTITUTION:A DC power source 1 is inputted to an inverter 2 which employs GTO, thereby driving an induction motor 3. At this time, a PWM signal (a) obtained by comparing the triangular wave with a sinusoidal wave and a signal which is delayed for the prescribed time by a delay circuit 4 are inputted to an exclusive OR circuit 5, the output of which and the pulse from an edge detector 6 are inputted to an AND gate 8, the output of which is applied through a flip-flop 9 to a control circuit 10, thereby controlling the GTO in the inverter 2. Accordingly, the output signal does not contain the pulse width shorter than the minimum pulse width by adequately determining the delay time of the delay circuit 4, thereby operating in high efficiency.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a variable pulse width vI4 (hereinafter referred to as PWM) used for variable frequency control of an induction motor.
The present invention relates to an inverter control device.

[Technical background of the invention and its problems]

Gate turn-on thyristors (hereinafter referred to as GTOs) are widely used as PWM inverters, and recently, PWM inverters based on GTOs with increased capacity have begun to be used.

FIG. 1 shows the basic groove formation of a PWM inverter using GTO. It is configured to convert the DC voltage of ItgA1 into an OT variable voltage and an OJ variable wavenumber AC voltage by an inverter 2, and drive the induction motor 3t. usually,
When driving a three-phase induction four-motor.

Inverter 2&! 6 GTOUP, VP, WP.

It is composed of UN, VN, and WN, and the output voltage and frequency are t-controlled by controlling the gate voltage t-control of these GTOs. In controlling such a gate voltage, the minimum pulse width of the control voltage becomes a problem.

In other words, the minimum pulse width is set to 600 mm in consideration of the switching speed of the GTO or ensuring the discharging time of the snubber circuit.
When using GT(l) of A, it is necessary to ensure about 100 μsec.

Therefore, in the control circuit of the inverter 2, a gate interlock circuit t- is provided, and the pulse @ is necessarily configured to be greater than the gate interlock circuit t-.

On the other hand, the gc11 frequency requires about 400 hertz to 1 kilohertz, and if the modulation frequency is 1 kilohertz, the on-duty can only be taken up to 90 minutes.
The output voltage will become low.

The second figure shows a waveform diagram to show the principle of PWM. As shown in Section 2a(a), to perform full PWM, the sine wave and the triangular wave are compared and only the signal in the section where the sine wave voltage is at a higher level than the triangular wave voltage is extracted.

As a result, an output waveform as shown in FIG. 2(b) is obtained. However, even if the control circuit obtains a PWM signal as shown in Figure 2(b), the gate interlock widens the narrow pulse width to the minimum pulse width, so the actual PWM signal is It becomes as shown by fusing (e).

Therefore, the output voltage of the PWM inverter that is completely controlled by the PWM signal becomes small as shown by the dot-by-dot line in FIG. 2(e).

Generally, the operating efficiency of an induction motor deteriorates rapidly when the voltage is insufficient. As mentioned above, in order to effectively drive the GTO, it is necessary to ensure a minimum pulse width, but the structure is designed to avoid the drop in Narita as shown in Figure 2 (e). There is a need.

However, in the conventional PWM inverter control device,
Thinking like this lol! What I paid for didn't exist.

[Purpose of the invention]

An object of the present invention is to provide a PWM inverter control device that does not cause a drop in output voltage even when a minimum pulse width for GTO operation is ensured.

[Summary of the Invention] In order to achieve the above object t, the present invention provides a pulse delay circuit that delays a pulse width modulated input signal t by a predetermined time, and a pulse delay circuit that delays the input signal and the output signal of the pulse delay circuit. a pulse erasing circuit that compares and removes only pulses having a time width shorter than the predetermined time that are present in the input signal; and a control circuit that outputs a control signal to an inverter in response to an output of the pulse erasing circuit. It is characterized by having the following.

The present invention will be explained in detail below with reference to Examples.

[Embodiment of the Invention] FIG. 3 is a block i showing an embodiment of the invention. 4 is a delay circuit constituted by a shift register, 5 is an exclusive logic circuit, 6 is an edge detection circuit that outputs a one-shot pulse at the rise and fall of the output signal of the delay circuit 1, and 7 is a negative logic circuit. , 8 is an AND circuit, 9 is a D-flip-flop circuit, and ■()
is a control circuit. Next, the operation of this circuit will be explained.

One of the input terminals of the delay circuit 4 and the exclusive OR circuit 5 is connected to the PWM signal shown in FIG. A signal is given. This pwMm signal is output with a certain delay by the delay circuit 4. This is shown in Figure @4 (C).
This is the waveform of The output of the delay circuit 4 is connected to the other input terminal of the exclusive OR circuit 5, and the exclusive OR circuit 5 combines the original PWM signal and PWyr*q delayed by the delay circuit 4. To compare and output "0" if the two match, otherwise output "1".

The output of exclusive logic circuit 5 is inverted by negative logic circuit 7. The output signal of the negative logic (b) path 7 is shown in Fig. 4 (
Shown in d).

On the other hand, the edge detection circuit 6 generates a one-shot pulse as shown in FIG. 4(e) at each rise and fall of the output signal of the delay circuit 4.

The output of the edge detection circuit 6 and the output of the NOT logic circuit 4 are ANDed by an AND circuit 8, so that an output pulse as shown in FIG. 4(i) is obtained. The output of this AND circuit 8 is input to the clock terminal of the D-7 lip-flop 9, while the output of the delay circuit 4 is input to the D! Since the Q output of the D-7 flip-flop circuit 9 has a waveform as shown in FIG. 4(h).

The output signal of the D-7 flip-flop 9 obtained in this way is input to a control circuit 10, and this control circuit 10 controls the GTO in the PWM inverter.

That’s all iB! As is clear, PWM (c human power figure 4 (b)
Of these, pulses whose pulse width is shorter than the delay time of the delay circuit 4 do not appear in the output signal of the D-7 flip-flop circuit 9. In other words, the exclusive theory f! The A-sum (b) circuit 5, the edge detection circuit 6, the negative logic circuit 7, the AND circuit 8, and the D-7 lip-flop circuit 9 constitute a kind of pulse cancellation circuit, which delays the total time of the input knife signal. The input signal is compared with the original input signal, and only those pulses whose delay time has not changed are passed.

Therefore, if the delay circuit 4 delay time is combined with the minimum pulse width t supplied by the GTO switching time and snubber circuit discharge time, the output signal will not include pulses with a pulse width shorter than the minimum pulse width. .

In this way, prepare t-3 circuits shown in diagram wJ3,
Each of the three-phase PWM polarization signals is processed, and the Q output of the D-7 lip-flop 9 is used as a control signal for the GTO on the positive side of the inverter, and the Q output is given as a control signal for the GTO on the negative side of the inverter. If the control circuit lO is configured as follows, the control output signal t
ζ no longer includes pulses shorter than the minimum pulse width.

Also, unlike the conventional gate interlock method, the output voltage is increased in the opposite direction. However, short pulse #7
jB′t− Neglecting the pulse with harmonic molecule t
T! ! However, since the fundamental wave component of the output voltage increases by that amount, the operating efficiency of the induction motor does not deteriorate.

Also, as the operating frequency increases, the phase of the phase voltage decreases to 90
The pulse width becomes shorter from the part near °, that is, the part that has a large effect on the fundamental wave, until it reaches the minimum pulse width and disappears. However, the pulse that has a large effect on harmonic removal is
Since it does not disappear easily, the increase in the harmonic distribution is not rapid.

It should be noted that the configuration of the pulse erasing circuit in the embodiment shown in FIG.

[Effects of the Invention] As will not be explained in detail above, according to the present invention, a pulse erasing circuit that erases pulse signals of a certain width or less included in a PWM signal is provided, so that the restriction on the minimum pulse width can be overcome. There is an advantage that the induction motor can be operated with high efficiency even with a PWM inverter using a large GTO4.

Furthermore, an inverter using a transistor instead of a GTO can also be used when operating at a large current and a slow switching speed of the transistor, or at a very high frequency.

[Brief explanation of the drawing]

@1 Figure shows the basic configuration of a PWM inverter, @2
The figure is a waveform diagram for explaining the principle of conventional PWM control, FIG. 3 is a boot diagram showing an embodiment of the present invention, and FIG.
The figure shows a waveform diagram for explaining the operation of the embodiment shown in FIG. 3. 4...Delay circuit, 5--Exclusive OR circuit, 6-
・・Edge detection circuit, 7・Negation logic circuit, 8・-AND circuit, 9-D-flip prop circuit, 10・・
・Control circuit. Applicant's agent Kiyoshi Inomata

Claims (1)

[Claims] a pulse delay circuit that delays a pulse-width modulated input signal by a predetermined time; and a pulse delay circuit that compares the input signal with the output signal of the pulse delay (b) path to determine whether the input signal exists in the input signal for a period shorter than the predetermined time. 1. A control device for a PW inverter, comprising: a pulse erasing circuit that erases only pulses of a certain width; and a control circuit that outputs a control signal to an inverter in response to the output of the pulse erasing (b) path.