WO2012153368A1 - Grid-connected inverter device, and distributed power source system provided with grid-connected inverter device - Google Patents

Grid-connected inverter device, and distributed power source system provided with grid-connected inverter device Download PDF

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Publication number
WO2012153368A1
WO2012153368A1 PCT/JP2011/002606 JP2011002606W WO2012153368A1 WO 2012153368 A1 WO2012153368 A1 WO 2012153368A1 JP 2011002606 W JP2011002606 W JP 2011002606W WO 2012153368 A1 WO2012153368 A1 WO 2012153368A1
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Prior art keywords
switch
grid
bridge circuit
voltage
inverter device
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PCT/JP2011/002606
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French (fr)
Japanese (ja)
Inventor
敏一 大久保
叶田 玲彦
亨 仁木
Original Assignee
日立アプライアンス株式会社
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Application filed by 日立アプライアンス株式会社 filed Critical 日立アプライアンス株式会社
Priority to CN201180070774.6A priority Critical patent/CN103534924B/en
Priority to PCT/JP2011/002606 priority patent/WO2012153368A1/en
Priority to JP2013513826A priority patent/JP5646053B2/en
Publication of WO2012153368A1 publication Critical patent/WO2012153368A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0048Circuits or arrangements for reducing losses
    • H02M1/0054Transistor switching losses
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a grid-connected inverter device, and more particularly to a technique for reducing loss.
  • the system is provided with a grid-connected inverter device so that the power obtained from the above-mentioned energy source can be supplied to a commercial system.
  • a grid-connected inverter device with low loss is desired.
  • Patent Document 1 discloses a conventional technique for reducing the loss of an inverter device.
  • Patent Document 1 when the load current is detected and the polarity of the load voltage and the polarity of the load current are positive or negative, the two switch elements (Q1 and Q2 or A technique is described in which the on / off operation of Q3 and Q4) is prevented so as to reduce the loss due to the switching element on / off.
  • Patent Document 1 does not consider the influence of ripples included in the load current, that is, the output current of the single-phase bridge inverter circuit 1.
  • the grid-connected inverter device outputs pulsed power (hereinafter referred to as pulse power) from the bridge circuit, smoothes it with a filter circuit, and outputs it to the commercial system. For this reason, generally, the output current of the bridge circuit includes a ripple as shown in FIG.
  • the power factor of the grid-connected inverter device is 0.95 to 1.0, and there is almost no phase difference between the grid voltage and grid current. Therefore, for example, in a small current region near the zero cross of the system voltage, the output current of the bridge circuit is small, and the polarity of the output current may repeat a positive polarity and a negative polarity every switching cycle due to the ripple described above. That is, in a small current region near the zero cross, the polarity determination of the output current becomes unstable, and the switching operation of the bridge circuit may become unstable. In this case, for example, the system current may be distorted, or the loss due to ON / OFF of the switch element (hereinafter referred to as switching loss) may not be sufficiently reduced.
  • switching loss the loss due to ON / OFF of the switch element
  • an object of the present invention is to provide a grid-connected inverter device that realizes a stable switching operation in a small current region near the zero cross of the grid voltage and has a small loss.
  • the bridge circuit Consists of a plurality of switches
  • the control means controls the switches so that the distortion of the current flowing through the commercial system is suppressed from the period before the predetermined period until the predetermined period has elapsed with the zero cross point of the voltage of the commercial system as a base point. It has a mode 1 and a mode 2 in which the switch is controlled so as to reduce the loss of the switch in a period from the elapse of a predetermined period until the next predetermined period.
  • the bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and both ends of the DC power supply are connected to both ends of the first switch and the second switch connected in series.
  • the third switch and the fourth switch connected in series are connected to both ends of the fourth switch.
  • the connection point of the first switch and the second switch, and the connection point of the third switch and the fourth switch are connected to the filter circuit.
  • the filter circuit is connected to a commercial system, and the control means is configured to perform a quotient in a period from a predetermined period before a predetermined period with a zero cross point of the commercial system voltage as a base point.
  • the control means is configured to perform a quotient in a period from a predetermined period before a predetermined period with a zero cross point of the commercial system voltage as a base point.
  • the grid interconnection has a bridge circuit, a filter circuit, and a control means for controlling the bridge circuit, and supplies power obtained from a DC power source to a commercial system through the bridge circuit and the filter circuit in this order.
  • the bridge circuit is composed of a plurality of switches, and the control means suppresses distortion of the current flowing through the commercial system from the period before the predetermined period until the predetermined period elapses with the zero cross point of the commercial system voltage as a base point.
  • a stable switching operation can be realized in a small current region, and a grid-connected inverter device with little loss can be provided.
  • the bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and both ends of the DC power supply are connected in series to the first switch and the second switch. Are connected to both ends of the first switch, the third switch and the fourth switch connected in series, the connection point of the first switch and the second switch, and the third switch and the fourth switch.
  • connection point is connected to the filter circuit, the filter circuit is connected to the commercial system, and the control means is based on the zero crossing point of the voltage of the commercial system from before the predetermined period until after the predetermined period has elapsed.
  • the first switch is turned on and the second switch is turned off and the third and fourth switches are complementary PWM.
  • the voltage of the commercial system is negative, In the mode 1 in which the third switch is turned on and the fourth switch is turned off and the first and second switches are complementary PWM, and the voltage of the commercial system is in the period from the elapse of a predetermined period to the next predetermined period.
  • the fourth switch When positive, the first switch is turned on, the second switch and the third switch are turned off, and the fourth switch is PWMed. When the commercial system voltage is negative, the third switch is turned on. In addition, by having the fourth switch and the mode 2 in which the first switch is turned off and the second switch is PWM, a stable switching operation is realized in a small current region near the zero cross of the system voltage. It is possible to provide a low loss interconnection inverter device.
  • a bridge circuit in which both ends of the first switch and the second switch connected in series, and both ends of the third switch and the fourth switch connected in series are connected to both ends of the DC power supply.
  • the first and third switches are composed of IGBTs and diodes to reduce conduction loss
  • the second and fourth switches are composed of MOSFETs and diodes to enable high-speed switching and reduce switching loss. Can be made.
  • FIG. 1 is a voltage / current waveform diagram when the operation mode switching means 120 is not used (operation waveform based on a PWM signal in mode 2).
  • FIG. 1 is a voltage-current waveform diagram when the operation mode switching means 120 is not used (operation waveform by a PWM signal in mode 1).
  • FIG. 2 is a voltage / current waveform diagram when the operation mode switching means 120 is used in FIG. 1.
  • FIG. 1 is a voltage / current waveform diagram when the operation mode switching means 120 is used (when the output current is larger than that in FIG. 7).
  • FIG. 11 is a detailed diagram of the switching operation of FIG. 10.
  • FIG. 1 is a circuit configuration diagram of a single-phase grid-connected inverter device 1 according to a first embodiment of the present invention.
  • the main circuit of the single-phase grid-connected inverter device 1 will be described.
  • a bypass capacitor 60 Connected to both ends of the DC power supply 10 are a bypass capacitor 60, a series connection body of the switching elements 20 and 21, and a series connection body of the switching elements 22 and 23.
  • Free wheel diodes 40 to 43 are connected in parallel to the switching elements 20 to 23, respectively.
  • a series connection body of an inductor 70, a capacitor 61, and an inductor 71 is connected between the connection point of the switching elements 20 and 21 and the connection point of the switching elements 22 and 23. Both ends of the capacitor 61 are connected to the commercial system 80.
  • IGBTs are used for the switching elements 20 and 22.
  • MOSFETs are used for the switching elements 21 and 23.
  • the switching element 20 and the diode 40, the switching element 21 and the diode 41, the switching element 22 and the diode 42, the switching element 23 and the diode 43 described above are respectively the first switch, the second switch, the third switch, and the fourth switch. Configure the switch.
  • the bypass capacitor 60 and the first to fourth switches constitute a single-phase bridge circuit that converts DC power output from the DC power supply 10 into AC pulsed power.
  • the output terminal of the single-phase bridge circuit is a connection point between the first switch and the second switch and a connection point between the third switch and the fourth switch.
  • the inductor 70, the capacitor 61, and the inductor 71 constitute a filter circuit that smoothes the AC pulse power output from the single-phase bridge circuit and outputs it to the system.
  • the input ends of the filter circuit are both ends of a series connection body composed of an inductor 70, a capacitor 61, and an inductor 71, and the output ends are both ends of the capacitor 61.
  • the single-phase grid-connected inverter device 1 is provided with a control means 100 for controlling the main circuit described above.
  • the control means 100 will be described.
  • voltage detection means 102 is connected to both ends of the bypass capacitor 60
  • voltage detection means 104 is connected to both ends of the capacitor 61 in order to detect the voltage on the output side. Is connected.
  • the voltage detection means 102 and 104 are connected to the grid connection control means 108.
  • a current sensor 90 is inserted on the positive electrode side of the DC power supply 10 to detect the current on the input side, and the switching elements 20 and 21 on the output side of the single-phase bridge circuit to detect the current on the output side.
  • a current sensor 91 is inserted between the connection point and the inductor 70.
  • the current sensor 90 and the current sensor 91 are connected to the current detection unit 101 and the current detection unit 103, respectively.
  • the current detection unit 101 and the current detection unit 103 are connected to the grid connection control unit 108.
  • PWM generation means 106 and 107 are connected to the grid interconnection control means 108.
  • the PWM generation unit 106 is connected to the switching unit 109 and the ripple detection unit 111.
  • the PWM generation unit 107 is connected to the switching unit 109.
  • the switching unit 109 is connected to the drive unit 105.
  • the drive means 105 is connected to the gates of the switching elements 20-23.
  • the voltage detection means 102 and 104 are connected to the ripple detection means 111.
  • the current detection unit 103 and the ripple detection unit 111 are connected to the comparison unit 110.
  • the comparison unit 110 is connected to the switching unit 109.
  • the control means 100 performs the following control so that the single-phase system interconnection inverter device 1 outputs desired power to the commercial system 80.
  • the grid connection control means 108 detects the voltage and current on the input side and output side from the voltage detection means 102 and 104 and the current detection means 101 and 103, and flows through the system voltage Vac of the commercial system 80 and the commercial system 80.
  • the modulation factor is calculated so that the current Iac has the same phase (power factor 0.95 to 1.0), and is output to the PWM generators 106 and 107.
  • PWM generation means 106 and 107 generate a PWM signal for switching the switching elements 20 to 23 by comparing the modulation factor output from the grid connection control means 108 with the carrier signal, and via the switching means 109.
  • the drive means 105 amplifies the PWM signal output from the PWM generation means 106 or 107 and drives the gates of the switching elements 20-23.
  • the switching unit 109 and the comparison unit 110 described above constitute an operation mode switching unit 120.
  • the operation mode switching unit 120 has a function of transmitting either the PWM generation unit 106 or the PWM signal generated by the PWM generation unit 107 to the drive unit 105 based on a method described later.
  • the operation mode switching means 120 and the ripple detection means 111 are means related to the present invention.
  • FIG. 2 shows operation waveforms when the switching elements 20 to 23 are switched by the PWM signal generated by the PWM generation means 106 (hereinafter referred to as mode 1) without using the operation mode switching means 120 in FIG. .
  • Vac is the voltage of the commercial system 80 (hereinafter referred to as system voltage).
  • Ii is an output current of the single-phase bridge circuit (Ii is a waveform in which a sine wave is superimposed on the second triangular wave from the top in FIG. 2).
  • Ii (ave) is an average current of Ii, which is substantially equal to the system current Iac, which is a current smoothed by the filter circuit.
  • Vg (20) to Vg (23) are gate drive voltages of the switching elements 20 to 23.
  • Vg (20) When Vac is a positive half cycle, Vg (20) is continuously turned on and Vg (21) is continuously turned off. Vg (22) and Vg (23) are alternately turned on / off (hereinafter referred to as complementary PWM).
  • Vg (20) and Vg (21) When Vac is a negative half cycle, Vg (20) and Vg (21) perform complementary PWM. Vg (22) is continuously turned on, and Vg (23) is continuously turned off.
  • the period (A) is a period in which the system voltage Vac is positive and the output current Ii of the single-phase bridge circuit is positive.
  • Periods (B) and (F) are periods in which Vac is positive and the upper limit of Ii is positive and the lower limit of Ii is negative due to ripple.
  • the difference between the periods (B) and (F) is only the difference in whether the average current Ii (ave) of Ii increases or decreases over time, and there is no difference related to the switching operation of the single-phase bridge circuit.
  • the period (D) is a period in which Vac is negative and Ii is negative.
  • Periods (C) and (E) are periods in which Vac is negative and the upper limit of Ii is positive and the lower limit of Ii is negative due to ripple.
  • the difference between the periods (C) and (E) is only the difference in whether the average current Ii (ave) of Ii increases or decreases over time, and there is no difference related to the switching operation of the single-phase bridge circuit. .
  • t1 is the time when the output current Ii> 0 and Ii starts to transition from rising to falling
  • t3 is the time when the output current Ii ⁇ 0 and Ii starts to transition from falling to rising
  • t1 ′ is the time when the output current Ii ⁇ 0 and Ii starts to transition from falling to rising.
  • t3 ′ is the time when the output current Ii> 0 and Ii starts to transition from rising to falling
  • the switching elements 20 to 23 are switched by the mode 1 PWM signal without using the operation mode switching means 120 and the ripple detection means 111 in FIG. 1, the switching elements (period ( Since the switching element 22 in A) and the switching element 20) in the period (D) are switched, an extra switching loss occurs.
  • the operation waveforms when the switching elements 20 to 23 are switched by the PWM signal generated by the PWM generation means 107 (hereinafter referred to as mode 2) without using the operation mode switching means 120 and the ripple detection means 111.
  • mode 2 the operation waveforms when the switching elements 20 to 23 are switched by the PWM signal generated by the PWM generation means 107 (hereinafter referred to as mode 2) without using the operation mode switching means 120 and the ripple detection means 111.
  • Vg (20) When Vac is a positive half cycle, Vg (20) is continuously turned on, and Vg (21) and Vg (22) are continuously turned off. Then, Vg (23) is turned on / off (hereinafter referred to as PWM).
  • Vg (22) When Vac is a negative half cycle, Vg (22) is continuously turned on, and Vg (20) and Vg (23) are continuously turned off.
  • Vg (21) is PWMed. In this way, FIG. 5 does not perform complementary PWM performed between Vg (20) and Vg (21) and between Vg (22) and Vg (23) as compared with FIG. 2, but Vg (21) or Vg ( 23) is PWMed.
  • FIG. 5 Since no current flows through the switching element 22 during the period (A) and through the switching element 20 during the period (D), the output current Ii of the single-phase bridge circuit is as shown in FIG. It is the same. However, in the periods (B), (C), (E), and (F), distortion as shown in FIG. 5 may occur in Ii. This is because the current on the negative side of Ii shown in FIG. 2 cannot flow through the switching element 22 during the periods (B) and (F), and Ii is on the positive side. The cause is an increase. Similarly, in the periods (C) and (E), since the switching element 20 is turned off, the current on the positive side of Ii shown in FIG. 2 cannot flow to the switching element 20, and Ii is on the negative side. The cause is an increase. On the other hand, however, FIG. 5 has the effect that the switching frequency of the switching elements 20 and 22 is small and the switching loss is small compared to FIG.
  • FIG. 6 shows operation waveforms when the operation mode switching means 120 and the ripple detection means 111 are used in FIG.
  • the operation mode switching means 120 discriminates the above-described periods (A) to (F), and in the periods (A) and (D), the PWM generation means 107 and the switching means are transmitted so as to transmit the mode 2 PWM signal to the drive means 105.
  • 109 and the drive means 105 are connected, and in the periods (B), (C), (E), and (F), the PWM generation means 106, the switching means 109, and the drive are transmitted so that the mode 1 PWM signal is transmitted to the drive means 105.
  • the means 105 is connected.
  • the operation mode switching means 120 compares the amplitude value
  • the ripple detecting means 111 a method of detecting the Ir by the ripple detecting means 111 will be described.
  • the voltage Vpn of the DC power supply 10 is output to the output terminal of the single-phase bridge circuit,
  • the voltage is applied to the inductor 70, the capacitor 61, and the inductor 71 that constitute the filter circuit.
  • a voltage obtained by subtracting Vac from Vpn is applied to the inductors 70 and 71, and the current of the inductors 70 and 71, that is, the output current Ii of the single-phase bridge circuit increases.
  • Half of the increased current value corresponds to the ripple amplitude Ir.
  • Ir can be obtained from the calculation based on Vpn, the ON time of the switching element 23 (the ON time of the switching element 21 when Vac is negative), Vac, and the combined inductance of the inductors 70 and 71. . Therefore, the ripple detection means 111 receives Vpn from the voltage detection means 102, the ON time of the switching elements 21 and 23 from the PWM generation means 106, and the system voltage Vac from the voltage detection means 104, and those values and stored inductors. Ir is calculated based on the combined inductance of 70 and 71. This calculation is performed each time the switching element 21 or 23 is switched, and Ir is updated. The ripple detection unit 111 holds and outputs Ir before being updated while Ir is updated.
  • the ripple amplitude value Ir can be detected by other methods.
  • An example is shown in FIG. In FIG. 7, a ripple detection unit 112 is provided instead of the ripple detection unit 111 in FIG.
  • the current detection means 103 is connected to the input of the ripple detection means 112, and the comparison means 110 is connected to the output.
  • the ripple detection means 112 includes a high-pass filter that cuts off the frequency of a commercial system (50 Hz or 60 Hz) and a gun-line detection circuit.
  • the arc detection circuit is a circuit that extracts only the arc line when there is target information in the arc line in the time series of the electrical signal.
  • the frequency of the commercial system is first cut by the above-described high-pass filter, so that only a ripple component is obtained.
  • this signal is input to the arcuate line detection circuit, only the arcuate line of the ripple component is extracted, that is, only the Ir amplitude value as shown in FIG. 6 is output. Further, Ir can be obtained by other methods and is not limited to the present embodiment.
  • the ripple amplitude value Ir obtained in this way is not a constant value but takes a maximum value in the middle of the system voltage Vac from zero to peak or from peak to zero.
  • the comparison unit 110 receives the amplitude value
  • the switching unit 109 connects the PWM generation unit 107, the switching unit 109, and the drive unit 105 so that the mode 2 PWM signal is transmitted to the drive unit 105 when the output of the comparison unit 110 is Low, and the output of the comparison unit 110 is High.
  • the PWM generation means 106, the switching means 109, and the drive means 105 are connected so as to transmit the PWM signal of mode 1 to the drive means 105.
  • the switching elements 20 to 23 are switched by the mode 1 complementary PWM signal.
  • the switching elements 20 to 23 are switched by the PWM signal of mode 2 that has a smaller number of switching times than mode 1, and the switching loss can be reduced.
  • FIG. 8 shows an operation waveform when the system current Iac is increased as compared with FIG.
  • the ripple amplitude value Ir of the single-phase bridge circuit is determined from Vpn, the ON time of the switching elements 21 and 23, Vac, and the combined inductance of the inductors 70 and 71, and is independent of the system current Iac. Therefore, the amplitude value Ir of the ripple is the same value as in FIG.
  • the mode in the period in which the amplitude value of the ripple is larger than the average output current amplitude value of the single-phase bridge circuit, centering on the zero cross of the system voltage, the mode operates within the period, and the outside of the period Then, it operates in mode 2.
  • the period changes in inverse proportion to the magnitude of the output current.
  • the operation mode switching means 120 by using the operation mode switching means 120 according to the present invention, the distortion of the system current near the zero cross of the system voltage is suppressed, and the switching frequency of the switching element is reduced to reduce the switching loss. Can be reduced. As a result, it is possible to obtain the effect of providing a single-phase grid-connected inverter device with little loss.
  • the switching elements 20 and 22 are IGBTs
  • the switching elements 21 and 23 are MOSFETs.
  • IGBTs or MOSFETs may be used for all switching elements, and the present invention is not limited to this embodiment.
  • FIG. 9 is a configuration diagram of the single-phase grid-connected inverter device 2 according to the second embodiment of the present invention.
  • the same components as those in FIG. 9 are identical to FIG. 9, the same components as those in FIG.
  • Switching elements 30 to 33 are connected in parallel to the switching elements 20 to 23, respectively. That is, in this embodiment, the switching element 20, the diode 40 and the switching element 30, the switching element 21 and the diode 41 and switching element 31, the switching element 22 and the diode 42 and switching element 32, the switching element 23 and the diode 43 and the switching element 33. Respectively constitute a first switch, a second switch, a third switch, and a fourth switch.
  • the gates of the switching elements 30 to 33 are connected to the control means 200.
  • the control unit 200 has all the functions of the control unit 100 described in the first embodiment and also has a function of driving the gates of the switching elements 30 to 33.
  • MOSFETs are used for the switching elements 30 and 32.
  • the switching elements 31 and 33 are IGBTs. In the present embodiment, the loss can be further reduced as compared with the first embodiment by including the switching elements 30 to 33.
  • Vg (30) and Vg (32) are gate drive voltages of the switching elements 30 and 32, respectively.
  • the switching element 30 switches during the periods (C) and (E).
  • the switching element 32 switches during the periods (B) and (F). That is, the switching elements 30 and 32 are switched when the single-phase system interconnection inverter device 2 is in the mode 1.
  • Vg (31) and Vg (33) are gate drive voltages of the switching elements 31 and 33, respectively.
  • the switching elements 31 and 33 are driven by substantially the same signals as the switching elements 21 and 23, respectively, but there is a slight difference in the turn-off time.
  • Ic (31) is a current between the collector and the emitter of the switching element 31.
  • Id (21) is the current between the drain and source of the switching element 21.
  • the control unit 200 turns off the gate of the switching element 31 before the switching element 21.
  • Ic (31) decreases and Id (21) increases.
  • Id (21) is a current obtained by adding Ic (31) before time t1 ′′. Since the switching element 21 is on during this time t1 ′′ to t2 ′′, the collector-emitter of the switching element 31 In the meantime, the ON voltage of the switching element 21 is applied. Generally, this ON voltage is about several volts, so that almost no switching loss occurs when the switching element 31 is OFF.
  • the switching element 21 21 gate is turned off.
  • Id (21) decreases to zero, and switching loss occurs in the switching element 21. Since the switching element 21 in the present embodiment uses a MOSFET as in the first embodiment, the switching loss of the switching element 21 occurring between the times t3 ′′ and t4 ′′ is the same as in the first embodiment. is there.
  • the addition of the switching element 31 can reduce the conduction loss of the switching element 21, and the loss of the second switch composed of the switching elements 21 and 31 and the diode 41 can be reduced to the embodiment. 1 can be reduced.
  • the control unit 200 may be provided with an oscillator that emits a pulse having a time of about 10 nsec to 1 usec, and the time of the pulse may be used to set the time from t1 ′′ to t3 ′′.
  • the time necessary and sufficient for the switching element 31 to turn off is proportional to the current value that has flowed through the switching element 31 before time t1 ′′, so that the current that has flowed through the switching element 31, that is, the output of the single-phase bridge circuit. It is desirable to change the pulse width emitted by the oscillator described above in proportion to the current Ii.
  • control means 200 is provided with a current detection means for detecting the current between the collector and the emitter of the switching element 31, and this current detection means detects the time when the current of the switching element 31 becomes zero and turns off the switching element 21.
  • this current detection means detects the time when the current of the switching element 31 becomes zero and turns off the switching element 21.
  • the switching elements 21 and 31 are turned on at the same time. In general, however, there is no significant difference in the turn-on speed between the IGBT and the MOSFET, so whichever is turned on first. Also good.
  • the switching operation of the switching elements 23 and 33 is performed by changing Vg (21), Vg (31), Ic (21), and Id (31) in FIG. 11 to Vg (23), Vg (33), and Ic ( 23) and Id (33), and the description thereof is omitted.
  • the switching element 33 By adding the switching element 33, the conduction loss of the switching element 23 can be reduced, and the loss of the fourth switch composed of the switching elements 23 and 33 and the diode 43 can be reduced.
  • the switching element 30 switches only in the periods (C) and (E), and the switching element 32 switches only in the periods (B) and (F).
  • Vg (22) in FIG. 3 is read as Vg (32).
  • Vg (20) in FIG. 4 is read as Vg (30).
  • switching element 22 ⁇ inductor 71 ⁇ capacitor 61 ⁇ inductor 70 ⁇ path of diode 40 and switching element 30 Current flows. That is, since the switching element 30 is a MOSFET, a current can flow from the source to the drain. Thereby, the current flowing through the diode 40 is reduced, and the loss of the first switch constituted by the switching elements 20 and 30 and the diode 40 can be reduced.
  • this embodiment can further reduce the loss compared to the first embodiment by including the switching elements 30 to 33.
  • the switching elements 31 and 33 reduce the loss of the switching elements 21 and 23 that switch in a large current region (periods (A) and (D) in FIG. 10), and the effect of reducing the loss is great.
  • FIG. 12 is a configuration diagram of a distributed power supply system according to a third embodiment of the present invention.
  • Reference numeral 300 denotes a distributed power supply system.
  • Reference numeral 301 denotes the single-phase grid-connected inverter device 1 shown in the first embodiment or the single-phase grid-connected inverter device 2 shown in the second embodiment.
  • 11 is a solar cell panel.
  • the solar cell panel 11 corresponds to the DC power source 10 in Examples 1 and 2.
  • 11 is not limited to a solar cell panel, but may be any DC voltage source.
  • the AC output of a fuel cell or wind power generator may be rectified to DC.
  • the distributed power system 300 includes the single-phase grid-connected inverter device 1 described in the first embodiment or the single-phase grid-connected inverter device 2 described in the second embodiment, the power loss is higher than that of the conventional distributed power system. There is little heat generation. For this reason, a heatsink and a cooling fan can be made smaller than before, and a compact and low-loss distributed power supply system can be obtained.
  • each of the above-described configurations, functions, and the like may be realized in hardware by designing a part or all of them, for example, with an integrated circuit.
  • each of the above-described configurations, functions, and the like may be realized by software by a processor interpreting and executing a program that realizes each function.
  • Information on the program that realizes each function can be stored in a recording device such as a memory, a hard disk, or an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
  • control lines and information lines indicate what is considered necessary for the explanation, and not all control lines and information lines on the product are necessarily shown. In practice, it can be considered that almost all the components are connected to each other.

Abstract

Provided is a grid-connected inverter device that achieves a stable switching operation in a low-current region in the vicinity of the zero-crossing point of grid voltage, and has low loss. The grid-connected inverter device has a bridge circuit, a filter circuit, and a control means that controls the bridge circuit, and the grid-connected inverter device is for supplying power obtained from a DC power source to a commercial power grid via the bridge circuit and the filter circuit in the given sequence. The bridge circuit comprises a plurality of switches, and the control means has: a mode (1) for controlling the switches in a manner so that distortion is suppressed of the current flowing through the commercial power grid during the time period that, with the zero-crossing point of the voltage of the commercial power grid as the origin, is from a predetermined period beforehand to after a predetermined period has elapsed; and a mode (2) for controlling the switches in a manner so that loss in the switches is decreased during the time period that is from after the predetermined period has elapsed to the next predetermined period beforehand.

Description

系統連系インバータ装置、および系統連系インバータ装置を備えた分散型電源システムGrid-connected inverter device and distributed power supply system including grid-connected inverter device
 本発明は、系統連系インバータ装置に関し、特に損失を低減する技術に関する。 The present invention relates to a grid-connected inverter device, and more particularly to a technique for reducing loss.
 近年、地球温暖化防止のため、燃料電池・太陽光・風力などをエネルギー源とした分散型電源システムが普及してきている。一般に、前記システムには前述したエネルギー源から得た電力を商用系統に供給できるようにするために系統連系インバータ装置が具備される。エネルギーの有効利用やシステムの小型化を促進するため、損失の少ない系統連系インバータ装置が望まれている。 Recently, in order to prevent global warming, distributed power systems using fuel cells, solar power, wind power, etc. as energy sources have become widespread. Generally, the system is provided with a grid-connected inverter device so that the power obtained from the above-mentioned energy source can be supplied to a commercial system. In order to promote effective use of energy and downsizing of the system, a grid-connected inverter device with low loss is desired.
 一方、インバータ装置の損失を低減する従来技術が特許文献1に開示されている。 On the other hand, Patent Document 1 discloses a conventional technique for reducing the loss of an inverter device.
特公平7-8145号公報Japanese Patent Publication No. 7-8145
 特許文献1には、負荷電流を検出して、負荷電圧の極性と負荷電流の極性とが正極同士または負極同士の場合に、単相ブリッジインバータ回路1の2個のスイッチ素子(Q1とQ2またはQ3とQ4)のオン・オフ動作をさせないようにして、スイッチ素子オン・オフによる損失を低減する技術が記載されている。しかし特許文献1では、負荷電流即ち単相ブリッジインバータ回路1の出力電流に含まれるリップルの影響は考慮されていない。 In Patent Document 1, when the load current is detected and the polarity of the load voltage and the polarity of the load current are positive or negative, the two switch elements (Q1 and Q2 or A technique is described in which the on / off operation of Q3 and Q4) is prevented so as to reduce the loss due to the switching element on / off. However, Patent Document 1 does not consider the influence of ripples included in the load current, that is, the output current of the single-phase bridge inverter circuit 1.
 ここで系統連系インバータ装置の概要に触れる。系統連系インバータ装置はブリッジ回路からパルス状の電力(以下、パルス電力と称す)を出力し、それをフィルタ回路で平滑して商用系統に出力する。このため、一般にブリッジ回路の出力電流は図13に示すようなリップルを含む。 Here, we will give an overview of the grid-connected inverter device. The grid-connected inverter device outputs pulsed power (hereinafter referred to as pulse power) from the bridge circuit, smoothes it with a filter circuit, and outputs it to the commercial system. For this reason, generally, the output current of the bridge circuit includes a ripple as shown in FIG.
 次に、系統連系インバータ装置に前述の特許文献1の技術を適用した場合を考える。一般に系統連系インバータ装置の力率は0.95~1.0であり、系統電圧と系統電流間の位相差は殆どない。従って、例えば、系統電圧のゼロクロス付近の小電流領域では、ブリッジ回路の出力電流が小さく、前述したリップルが原因でその出力電流の極性がスイッチング周期毎に正極と負極を繰り返す場合がある。つまり、ゼロクロス付近の小電流領域では、出力電流の極性判別が不安定になり、ブリッジ回路のスイッチング動作が不安定になる場合がある。この場合、例えば、系統電流に歪みを生じたり、スイッチ素子のオン・オフによる損失(以下、スイッチング損失と称す)を十分に低減できない等の恐れがある。 Next, consider the case where the technology of the above-mentioned Patent Document 1 is applied to the grid interconnection inverter device. In general, the power factor of the grid-connected inverter device is 0.95 to 1.0, and there is almost no phase difference between the grid voltage and grid current. Therefore, for example, in a small current region near the zero cross of the system voltage, the output current of the bridge circuit is small, and the polarity of the output current may repeat a positive polarity and a negative polarity every switching cycle due to the ripple described above. That is, in a small current region near the zero cross, the polarity determination of the output current becomes unstable, and the switching operation of the bridge circuit may become unstable. In this case, for example, the system current may be distorted, or the loss due to ON / OFF of the switch element (hereinafter referred to as switching loss) may not be sufficiently reduced.
 そこで、本発明の目的は、系統電圧のゼロクロス付近の小電流領域において安定なスイッチング動作を実現し、損失の少ない系統連系インバータ装置を提供することである。 Therefore, an object of the present invention is to provide a grid-connected inverter device that realizes a stable switching operation in a small current region near the zero cross of the grid voltage and has a small loss.
 ブリッジ回路とフィルタ回路とブリッジ回路を制御する制御手段とを有し、直流電源から得た電力をブリッジ回路,フィルタ回路の順に介して商用系統に供給するための系統連系インバータ装置において、ブリッジ回路は複数のスイッチからなり、制御手段は、商用系統の電圧のゼロクロス点を基点として所定の期間前から所定期間経過後までの期間で商用系統を流れる電流の歪みが抑えられるようにスイッチを制御するモード1と、所定期間経過後から次の所定期間前までの期間でスイッチの損失を低減するようにスイッチを制御するモード2とを有することを特徴とする。 In a grid-connected inverter device having a bridge circuit, a filter circuit, and a control means for controlling the bridge circuit, and supplying power obtained from a DC power source to a commercial system through the bridge circuit and the filter circuit in this order, the bridge circuit Consists of a plurality of switches, and the control means controls the switches so that the distortion of the current flowing through the commercial system is suppressed from the period before the predetermined period until the predetermined period has elapsed with the zero cross point of the voltage of the commercial system as a base point. It has a mode 1 and a mode 2 in which the switch is controlled so as to reduce the loss of the switch in a period from the elapse of a predetermined period until the next predetermined period.
 あるいは、ブリッジ回路とフィルタ回路とブリッジ回路を制御する制御手段とを有し、直流電源から得た電力をブリッジ回路,フィルタ回路の順に介して商用系統に供給するための系統連系インバータ装置において、ブリッジ回路は、第1のスイッチと第2のスイッチと第3のスイッチと第4のスイッチとからなり、直流電源の両端は、直列接続された第1のスイッチと第2のスイッチの両端と、直列接続された第3のスイッチと第4のスイッチの両端とに接続され、第1のスイッチと第2のスイッチの接続点と、第3のスイッチと第4のスイッチの接続点はフィルタ回路に接続され、フィルタ回路は商用系統に接続され、制御手段は、商用系統の電圧のゼロクロス点を基点として所定の期間前から所定期間経過後までの期間において、商用系統の電圧が正のときに、第1のスイッチをオンすると共に第2のスイッチをオフかつ第3と第4のスイッチを相補PWMし、商用系統の電圧が負のときに、第3のスイッチをオンすると共に第4のスイッチをオフかつ第1と第2のスイッチを相補PWMするモード1と、所定期間経過後から次の所定期間前までの期間において、商用系統の電圧が正のときに、第1のスイッチをオンすると共に第2のスイッチと第3のスイッチをオフかつ第4のスイッチをPWMし、商用系統の電圧が負のときに、第3のスイッチをオンすると共に第4のスイッチと第1のスイッチをオフかつ第2のスイッチをPWMするモード2とを有することを特徴とする。 Alternatively, in a grid-connected inverter device that has a bridge circuit, a filter circuit, and a control means for controlling the bridge circuit, and supplies power obtained from a DC power source to the commercial system through the bridge circuit and the filter circuit in this order, The bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and both ends of the DC power supply are connected to both ends of the first switch and the second switch connected in series. The third switch and the fourth switch connected in series are connected to both ends of the fourth switch. The connection point of the first switch and the second switch, and the connection point of the third switch and the fourth switch are connected to the filter circuit. The filter circuit is connected to a commercial system, and the control means is configured to perform a quotient in a period from a predetermined period before a predetermined period with a zero cross point of the commercial system voltage as a base point. When the system voltage is positive, the first switch is turned on, the second switch is turned off, and the third and fourth switches are complementary PWM. When the commercial system voltage is negative, the third switch Mode 1 in which the fourth switch is turned off and the first and second switches are complemented PWM, and when the voltage of the commercial system is positive during the period from the elapse of a predetermined period to the next predetermined period The first switch is turned on, the second switch and the third switch are turned off, and the fourth switch is PWMed. When the commercial system voltage is negative, the third switch is turned on and the fourth switch is turned on. And a mode 2 in which the first switch is turned off and the second switch is PWMed.
 本発明によれば、ブリッジ回路とフィルタ回路とブリッジ回路を制御する制御手段とを有し、直流電源から得た電力をブリッジ回路,フィルタ回路の順に介して商用系統に供給するための系統連系インバータ装置において、ブリッジ回路は複数のスイッチからなり、制御手段は、商用系統の電圧のゼロクロス点を基点として所定の期間前から所定期間経過後までの期間で商用系統を流れる電流の歪みが抑えられるようにスイッチを制御するモード1と、所定期間経過後から次の所定期間前までの期間でスイッチの損失を低減するようにスイッチを制御するモード2とを有することにより、系統電圧のゼロクロス付近の小電流領域において安定なスイッチング動作を実現し、損失の少ない系統連系インバータ装置を提供することができる。 According to the present invention, the grid interconnection has a bridge circuit, a filter circuit, and a control means for controlling the bridge circuit, and supplies power obtained from a DC power source to a commercial system through the bridge circuit and the filter circuit in this order. In the inverter device, the bridge circuit is composed of a plurality of switches, and the control means suppresses distortion of the current flowing through the commercial system from the period before the predetermined period until the predetermined period elapses with the zero cross point of the commercial system voltage as a base point. Mode 1 for controlling the switch as described above and mode 2 for controlling the switch so as to reduce the loss of the switch in a period from the elapse of a predetermined period to the next predetermined period. A stable switching operation can be realized in a small current region, and a grid-connected inverter device with little loss can be provided.
 あるいは、本発明によれば、ブリッジ回路とフィルタ回路とブリッジ回路を制御する制御手段とを有し、直流電源から得た電力をブリッジ回路,フィルタ回路の順に介して商用系統に供給するための系統連系インバータ装置において、ブリッジ回路は、第1のスイッチと第2のスイッチと第3のスイッチと第4のスイッチとからなり、直流電源の両端は、直列接続された第1のスイッチと第2のスイッチの両端と、直列接続された第3のスイッチと第4のスイッチの両端とに接続され、第1のスイッチと第2のスイッチの接続点と、第3のスイッチと第4のスイッチの接続点はフィルタ回路に接続され、フィルタ回路は商用系統に接続され、制御手段は、商用系統の電圧のゼロクロス点を基点として所定の期間前から所定期間経過後までの期間において、商用系統の電圧が正のときに、第1のスイッチをオンすると共に第2のスイッチをオフかつ第3と第4のスイッチを相補PWMし、商用系統の電圧が負のときに、第3のスイッチをオンすると共に第4のスイッチをオフかつ第1と第2のスイッチを相補PWMするモード1と、所定期間経過後から次の所定期間前までの期間において、商用系統の電圧が正のときに、第1のスイッチをオンすると共に第2のスイッチと第3のスイッチをオフかつ第4のスイッチをPWMし、商用系統の電圧が負のときに、第3のスイッチをオンすると共に第4のスイッチと第1のスイッチをオフかつ第2のスイッチをPWMするモード2とを有することにより、系統電圧のゼロクロス付近の小電流領域において安定なスイッチング動作を実現し、損失の少ない系統連系インバータ装置を提供することができる。 Alternatively, according to the present invention, a system that has a bridge circuit, a filter circuit, and a control unit that controls the bridge circuit, and supplies power obtained from a DC power supply to a commercial system through the bridge circuit and the filter circuit in this order. In the interconnected inverter device, the bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and both ends of the DC power supply are connected in series to the first switch and the second switch. Are connected to both ends of the first switch, the third switch and the fourth switch connected in series, the connection point of the first switch and the second switch, and the third switch and the fourth switch. The connection point is connected to the filter circuit, the filter circuit is connected to the commercial system, and the control means is based on the zero crossing point of the voltage of the commercial system from before the predetermined period until after the predetermined period has elapsed. In the meantime, when the voltage of the commercial system is positive, the first switch is turned on and the second switch is turned off and the third and fourth switches are complementary PWM. When the voltage of the commercial system is negative, In the mode 1 in which the third switch is turned on and the fourth switch is turned off and the first and second switches are complementary PWM, and the voltage of the commercial system is in the period from the elapse of a predetermined period to the next predetermined period. When positive, the first switch is turned on, the second switch and the third switch are turned off, and the fourth switch is PWMed. When the commercial system voltage is negative, the third switch is turned on. In addition, by having the fourth switch and the mode 2 in which the first switch is turned off and the second switch is PWM, a stable switching operation is realized in a small current region near the zero cross of the system voltage. It is possible to provide a low loss interconnection inverter device.
 さらに本発明によれば、直列接続された第1のスイッチと第2のスイッチの両端と、直列接続された第3のスイッチと第4のスイッチの両端を直流電源の両端に接続したブリッジ回路を有し、第1および第3のスイッチはIGBTとダイオードで構成することで導通損失を減らし、第2および第4のスイッチはMOSFETとダイオードで構成することで高速にスイッチングでき、かつスイッチング損失を低減させることができる。 Further, according to the present invention, there is provided a bridge circuit in which both ends of the first switch and the second switch connected in series, and both ends of the third switch and the fourth switch connected in series are connected to both ends of the DC power supply. The first and third switches are composed of IGBTs and diodes to reduce conduction loss, and the second and fourth switches are composed of MOSFETs and diodes to enable high-speed switching and reduce switching loss. Can be made.
本発明の第1の実施例による単相系統連系インバータ装置の構成図。BRIEF DESCRIPTION OF THE DRAWINGS The block diagram of the single phase system connection inverter apparatus by the 1st Example of this invention. 図1において、動作モード切替手段120を使用しない場合の電圧電流波形図(モード2のPWM信号による動作波形)。FIG. 1 is a voltage / current waveform diagram when the operation mode switching means 120 is not used (operation waveform based on a PWM signal in mode 2). 図2の期間(B)と(F)の拡大図。The enlarged view of the period (B) and (F) of FIG. 図2の期間(C)と(E)の拡大図。The enlarged view of the period (C) and (E) of FIG. 図1において、動作モード切替手段120を使用しない場合の電圧電流波形図(モード1のPWM信号による動作波形)。FIG. 1 is a voltage-current waveform diagram when the operation mode switching means 120 is not used (operation waveform by a PWM signal in mode 1). 図1において、動作モード切替手段120を使用した場合の電圧電流波形図。FIG. 2 is a voltage / current waveform diagram when the operation mode switching means 120 is used in FIG. 1. 本発明の第1の実施例による単相系統連系インバータ装置の制御手段。The control means of the single phase system connection inverter apparatus by the 1st example of the present invention. 図1において、動作モード切替手段120を使用した場合の電圧電流波形図(図7よりも出力電流が大きい場合)。FIG. 1 is a voltage / current waveform diagram when the operation mode switching means 120 is used (when the output current is larger than that in FIG. 7). 本発明の第2の実施例による単相系統連系インバータ装置の構成図。The block diagram of the single phase system connection inverter apparatus by the 2nd Example of this invention. 本発明の第2の実施例における電圧電流波形図。The voltage-current waveform figure in the 2nd Example of this invention. 図10のスイッチング動作の詳細図。FIG. 11 is a detailed diagram of the switching operation of FIG. 10. 本発明の第3の実施例による分散電源システムの構成図。The block diagram of the distributed power supply system by the 3rd Example of this invention. 系統連系インバータ装置の構成図。The block diagram of a grid connection inverter apparatus.
 以下、本発明について実施例を挙げながら説明する。 Hereinafter, the present invention will be described with reference to examples.
 図1は本発明の第1の実施例による単相系統連系インバータ装置1の回路構成図である。 FIG. 1 is a circuit configuration diagram of a single-phase grid-connected inverter device 1 according to a first embodiment of the present invention.
 単相系統連系インバータ装置1の主回路について説明する。直流電源10の両端には、バイパスコンデンサ60,スイッチング素子20と21の直列接続体およびスイッチング素子22と23の直列接続体が接続される。スイッチング素子20~23には、それぞれ、フリーホイールダイオード40~43が並列に接続される。スイッチング素子20と21の接続点と、スイッチング素子22と23の接続点との間に、インダクタ70とコンデンサ61とインダクタ71との直列接続体が接続される。コンデンサ61の両端が商用系統80に接続される。本実施例では、スイッチング素子20と22にはIGBTを用いる。またスイッチング素子21と23にはMOSFETを用いる。 The main circuit of the single-phase grid-connected inverter device 1 will be described. Connected to both ends of the DC power supply 10 are a bypass capacitor 60, a series connection body of the switching elements 20 and 21, and a series connection body of the switching elements 22 and 23. Free wheel diodes 40 to 43 are connected in parallel to the switching elements 20 to 23, respectively. A series connection body of an inductor 70, a capacitor 61, and an inductor 71 is connected between the connection point of the switching elements 20 and 21 and the connection point of the switching elements 22 and 23. Both ends of the capacitor 61 are connected to the commercial system 80. In the present embodiment, IGBTs are used for the switching elements 20 and 22. Further, MOSFETs are used for the switching elements 21 and 23.
 前述したスイッチング素子20とダイオード40、スイッチング素子21とダイオード41、スイッチング素子22とダイオード42、スイッチング素子23とダイオード43は、それぞれ、第1のスイッチ,第2のスイッチ,第3のスイッチ,第4のスイッチを構成する。また、バイパスコンデンサ60、第1~4のスイッチは、直流電源10から出力される直流電力を交流のパルス電力に変換する単相ブリッジ回路を構成する。 The switching element 20 and the diode 40, the switching element 21 and the diode 41, the switching element 22 and the diode 42, the switching element 23 and the diode 43 described above are respectively the first switch, the second switch, the third switch, and the fourth switch. Configure the switch. The bypass capacitor 60 and the first to fourth switches constitute a single-phase bridge circuit that converts DC power output from the DC power supply 10 into AC pulsed power.
 前記単相ブリッジ回路の出力端は、第1スイッチと第2スイッチの接続点と、第3スイッチと第4スイッチの接続点である。また、インダクタ70,コンデンサ61,インダクタ71は、前記単相ブリッジ回路から出力された交流のパルス電力を平滑して系統へ出力するフィルタ回路を構成する。前記フィルタ回路の入力端は、インダクタ70とコンデンサ61とインダクタ71とで構成された直列接続体の両端であり、出力端はコンデンサ61の両端である。 The output terminal of the single-phase bridge circuit is a connection point between the first switch and the second switch and a connection point between the third switch and the fourth switch. The inductor 70, the capacitor 61, and the inductor 71 constitute a filter circuit that smoothes the AC pulse power output from the single-phase bridge circuit and outputs it to the system. The input ends of the filter circuit are both ends of a series connection body composed of an inductor 70, a capacitor 61, and an inductor 71, and the output ends are both ends of the capacitor 61.
 また、単相系統連系インバータ装置1には、前述した主回路を制御するための制御手段100が設けられている。制御手段100について説明する。単相系統連系インバータ装置1の入力側の電圧を検出するためにバイパスコンデンサ60の両端に電圧検出手段102が接続され、出力側の電圧を検出するためにコンデンサ61の両端に電圧検出手段104が接続される。そして、電圧検出手段102,104は系統連系制御手段108に接続される。また、入力側の電流を検出するために直流電源10の正極側に電流センサ90が挿入され、出力側の電流を検出するために前記単相ブリッジ回路の出力側であるスイッチング素子20と21の接続点とインダクタ70との間に電流センサ91が挿入される。電流センサ90と電流センサ91は、それぞれ、電流検出手段101と電流検出手段103に接続される。そして電流検出手段101と電流検出手段103は、系統連系制御手段108に接続される。系統連系制御手段108にはPWM生成手段106と107が接続される。PWM生成手段106は切替手段109とリップル検出手段111に接続される。PWM生成手段107は切替手段109に接続される。切替手段109はドライブ手段105に接続される。ドライブ手段105にはスイッチング素子20~23のゲートが接続される。更に、電圧検出手段102と104はリップル検出手段111に接続される。電流検出手段103とリップル検出手段111は比較手段110に接続される。比較手段110は切替手段109に接続される。 The single-phase grid-connected inverter device 1 is provided with a control means 100 for controlling the main circuit described above. The control means 100 will be described. In order to detect the voltage on the input side of the single-phase grid-connected inverter device 1, voltage detection means 102 is connected to both ends of the bypass capacitor 60, and voltage detection means 104 is connected to both ends of the capacitor 61 in order to detect the voltage on the output side. Is connected. The voltage detection means 102 and 104 are connected to the grid connection control means 108. Further, a current sensor 90 is inserted on the positive electrode side of the DC power supply 10 to detect the current on the input side, and the switching elements 20 and 21 on the output side of the single-phase bridge circuit to detect the current on the output side. A current sensor 91 is inserted between the connection point and the inductor 70. The current sensor 90 and the current sensor 91 are connected to the current detection unit 101 and the current detection unit 103, respectively. The current detection unit 101 and the current detection unit 103 are connected to the grid connection control unit 108. PWM generation means 106 and 107 are connected to the grid interconnection control means 108. The PWM generation unit 106 is connected to the switching unit 109 and the ripple detection unit 111. The PWM generation unit 107 is connected to the switching unit 109. The switching unit 109 is connected to the drive unit 105. The drive means 105 is connected to the gates of the switching elements 20-23. Further, the voltage detection means 102 and 104 are connected to the ripple detection means 111. The current detection unit 103 and the ripple detection unit 111 are connected to the comparison unit 110. The comparison unit 110 is connected to the switching unit 109.
 制御手段100は、単相系統連系インバータ装置1が商用系統80に所望の電力を出力するように以下の制御を行う。系統連系制御手段108は、電圧検出手段102と104、電流検出手段101と103から入力側および出力側の電圧・電流を検出して、商用系統80の系統電圧Vacと商用系統80を流れる系統電流Iacが同位相(力率0.95~1.0)となるように変調率を演算し、PWM生成手段106と107に出力する。PWM生成手段106と107は、系統連系制御手段108から出力された変調率とキャリア信号とを比較してスイッチング素子20~23をスイッチングするためのPWM信号を生成し、切替手段109を介してドライブ手段105へ出力する。ドライブ手段105はPWM生成手段106または107から出力されたPWM信号を増幅し、スイッチング素子20~23のゲートをドライブする。 The control means 100 performs the following control so that the single-phase system interconnection inverter device 1 outputs desired power to the commercial system 80. The grid connection control means 108 detects the voltage and current on the input side and output side from the voltage detection means 102 and 104 and the current detection means 101 and 103, and flows through the system voltage Vac of the commercial system 80 and the commercial system 80. The modulation factor is calculated so that the current Iac has the same phase (power factor 0.95 to 1.0), and is output to the PWM generators 106 and 107. PWM generation means 106 and 107 generate a PWM signal for switching the switching elements 20 to 23 by comparing the modulation factor output from the grid connection control means 108 with the carrier signal, and via the switching means 109. Output to the drive means 105. The drive means 105 amplifies the PWM signal output from the PWM generation means 106 or 107 and drives the gates of the switching elements 20-23.
 ここで、前述した切替手段109と比較手段110は、動作モード切替手段120を構成する。動作モード切替手段120は、PWM生成手段106またはPWM生成手段107が生成したPWM信号のどちらかを、後述する方法を基にしてドライブ手段105に伝達する機能を持つ。この動作モード切替手段120とリップル検出手段111が本発明に関わる手段である。 Here, the switching unit 109 and the comparison unit 110 described above constitute an operation mode switching unit 120. The operation mode switching unit 120 has a function of transmitting either the PWM generation unit 106 or the PWM signal generated by the PWM generation unit 107 to the drive unit 105 based on a method described later. The operation mode switching means 120 and the ripple detection means 111 are means related to the present invention.
 本実施例の動作について以下説明する。本発明の作用・効果を明確にするため、本発明に関わる動作モード切替手段120とリップル検出手段111を使用しない場合およびそれらを使用した場合にわけて説明する。 The operation of this embodiment will be described below. In order to clarify the operation and effect of the present invention, the operation mode switching means 120 and the ripple detection means 111 according to the present invention will be described separately when they are used and when they are used.
(動作モード切替手段120とリップル検出手段111を使用しない場合の動作)
 まず、図1において動作モード切替手段120を使用せず、PWM生成手段106が生成したPWM信号(以後、モード1と称す)でスイッチング素子20~23をスイッチングした場合の動作波形を図2に示す。Vacは商用系統80の電圧(以下、系統電圧と称す)である。Iiは前記単相ブリッジ回路の出力電流である(Iiは、図2中の上から2番目にある三角波に正弦波が重畳した形の波形)。Ii(ave)はIiの平均電流であり、これはIiが前記フィルタ回路で平滑された電流である系統電流Iacとほぼ等しい。Vg(20)~Vg(23)はスイッチング素子20~23のゲート駆動電圧である。以下、図2を参照しながら説明する。
(Operation when the operation mode switching means 120 and the ripple detection means 111 are not used)
First, FIG. 2 shows operation waveforms when the switching elements 20 to 23 are switched by the PWM signal generated by the PWM generation means 106 (hereinafter referred to as mode 1) without using the operation mode switching means 120 in FIG. . Vac is the voltage of the commercial system 80 (hereinafter referred to as system voltage). Ii is an output current of the single-phase bridge circuit (Ii is a waveform in which a sine wave is superimposed on the second triangular wave from the top in FIG. 2). Ii (ave) is an average current of Ii, which is substantially equal to the system current Iac, which is a current smoothed by the filter circuit. Vg (20) to Vg (23) are gate drive voltages of the switching elements 20 to 23. Hereinafter, a description will be given with reference to FIG.
 Vacが正の半周期のときは、Vg(20)は連続的にオンし、Vg(21)は連続的にオフである。そして、Vg(22)とVg(23)は互い違いにオン・オフする(以下、これを相補PWMと呼ぶ)。また、Vacが負の半周期のときは、Vg(20)とVg(21)は相補PWMする。そして、Vg(22)は連続的にオンし、Vg(23)は連続的にオフである。 When Vac is a positive half cycle, Vg (20) is continuously turned on and Vg (21) is continuously turned off. Vg (22) and Vg (23) are alternately turned on / off (hereinafter referred to as complementary PWM). When Vac is a negative half cycle, Vg (20) and Vg (21) perform complementary PWM. Vg (22) is continuously turned on, and Vg (23) is continuously turned off.
 なお、直列に接続されたスイッチング素子20と21、スイッチング素子22と23が共にオン状態となることがないように、Vg(20)とVg(21)との間および、Vg(22)とVg(23)との間にはデッドタイムを設けている。前述したデッドタイムを設けない場合、スイッチング素子におけるターンオン時間とターンオフ時間との相違から、スイッチング素子20と21またはスイッチング素子22と23が共にオンした状態になる可能性がある。そして、この場合は直流電源10→スイッチング素子20→スイッチング素子21、あるいは直流電源10→スイッチング素子22→スイッチング素子23のループに大きな短絡電流が流れ、スイッチング素子が破壊する恐れがある。 In addition, between Vg (20) and Vg (21) and between Vg (22) and Vg so that switching elements 20 and 21 and switching elements 22 and 23 connected in series are not turned on. A dead time is provided between (23) and (23). When the above-described dead time is not provided, there is a possibility that both the switching elements 20 and 21 or the switching elements 22 and 23 are turned on due to the difference between the turn-on time and the turn-off time in the switching element. In this case, a large short-circuit current flows through the loop of the DC power supply 10 → the switching element 20 → the switching element 21 or the DC power supply 10 → the switching element 22 → the switching element 23, and the switching element may be destroyed.
 これ以後、図中の期間(A)~(F)に分けて動作を説明する。期間(A)は系統電圧Vacが正かつ前記単相ブリッジ回路の出力電流Iiが正となる期間である。期間(B)と(F)は、Vacが正であって、リップルが原因でIiの上限が正かつIiの下限が負になる期間である。期間(B)と(F)の差は、Iiの平均電流Ii(ave)が時間経過で上昇するか下降するかの違いのみであって、前記単相ブリッジ回路のスイッチング動作に関わる違いはない。これと同様の考えで、期間(D)はVacが負かつIiが負となる期間である。期間(C)と(E)は、Vacが負であって、リップルが原因でIiの上限が正かつIiの下限が負になる期間である。期間(C)と(E)の差は、Iiの平均電流Ii(ave)が時間経過で上昇するか下降するかの違いのみであって、前記単相ブリッジ回路のスイッチング動作に関わる違いはない。 Hereafter, the operation will be described in divided periods (A) to (F) in the figure. The period (A) is a period in which the system voltage Vac is positive and the output current Ii of the single-phase bridge circuit is positive. Periods (B) and (F) are periods in which Vac is positive and the upper limit of Ii is positive and the lower limit of Ii is negative due to ripple. The difference between the periods (B) and (F) is only the difference in whether the average current Ii (ave) of Ii increases or decreases over time, and there is no difference related to the switching operation of the single-phase bridge circuit. . Based on the same idea, the period (D) is a period in which Vac is negative and Ii is negative. Periods (C) and (E) are periods in which Vac is negative and the upper limit of Ii is positive and the lower limit of Ii is negative due to ripple. The difference between the periods (C) and (E) is only the difference in whether the average current Ii (ave) of Ii increases or decreases over time, and there is no difference related to the switching operation of the single-phase bridge circuit. .
 はじめに、系統電圧Vacが正である期間(A),(B),(F)について説明する。 First, the periods (A), (B), and (F) in which the system voltage Vac is positive will be described.
 期間(A)において、スイッチング素子22がオフ、スイッチング素子23がオンしているときは、直流電源10→スイッチング素子20→インダクタ70→コンデンサ61→インダクタ71→スイッチング素子23の経路で電流が流れる。次にスイッチング素子22がオン、スイッチング素子23がオフしているときは、スイッチング素子20→インダクタ70→コンデンサ61→インダクタ71→ダイオード42の経路で電流が流れる。この通り、期間(A)においてはスイッチング素子22に電流は流れておらず、スイッチング素子22をオンしなくても問題はない。 In the period (A), when the switching element 22 is off and the switching element 23 is on, a current flows through the path of the DC power source 10 → the switching element 20 → the inductor 70 → the capacitor 61 → the inductor 71 → the switching element 23. Next, when the switching element 22 is on and the switching element 23 is off, a current flows through the path of the switching element 20 → the inductor 70 → the capacitor 61 → the inductor 71 → the diode 42. As described above, no current flows through the switching element 22 in the period (A), and there is no problem even if the switching element 22 is not turned on.
 期間(B)と(F)の動作を説明するため、その期間を拡大した動作波形を図3に示す。ここから図3を参照しながら説明する。図3において、t0は出力電流Iiが負から正になるIi=0の時の時刻であり、t1は出力電流Ii>0でありIiが上昇から下降に遷移しはじめるときの時刻であり、t2は出力電流Iiが正から負になるIi=0の時の時刻であり、t3は出力電流Ii<0でありIiが下降から上昇に遷移しはじめるときの時刻であり、t4は出力電流Iiが負から正になるIi=0の時の時刻である。 In order to explain the operation in the periods (B) and (F), FIG. This will be described with reference to FIG. In FIG. 3, t0 is the time when Ii = 0 when the output current Ii becomes negative to positive, t1 is the time when the output current Ii> 0 and Ii starts to transition from rising to falling, and t2 Is the time when Ii = 0 when the output current Ii becomes negative from positive, t3 is the time when the output current Ii <0 and Ii starts to transition from falling to rising, and t4 is the time when the output current Ii is This is the time when Ii = 0 from negative to positive.
 まず、前記ブリッジインバータ回路の出力電流Iiが正である時刻t0からt2の動作を説明する。時刻t0-t1において、スイッチング素子22がオフ、スイッチング素子23がオンしているときは、直流電源10→スイッチング素子20→インダクタ70→コンデンサ61→インダクタ71→スイッチング素子23の経路で電流が流れる。次に、時刻t1-t2において、スイッチング素子23がオフ、スイッチング素子22がオンしているときは、スイッチング素子20→インダクタ70→コンデンサ61→インダクタ71→ダイオード42の経路で電流が流れる。つまり、Iiが正である時刻t0-t2の間までは、期間(A)の動作と同様である。 First, the operation from time t0 to t2 when the output current Ii of the bridge inverter circuit is positive will be described. At time t0-t1, when the switching element 22 is off and the switching element 23 is on, a current flows through the path of the DC power source 10 → the switching element 20 → the inductor 70 → the capacitor 61 → the inductor 71 → the switching element 23. Next, at time t1-t2, when switching element 23 is off and switching element 22 is on, a current flows through the path of switching element 20 → inductor 70 → capacitor 61 → inductor 71 → diode 42. That is, the operation is similar to that in the period (A) until time t0-t2 when Ii is positive.
 次に、前記単相ブリッジ回路の出力電流Iiが負となる時刻t2からt4の動作を説明する。t2-t3において、スイッチング素子22がオン、スイッチング素子23がオフしているときは、コンデンサ61→インダクタ70→ダイオード40→スイッチング素子22→インダクタ71の経路で電流が流れる。次に時刻t3-t4で、スイッチング素子22がオフ、スイッチング素子23がオンすると、コンデンサ61→インダクタ70→ダイオード40→直流電源10→スイッチング素子23とダイオード43の経路で電流が流れる。つまり、Iiが負になる時刻t2-t4の間は、スイッチング素子22に電流が流れる期間が存在する。 Next, the operation from time t2 to t4 when the output current Ii of the single-phase bridge circuit becomes negative will be described. At t2-t3, when the switching element 22 is on and the switching element 23 is off, a current flows through the path of the capacitor 61 → the inductor 70 → the diode 40 → the switching element 22 → the inductor 71. Next, at time t3-t4, when the switching element 22 is turned off and the switching element 23 is turned on, a current flows through the path of the capacitor 61 → the inductor 70 → the diode 40 → the DC power supply 10 → the switching element 23 and the diode 43. That is, there is a period during which current flows through the switching element 22 between time t2 and t4 when Ii becomes negative.
 次に図2に戻って、系統電圧Vacが負である期間(C)~(E)について説明する。 Next, returning to FIG. 2, the periods (C) to (E) in which the system voltage Vac is negative will be described.
 期間(D)において、スイッチング素子20がオフ、スイッチング素子21がオンしているときは、直流電源10→スイッチング素子22→インダクタ71→コンデンサ61→インダクタ70→スイッチング素子21の経路で電流が流れる。次にスイッチング素子20がオン、スイッチング素子21がオフしているときは、スイッチング素子22→インダクタ71→コンデンサ61→インダクタ70→ダイオード40の経路で電流が流れる。この通り、期間(D)においてはスイッチング素子20に電流は流れておらず、スイッチング素子20をオンしなくても問題はない。 In the period (D), when the switching element 20 is off and the switching element 21 is on, a current flows through the path of the DC power source 10 → the switching element 22 → the inductor 71 → the capacitor 61 → the inductor 70 → the switching element 21. Next, when the switching element 20 is on and the switching element 21 is off, a current flows through the path of the switching element 22 → the inductor 71 → the capacitor 61 → the inductor 70 → the diode 40. As described above, no current flows through the switching element 20 during the period (D), and there is no problem even if the switching element 20 is not turned on.
 期間(C)と(E)の動作を説明するため、その期間を拡大した動作波形を図4に示す。ここから図4を参照しながら説明する。図4において、t0′は出力電流Iiが正から負になるIi=0の時の時刻であり、t1′は出力電流Ii<0でありIiが下降から上昇に遷移しはじめるときの時刻であり、t2′は出力電流Iiが負から正になるIi=0の時の時刻であり、t3′は出力電流Ii>0でありIiが上昇から下降に遷移しはじめるときの時刻であり、t4′は出力電流Iiが正から負になるIi=0の時の時刻である。 In order to explain the operation of the periods (C) and (E), FIG. This will be described with reference to FIG. In FIG. 4, t0 ′ is the time when Ii = 0 when the output current Ii becomes negative from positive, and t1 ′ is the time when the output current Ii <0 and Ii starts to transition from falling to rising. , T2 ′ is the time when Ii = 0 when the output current Ii becomes negative to positive, t3 ′ is the time when the output current Ii> 0 and Ii starts to transition from rising to falling, and t4 ′. Is the time when Ii = 0 when the output current Ii changes from positive to negative.
 まず、前記単相ブリッジ回路の出力電流Iiが負である時刻t0′からt2′の動作を説明する。時刻t0′-t1′において、スイッチング素子20がオフ、スイッチング素子21がオンしているときは、直流電源10→スイッチング素子22→インダクタ71→コンデンサ61→インダクタ70→スイッチング素子21の経路で電流が流れる。次に、時刻t1′-t2′において、スイッチング素子21がオフ、スイッチング素子20がオンしているときは、スイッチング素子22→インダクタ71→コンデンサ61→インダクタ70→ダイオード40の経路で電流が流れる。つまり、Iiが負である時刻t0′-t2′の間までは、期間(D)の動作と同様である。 First, the operation from time t0 ′ to t2 ′ when the output current Ii of the single-phase bridge circuit is negative will be described. At time t0'-t1 ', when the switching element 20 is off and the switching element 21 is on, current flows through the path of the DC power source 10 → switching element 22 → inductor 71 → capacitor 61 → inductor 70 → switching element 21. Flowing. Next, at time t1′-t2 ′, when the switching element 21 is off and the switching element 20 is on, a current flows through the path of the switching element 22 → the inductor 71 → the capacitor 61 → the inductor 70 → the diode 40. That is, the operation is similar to that in the period (D) until time t0′-t2 ′ where Ii is negative.
 次に、前記単相ブリッジ回路の出力電流Iiが正となる時刻t2′からt4′の動作を説明する。t2′-t3′において、スイッチング素子20がオン、スイッチング素子21がオフしているときは、コンデンサ61→インダクタ71→ダイオード42→スイッチング素子20→インダクタ70の経路で電流が流れる。次に時刻t3′-t4′で、スイッチング素子20がオフ、スイッチング素子21がオンすると、コンデンサ61→インダクタ71→ダイオード42→直流電源10→スイッチング素子21とダイオード41の経路で電流が流れる。つまり、Iiが正になる時刻t2′-t4′の間は、スイッチング素子20に電流が流れる期間が存在する。 Next, the operation from time t2 ′ to t4 ′ when the output current Ii of the single-phase bridge circuit becomes positive will be described. At t2′-t3 ′, when the switching element 20 is on and the switching element 21 is off, a current flows through the path of the capacitor 61 → the inductor 71 → the diode 42 → the switching element 20 → the inductor 70. Next, at time t3′-t4 ′, when switching element 20 is turned off and switching element 21 is turned on, a current flows through the path of capacitor 61 → inductor 71 → diode 42 → DC power supply 10 → switching element 21 and diode 41. In other words, there is a period during which current flows through the switching element 20 between time t2 ′ and t4 ′ when Ii becomes positive.
 以上に説明した通り、図1において動作モード切替手段120とリップル検出手段111を使用せず、モード1のPWM信号でスイッチング素子20~23をスイッチングした場合、電流が流れていないスイッチング素子(期間(A)でのスイッチング素子22、期間(D)でのスイッチング素子20)をスイッチングするため、余分なスイッチング損失が発生する。 As described above, when the switching elements 20 to 23 are switched by the mode 1 PWM signal without using the operation mode switching means 120 and the ripple detection means 111 in FIG. 1, the switching elements (period ( Since the switching element 22 in A) and the switching element 20) in the period (D) are switched, an extra switching loss occurs.
 一方、図1において動作モード切替手段120とリップル検出手段111を使用せず、PWM生成手段107が生成したPWM信号(以後、モード2と称す)でスイッチング素子20~23をスイッチングした場合の動作波形を図5に示す。以下、図5を参照しながら説明する。 On the other hand, in FIG. 1, the operation waveforms when the switching elements 20 to 23 are switched by the PWM signal generated by the PWM generation means 107 (hereinafter referred to as mode 2) without using the operation mode switching means 120 and the ripple detection means 111. Is shown in FIG. Hereinafter, a description will be given with reference to FIG.
 Vacが正の半周期のときは、Vg(20)は連続的にオンし、Vg(21)とVg(22)は連続的にオフである。そして、Vg(23)がオン・オフする(以下、これをPWMと呼ぶ)。また、Vacが負の半周期のときは、Vg(22)は連続的にオンし、Vg(20)とVg(23)は連続的にオフである。そして、Vg(21)はPWMする。この通り、図5は図2と比較してVg(20)とVg(21)間、Vg(22)とVg(23)間で行っていた相補PWMをせず、Vg(21)あるいはVg(23)をPWMしている。 When Vac is a positive half cycle, Vg (20) is continuously turned on, and Vg (21) and Vg (22) are continuously turned off. Then, Vg (23) is turned on / off (hereinafter referred to as PWM). When Vac is a negative half cycle, Vg (22) is continuously turned on, and Vg (20) and Vg (23) are continuously turned off. Vg (21) is PWMed. In this way, FIG. 5 does not perform complementary PWM performed between Vg (20) and Vg (21) and between Vg (22) and Vg (23) as compared with FIG. 2, but Vg (21) or Vg ( 23) is PWMed.
 期間(A)においてはスイッチング素子22に、期間(D)においてはスイッチング素子20に電流は流れないことから、それらのスイッチング素子をオンせずとも、前記単相ブリッジ回路の出力電流Iiは図2と同様である。しかしながら、期間(B),(C),(E),(F)においてはIiに図5のような歪みが生じる場合がある。これは、期間(B),(F)においてはスイッチング素子22がオフしているため、図2で示したIiの負側の電流がスイッチング素子22に流れることができず、Iiが正側に増加してしまうことが原因である。また期間(C),(E)でも同様に、スイッチング素子20をオフしているため、図2で示したIiの正側の電流がスイッチング素子20に流れることができず、Iiが負側に増加してしまうことが原因である。しかし一方で、図5は図2と比較し、スイッチング素子20と22のスイッチングの回数が少なくてスイッチング損失が少ないという効果を奏する。 Since no current flows through the switching element 22 during the period (A) and through the switching element 20 during the period (D), the output current Ii of the single-phase bridge circuit is as shown in FIG. It is the same. However, in the periods (B), (C), (E), and (F), distortion as shown in FIG. 5 may occur in Ii. This is because the current on the negative side of Ii shown in FIG. 2 cannot flow through the switching element 22 during the periods (B) and (F), and Ii is on the positive side. The cause is an increase. Similarly, in the periods (C) and (E), since the switching element 20 is turned off, the current on the positive side of Ii shown in FIG. 2 cannot flow to the switching element 20, and Ii is on the negative side. The cause is an increase. On the other hand, however, FIG. 5 has the effect that the switching frequency of the switching elements 20 and 22 is small and the switching loss is small compared to FIG.
 (動作モード切替手段120とリップル検出手段111を使用した場合の動作)
 図1において動作モード切替手段120とリップル検出手段111を使用した場合の動作波形を図6に示す。以後、図1と図6を参照しながら説明する。動作モード切替手段120は前述した期間(A)~(F)を判別し、期間(A)と(D)ではモード2のPWM信号をドライブ手段105に伝達するようにPWM生成手段107と切替手段109とドライブ手段105とをつなぎ、期間(B),(C),(E),(F)ではモード1のPWM信号をドライブ手段105に伝達するようにPWM生成手段106と切替手段109とドライブ手段105とをつなぐ。
(Operation when the operation mode switching means 120 and the ripple detection means 111 are used)
FIG. 6 shows operation waveforms when the operation mode switching means 120 and the ripple detection means 111 are used in FIG. Hereinafter, description will be made with reference to FIG. 1 and FIG. The operation mode switching means 120 discriminates the above-described periods (A) to (F), and in the periods (A) and (D), the PWM generation means 107 and the switching means are transmitted so as to transmit the mode 2 PWM signal to the drive means 105. 109 and the drive means 105 are connected, and in the periods (B), (C), (E), and (F), the PWM generation means 106, the switching means 109, and the drive are transmitted so that the mode 1 PWM signal is transmitted to the drive means 105. The means 105 is connected.
 次に、動作モード切替手段120が期間(A)~(F)を判別する方法を説明する。 Next, a method in which the operation mode switching unit 120 determines the periods (A) to (F) will be described.
 まず、判別の条件については下記の通りである。動作モード切替手段120は、前記単相ブリッジ回路の平均出力電流Ii(ave)の振幅値|Ii(ave)|とIiのリップルの振幅値Irとを比較し、Irが|Ii(ave)|より大きい場合は前記単相ブリッジ回路のスイッチング動作中に電流の極性が切り替わる期間(B),(C),(E),(F)と判別する。それとは逆に、動作モード切替手段120は、Irが|Ii(ave)|より小さい場合は、期間(A),(D)と判別する。 First, the conditions for discrimination are as follows. The operation mode switching means 120 compares the amplitude value | Ii (ave) | of the average output current Ii (ave) of the single-phase bridge circuit with the amplitude value Ir of the ripple of Ii, and Ir is | Ii (ave) | If larger, it is determined as periods (B), (C), (E), and (F) during which the polarity of the current is switched during the switching operation of the single-phase bridge circuit. On the other hand, when Ir is smaller than | Ii (ave) |, the operation mode switching unit 120 determines the periods (A) and (D).
 ここでリップル検出手段111がIrを検出する方法に触れる。例えば、系統電圧Vacが正であってスイッチング素子20がオンし、スイッチング素子23がオフからオンに遷移したとき、前記単相ブリッジ回路の出力端には直流電源10の電圧Vpnが出力され、前記フィルタ回路を構成するインダクタ70,コンデンサ61,インダクタ71に印加される。従って、インダクタ70と71には、VpnからVacを差し引いた電圧が印加され、インダクタ70と71の電流即ち前記単相ブリッジ回路の出力電流Iiは増加する。この増加した電流値の半分の値がリップルの振幅Irに相当する。これより、Irは、Vpn、スイッチング素子23のオン時間(Vacが負の場合はスイッチング素子21のオン時間)、Vac、インダクタ70と71の合成インダクタンスを基にした演算から求めることが可能である。そこで、リップル検出手段111には、電圧検出手段102からVpn、PWM生成手段106からスイッチング素子21と23のオン時間、電圧検出手段104から系統電圧Vacが入力され、それらの値と記憶されたインダクタ70と71の合成インダクタンスを基にIrを演算する。なお、この演算はスイッチング素子21または23のスイッチング動作の度に行われ、Irは更新される。リップル検出手段111は、Irが更新される間は更新される前のIrを保持して出力する。 Here, a method of detecting the Ir by the ripple detecting means 111 will be described. For example, when the system voltage Vac is positive and the switching element 20 is turned on and the switching element 23 transitions from OFF to ON, the voltage Vpn of the DC power supply 10 is output to the output terminal of the single-phase bridge circuit, The voltage is applied to the inductor 70, the capacitor 61, and the inductor 71 that constitute the filter circuit. Accordingly, a voltage obtained by subtracting Vac from Vpn is applied to the inductors 70 and 71, and the current of the inductors 70 and 71, that is, the output current Ii of the single-phase bridge circuit increases. Half of the increased current value corresponds to the ripple amplitude Ir. Thus, Ir can be obtained from the calculation based on Vpn, the ON time of the switching element 23 (the ON time of the switching element 21 when Vac is negative), Vac, and the combined inductance of the inductors 70 and 71. . Therefore, the ripple detection means 111 receives Vpn from the voltage detection means 102, the ON time of the switching elements 21 and 23 from the PWM generation means 106, and the system voltage Vac from the voltage detection means 104, and those values and stored inductors. Ir is calculated based on the combined inductance of 70 and 71. This calculation is performed each time the switching element 21 or 23 is switched, and Ir is updated. The ripple detection unit 111 holds and outputs Ir before being updated while Ir is updated.
 一方、リップルの振幅値Irの検出は他の方法でも可能である。その一例を図7に示す。図7では、図1中のリップル検出手段111の替わりに、リップル検出手段112が備えられている。リップル検出手段112の入力には電流検出手段103が接続され、その出力には比較手段110が接続される。リップル検出手段112は、商用系統(50Hzまたは60Hz)の周波数をカットするハイパスフィルタと砲絡線検波回路から構成される。一般的に砲絡線検波回路とは、電気信号の時系列における砲絡線に目的の情報がある場合に砲絡線のみを取り出す回路である。電流検出手段103から前記単相ブリッジ回路の出力電流Iiの値がリップル検出手段112に入力されると、まず前述したハイパスフィルタで商用系統の周波数がカットされ、リップル成分のみの信号になる。この信号を砲絡線検波回路に入力すると、リップル成分の砲絡線のみが取り出され、すなわち図6に示したようなIrの振幅値のみが出力される。また、Irを求める手段には他の方法でも可能であり、本実施例に限定されるものではない。 On the other hand, the ripple amplitude value Ir can be detected by other methods. An example is shown in FIG. In FIG. 7, a ripple detection unit 112 is provided instead of the ripple detection unit 111 in FIG. The current detection means 103 is connected to the input of the ripple detection means 112, and the comparison means 110 is connected to the output. The ripple detection means 112 includes a high-pass filter that cuts off the frequency of a commercial system (50 Hz or 60 Hz) and a gun-line detection circuit. In general, the arc detection circuit is a circuit that extracts only the arc line when there is target information in the arc line in the time series of the electrical signal. When the value of the output current Ii of the single-phase bridge circuit is input from the current detection unit 103 to the ripple detection unit 112, the frequency of the commercial system is first cut by the above-described high-pass filter, so that only a ripple component is obtained. When this signal is input to the arcuate line detection circuit, only the arcuate line of the ripple component is extracted, that is, only the Ir amplitude value as shown in FIG. 6 is output. Further, Ir can be obtained by other methods and is not limited to the present embodiment.
 こうして求めたリップルの振幅値Irは、図6に示す通り、一定値ではなくて系統電圧Vacがゼロからピークまたはピークからゼロになる途中に極大値をとる。 As shown in FIG. 6, the ripple amplitude value Ir obtained in this way is not a constant value but takes a maximum value in the middle of the system voltage Vac from zero to peak or from peak to zero.
 ここから、動作モード切替手段の動作の説明に戻る。比較手段110には、電流検出手段103から前記単相ブリッジ回路の平均出力電流Ii(ave)の振幅値|Ii(ave)|、リップル検出手段111からIiのリップルの振幅値Irが入力される。比較手段110は|Ii(ave)|とIrを比較し、|Ii(ave)|がIrより大きい場合はLowを出力し、その逆の場合はHighを出力する。切替手段109は、比較手段110の出力がLowの場合はモード2のPWM信号をドライブ手段105に伝達するようPWM生成手段107と切替手段109とドライブ手段105をつなぎ、比較手段110の出力がHighの場合はモード1のPWM信号をドライブ手段105に伝達するようPWM生成手段106と切替手段109とドライブ手段105をつなぐ。 From here, it returns to the description of the operation of the operation mode switching means. The comparison unit 110 receives the amplitude value | Ii (ave) | of the average output current Ii (ave) of the single-phase bridge circuit from the current detection unit 103 and the ripple amplitude value Ir of Ii from the ripple detection unit 111. . Comparing means 110 compares | Ii (ave) | and Ir, and outputs Low when | Ii (ave) | is greater than Ir, and outputs High when vice versa. The switching unit 109 connects the PWM generation unit 107, the switching unit 109, and the drive unit 105 so that the mode 2 PWM signal is transmitted to the drive unit 105 when the output of the comparison unit 110 is Low, and the output of the comparison unit 110 is High. In this case, the PWM generation means 106, the switching means 109, and the drive means 105 are connected so as to transmit the PWM signal of mode 1 to the drive means 105.
 これらの動作により、系統電圧Vacのゼロクロス付近の小電流領域(期間(B),(C),(E),(F))では、モード1の相補PWM信号でスイッチング素子20~23をスイッチングして、系統電流Iacの歪みを抑えることができる。そして、大電流領域(期間(A),(D))においては、モード1よりスイッチング回数の少ないモード2のPWM信号でスイッチング素子20~23をスイッチングして、スイッチング損失を低減することができる。 With these operations, in the small current region (periods (B), (C), (E), (F)) near the zero cross of the system voltage Vac, the switching elements 20 to 23 are switched by the mode 1 complementary PWM signal. Thus, distortion of the system current Iac can be suppressed. In the large current region (periods (A) and (D)), the switching elements 20 to 23 are switched by the PWM signal of mode 2 that has a smaller number of switching times than mode 1, and the switching loss can be reduced.
 図8に、図6よりも系統電流Iacを増加させた場合の動作波形を示す。前述の通り、前記単相ブリッジ回路のリップルの振幅値Irは、Vpn、スイッチング素子21と23のオン時間、Vac、インダクタ70と71の合成インダクタンスから決定され、系統電流Iacとは無関係であることから、リップルの振幅値Irは図6の場合と同様の値である。これに対し、Iacが増加して前記単相ブリッジ回路の平均出力電流Ii(ave)が大きくなったことから、|Ii(ave)|がIrより大きな期間(A)と(D)の時間が広がり、逆に|Ii(ave)|がIrより小さな期間(B),(C),(E),(F)が狭まっている。その結果、モード2で動作する期間が広がり、逆にモード1で動作する期間が狭まっている。つまり、本実施例では、系統電圧のゼロクロスを中心として、前記単相ブリッジ回路の平均出力電流振幅値よりそのリップルの振幅値が大きい期間において、前記期間内ではモード1で動作し、前記期間外ではモード2で動作をする。そして、前記期間は出力電流の大きさに反比例して変化する。 FIG. 8 shows an operation waveform when the system current Iac is increased as compared with FIG. As described above, the ripple amplitude value Ir of the single-phase bridge circuit is determined from Vpn, the ON time of the switching elements 21 and 23, Vac, and the combined inductance of the inductors 70 and 71, and is independent of the system current Iac. Therefore, the amplitude value Ir of the ripple is the same value as in FIG. On the other hand, since Iac is increased and the average output current Ii (ave) of the single-phase bridge circuit is increased, time periods (A) and (D) in which | Ii (ave) | On the contrary, the periods (B), (C), (E), and (F) in which | Ii (ave) | is smaller than Ir are narrowed. As a result, the period for operating in mode 2 is widened, while the period for operating in mode 1 is conversely narrowed. That is, in this embodiment, in the period in which the amplitude value of the ripple is larger than the average output current amplitude value of the single-phase bridge circuit, centering on the zero cross of the system voltage, the mode operates within the period, and the outside of the period Then, it operates in mode 2. The period changes in inverse proportion to the magnitude of the output current.
 以上に説明した通り、本実施例では本発明に関わる動作モード切替手段120を使用することで、系統電圧のゼロクロス付近における系統電流の歪みを抑えると共に、スイッチング素子のスイッチング回数を減らしてスイッチング損失を低減できる。その結果、損失の少ない単相系統連系インバータ装置を提供する効果を得ることができる。 As described above, in this embodiment, by using the operation mode switching means 120 according to the present invention, the distortion of the system current near the zero cross of the system voltage is suppressed, and the switching frequency of the switching element is reduced to reduce the switching loss. Can be reduced. As a result, it is possible to obtain the effect of providing a single-phase grid-connected inverter device with little loss.
 なお、スイッチング素子の損失を低減するため、スイッチングの回数が少ないスイッチング素子20と22には、一般にスイッチング速度は比較的遅いが導通損失の少ないIGBTを用いることが望ましい。また、スイッチング回数の多いスイッチング素子21と23には、一般に高速にスイッチングできてスイッチング損失の少ないMOSFETを用いることが望ましい。これを考慮し、本実施例では、スイッチング素子20と22にはIGBTを用い、スイッチング素子21と23にはMOSFETを用いた。しかし、全てのスイッチング素子についてIGBTもしくはMOSFETを用いてもよく、本実施例のみに限定するものではない。 In order to reduce the loss of the switching element, it is generally desirable to use an IGBT with a relatively low switching speed but a small conduction loss for the switching elements 20 and 22 having a small number of times of switching. For the switching elements 21 and 23 having a large number of times of switching, it is generally desirable to use MOSFETs that can be switched at high speed and have low switching loss. Considering this, in this embodiment, the switching elements 20 and 22 are IGBTs, and the switching elements 21 and 23 are MOSFETs. However, IGBTs or MOSFETs may be used for all switching elements, and the present invention is not limited to this embodiment.
 また、本実施例では単相系統連系インバータで説明したがこの限りでない。単相ブリッジ回路を三相ブリッジ回路に、三相系統の電圧・電流を検知するセンサ、三相に対応したPWM生成手段・リップル検出手段を備えた三相系統連系インバータでも上記制御を行うことで同様の効果が見込める。 In addition, although the present embodiment has been described with a single-phase grid-connected inverter, this is not restrictive. The above control is also performed in a three-phase grid-connected inverter equipped with a single-phase bridge circuit as a three-phase bridge circuit, a sensor that detects the voltage and current of the three-phase system, and a PWM generation means / ripple detection means that supports three phases. The same effect can be expected.
 図9は本発明の第2の実施例による単相系統連系インバータ装置2の構成図である。図9において、図1と同一の構成要素には同一符号を付し、重複説明は避ける。 FIG. 9 is a configuration diagram of the single-phase grid-connected inverter device 2 according to the second embodiment of the present invention. In FIG. 9, the same components as those in FIG.
 図9と図1で異なる点について説明する。スイッチング素子20~23には、それぞれスイッチング素子30~33が並列接続される。つまり、本実施例では、スイッチング素子20とダイオード40とスイッチング素子30、スイッチング素子21とダイオード41とスイッチング素子31、スイッチング素子22とダイオード42とスイッチング素子32、スイッチング素子23とダイオード43とスイッチング素子33が、それぞれ第1スイッチ,第2スイッチ,第3スイッチ,第4スイッチを構成する。そして、スイッチング素子30~33のゲートは制御手段200に接続される。制御手段200は、実施例1で説明した制御手段100が持つ機能を全て備えると共に、スイッチング素子30~33のゲートをドライブする機能を備える。スイッチング素子30と32にはMOSFETを用いる。またスイッチング素子31と33にはIGBTを用いる。本実施例は、スイッチング素子30~33を備えることにより、実施例1よりも更に損失を低減することができる。 The differences between FIG. 9 and FIG. 1 will be described. Switching elements 30 to 33 are connected in parallel to the switching elements 20 to 23, respectively. That is, in this embodiment, the switching element 20, the diode 40 and the switching element 30, the switching element 21 and the diode 41 and switching element 31, the switching element 22 and the diode 42 and switching element 32, the switching element 23 and the diode 43 and the switching element 33. Respectively constitute a first switch, a second switch, a third switch, and a fourth switch. The gates of the switching elements 30 to 33 are connected to the control means 200. The control unit 200 has all the functions of the control unit 100 described in the first embodiment and also has a function of driving the gates of the switching elements 30 to 33. MOSFETs are used for the switching elements 30 and 32. The switching elements 31 and 33 are IGBTs. In the present embodiment, the loss can be further reduced as compared with the first embodiment by including the switching elements 30 to 33.
 次に、本実施例の動作を説明する。各部の動作波形を図10に示す。Vg(30)とVg(32)は、それぞれスイッチング素子30と32のゲート駆動電圧である。スイッチング素子30は期間(C)と(E)中にスイッチングする。また、スイッチング素子32は期間(B)と(F)中にスイッチングする。つまり、スイッチング素子30と32は、単相系統連系インバータ装置2がモード1のときにスイッチングする。そして、Vg(31)とVg(33)は、それぞれスイッチング素子31と33のゲート駆動電圧である。スイッチング素子31と33は、それぞれスイッチング素子21と23とほぼ同様の信号でドライブされるが、オフする時刻に僅かな違いがある。 Next, the operation of this embodiment will be described. The operation waveform of each part is shown in FIG. Vg (30) and Vg (32) are gate drive voltages of the switching elements 30 and 32, respectively. The switching element 30 switches during the periods (C) and (E). Further, the switching element 32 switches during the periods (B) and (F). That is, the switching elements 30 and 32 are switched when the single-phase system interconnection inverter device 2 is in the mode 1. Vg (31) and Vg (33) are gate drive voltages of the switching elements 31 and 33, respectively. The switching elements 31 and 33 are driven by substantially the same signals as the switching elements 21 and 23, respectively, but there is a slight difference in the turn-off time.
 まず、スイッチング素子31と33を付加した効果を説明する。スイッチング素子21と31のスイッチング動作の詳細を図11に示す。Ic(31)はスイッチング素子31のコレクタ-エミッタ間の電流である。また、Id(21)はスイッチング素子21のドレイン-ソース間の電流である。制御手段200がスイッチング素子21と31を時刻t0″で同時にオンすると、それぞれの素子に電流が流れる。一般に、IGBTとMOSFETを比較するとIGBTの方が低抵抗なため、Ic(31)の方がId(21)よりも大きくなる。つまり、スイッチング素子31を付加したことにより、スイッチング素子21の導通損失を低減でき、スイッチング素子21と31とダイオード41で構成された前記第2スイッチの損失を低減できる。 First, the effect of adding the switching elements 31 and 33 will be described. Details of the switching operation of the switching elements 21 and 31 are shown in FIG. Ic (31) is a current between the collector and the emitter of the switching element 31. Id (21) is the current between the drain and source of the switching element 21. When the control means 200 turns on the switching elements 21 and 31 at time t0 ″ at the same time, a current flows through each element. Generally, when comparing IGBT with MOSFET, IGBT has lower resistance, so Ic (31) is more In other words, by adding the switching element 31, the conduction loss of the switching element 21 can be reduced, and the loss of the second switch constituted by the switching elements 21 and 31 and the diode 41 is reduced. it can.
 しかし、一般にIGBTはMOSFETと比較するとターンオフする速度が遅く、IGBTはMOSFETよりもターンオフ損失が大きい。そこで、制御手段200は、スイッチング素子21よりも先にスイッチング素子31のゲートをオフにする。スイッチング素子31のゲートをオフした時刻t1″以降、Ic(31)が低減するとともにId(21)が増加する。時刻t2″でIc(31)はゼロとなる。そして、Id(21)は時刻t1″以前のIc(31)が加算された電流となる。この時刻t1″からt2″の間、スイッチング素子21はオンしているのでスイッチング素子31のコレクタ-エミッタ間にはスイッチング素子21のオン電圧が印加される。一般に、このオン電圧は数V程度であるから、スイッチング素子31のオフ時のスイッチング損失は殆ど発生しない。次に、時刻t3″でスイッチング素子21のゲートをオフにする。 However, in general, the IGBT is turned off slower than the MOSFET, and the IGBT has a larger turn-off loss than the MOSFET. Therefore, the control unit 200 turns off the gate of the switching element 31 before the switching element 21. After time t1 ″ when the gate of the switching element 31 is turned off, Ic (31) decreases and Id (21) increases. At time t2 ″, Ic (31) becomes zero. Id (21) is a current obtained by adding Ic (31) before time t1 ″. Since the switching element 21 is on during this time t1 ″ to t2 ″, the collector-emitter of the switching element 31 In the meantime, the ON voltage of the switching element 21 is applied. Generally, this ON voltage is about several volts, so that almost no switching loss occurs when the switching element 31 is OFF. Next, at time t3 ″, the switching element 21 21 gate is turned off.
 時刻t3″からt4″の間にId(21)は減少してゼロになり、スイッチング素子21にスイッチング損失が発生する。本実施例におけるスイッチング素子21は実施例1と同様にMOSFETを使用していることから、時刻t3″からt4″の間に発生するスイッチング素子21のスイッチング損失は、実施例1の場合と同等である。 From time t3 ″ to t4 ″, Id (21) decreases to zero, and switching loss occurs in the switching element 21. Since the switching element 21 in the present embodiment uses a MOSFET as in the first embodiment, the switching loss of the switching element 21 occurring between the times t3 ″ and t4 ″ is the same as in the first embodiment. is there.
 以上に説明した通り、本実施例では、スイッチング素子31を付加したことによってスイッチング素子21の導通損失を低減でき、スイッチング素子21と31とダイオード41で構成された前記第2スイッチの損失を実施例1よりも低減できる。 As described above, in this embodiment, the addition of the switching element 31 can reduce the conduction loss of the switching element 21, and the loss of the second switch composed of the switching elements 21 and 31 and the diode 41 can be reduced to the embodiment. 1 can be reduced.
 スイッチング素子31のゲートをオフする時刻t1″からスイッチング素子21のゲートをオフする時刻t3″までの時間は、スイッチング素子31がオフする十分な時間とすることが望ましい。例えば、制御手段200に10n秒~1u秒ほどの時間のパルスを発する発振器を備えてそのパルスの時間を利用し、t1″からt3″の時間としてもよい。 It is desirable that the time from the time t1 ″ when the gate of the switching element 31 is turned off to the time t3 ″ when the gate of the switching element 21 is turned off is a sufficient time that the switching element 31 is turned off. For example, the control unit 200 may be provided with an oscillator that emits a pulse having a time of about 10 nsec to 1 usec, and the time of the pulse may be used to set the time from t1 ″ to t3 ″.
 また、スイッチング素子31がオフするのに必要十分な時間は時刻t1″以前にスイッチング素子31に流れていた電流値に比例するから、スイッチング素子31に流れていた電流即ち前記単相ブリッジ回路の出力電流Iiに比例して、前述した発振器が発するパルス幅を変化させることが望ましい。 Further, the time necessary and sufficient for the switching element 31 to turn off is proportional to the current value that has flowed through the switching element 31 before time t1 ″, so that the current that has flowed through the switching element 31, that is, the output of the single-phase bridge circuit. It is desirable to change the pulse width emitted by the oscillator described above in proportion to the current Ii.
 また或いは制御手段200にスイッチング素子31のコレクタ-エミッタ間の電流を検出する電流検出手段を備え、この電流検出手段でスイッチング素子31の電流がゼロになった時刻を検出し、スイッチング素子21をオフしても同様の効果を得ることができる。 Alternatively, the control means 200 is provided with a current detection means for detecting the current between the collector and the emitter of the switching element 31, and this current detection means detects the time when the current of the switching element 31 becomes zero and turns off the switching element 21. However, the same effect can be obtained.
 更に、本実施例ではスイッチング素子21と31をオンする時刻を同時としたが、一般にIGBTとMOSFETを比較した場合に両者のターンオンする速度に大きな差はないことから、どちらを先にオンさせてもよい。 Furthermore, in the present embodiment, the switching elements 21 and 31 are turned on at the same time. In general, however, there is no significant difference in the turn-on speed between the IGBT and the MOSFET, so whichever is turned on first. Also good.
 なお、スイッチング素子23と33のスイッチング動作は、図11中のVg(21),Vg(31),Ic(21),Id(31)を、それぞれVg(23),Vg(33),Ic(23),Id(33)と読み替えたものと同様であり、その説明は省略する。スイッチング素子33を付加したことによってスイッチング素子23の導通損失を低減でき、スイッチング素子23と33とダイオード43で構成された前記第4スイッチの損失を低減できる。 Note that the switching operation of the switching elements 23 and 33 is performed by changing Vg (21), Vg (31), Ic (21), and Id (31) in FIG. 11 to Vg (23), Vg (33), and Ic ( 23) and Id (33), and the description thereof is omitted. By adding the switching element 33, the conduction loss of the switching element 23 can be reduced, and the loss of the fourth switch composed of the switching elements 23 and 33 and the diode 43 can be reduced.
 次に、スイッチング素子30と32を付加した効果を説明する。図10に示した通り、スイッチング素子30は期間(C)と(E)でのみスイッチングし、スイッチング素子32は期間(B)と(F)でのみスイッチングする。 Next, the effect of adding the switching elements 30 and 32 will be described. As shown in FIG. 10, the switching element 30 switches only in the periods (C) and (E), and the switching element 32 switches only in the periods (B) and (F).
 スイッチング素子32を付加した際の期間(B)と(F)における動作を、先に示した図3を参照しながら説明する。ここでは図3中のVg(22)をVg(32)に読み替えるものとする。 The operation in the periods (B) and (F) when the switching element 32 is added will be described with reference to FIG. Here, Vg (22) in FIG. 3 is read as Vg (32).
 スイッチング素子32には、Vg(32)がオンしている時刻t1からt3の間に電流が流れる。まず、時刻t1-t2において、スイッチング素子23と33がオフ、スイッチング素子32がオンしているときは、スイッチング素子20→インダクタ70→コンデンサ61→インダクタ71→ダイオード42とスイッチング素子32の経路で電流が流れる。つまり、スイッチング素子32はMOSFETであることからソースからドレインに電流を流すことができる。これにより、ダイオード42に流れる電流が減って、スイッチング素子22と32とダイオード42で構成された前記第2スイッチの損失を低減できる。 Current flows through the switching element 32 from time t1 to time t3 when Vg (32) is on. First, at time t1-t2, when the switching elements 23 and 33 are off and the switching element 32 is on, the current flows through the path of the switching element 20 → the inductor 70 → the capacitor 61 → the inductor 71 → the diode 42 and the switching element 32. Flows. That is, since the switching element 32 is a MOSFET, a current can flow from the source to the drain. Thereby, the current flowing through the diode 42 is reduced, and the loss of the second switch constituted by the switching elements 22 and 32 and the diode 42 can be reduced.
 時刻t2-t3において、スイッチング素子32がオン、スイッチング素子23と33がオフしているときは、コンデンサ61→インダクタ70→ダイオード40→スイッチング素子22と32→インダクタ71の経路で電流が流れる。つまり、スイッチング素子22と32で電流が分流し、スイッチング素子22と32とダイオード42で構成された前記第2スイッチの損失を低減できる。 At time t2-t3, when the switching element 32 is on and the switching elements 23 and 33 are off, a current flows through the path of the capacitor 61 → the inductor 70 → the diode 40 → the switching elements 22 and 32 → the inductor 71. That is, current is shunted by the switching elements 22 and 32, and the loss of the second switch constituted by the switching elements 22 and 32 and the diode 42 can be reduced.
 次に、スイッチング素子30を付加した際の期間(C)と(E)の動作を、先に示した図4を参照しながら説明する。ここでは図4中のVg(20)をVg(30)に読み替えるものとする。 Next, the operation in the periods (C) and (E) when the switching element 30 is added will be described with reference to FIG. 4 described above. Here, it is assumed that Vg (20) in FIG. 4 is read as Vg (30).
 スイッチング素子30には、Vg(30)がオンの間である時刻t1′からt3′の間に電流が流れる。まず、時刻t1′-t2′において、スイッチング素子21と31がオフ、スイッチング素子30がオンしているときは、スイッチング素子22→インダクタ71→コンデンサ61→インダクタ70→ダイオード40とスイッチング素子30の経路で電流が流れる。つまり、スイッチング素子30はMOSFETであることからソースからドレインに電流を流すことができる。これにより、ダイオード40に流れる電流が減って、スイッチング素子20と30とダイオード40で構成された前記第1スイッチの損失を低減できる。 The current flows through the switching element 30 from time t1 ′ to t3 ′ when Vg (30) is on. First, at time t1′-t2 ′, when switching elements 21 and 31 are off and switching element 30 is on, switching element 22 → inductor 71 → capacitor 61 → inductor 70 → path of diode 40 and switching element 30 Current flows. That is, since the switching element 30 is a MOSFET, a current can flow from the source to the drain. Thereby, the current flowing through the diode 40 is reduced, and the loss of the first switch constituted by the switching elements 20 and 30 and the diode 40 can be reduced.
 時刻t2′-t3′において、スイッチング素子30がオン、スイッチング素子21と31がオフしているときは、コンデンサ61→インダクタ71→ダイオード42→スイッチング素子20と30→インダクタ70の経路で電流が流れる。つまり、スイッチング素子20と30で電流が分流し、スイッチング素子20と30とダイオード40で構成された前記第1スイッチの損失を低減できる。 At time t2′-t3 ′, when switching element 30 is on and switching elements 21 and 31 are off, current flows through the path of capacitor 61 → inductor 71 → diode 42 → switching elements 20 and 30 → inductor 70. . That is, the current is shunted by the switching elements 20 and 30, and the loss of the first switch constituted by the switching elements 20 and 30 and the diode 40 can be reduced.
 以上に説明した通り、本実施例は、スイッチング素子30~33を備えることにより、実施例1よりも更に損失を低減することができる。特に、スイッチング素子31と33は、大電流領域(図10の期間(A),(D))でスイッチングするスイッチング素子21と23の損失を低減しており、損失を低減する効果が大きい。これらの結果、本実施例においても、損失の少ない単相系統連系インバータ装置を提供する効果を得ることができる。 As described above, this embodiment can further reduce the loss compared to the first embodiment by including the switching elements 30 to 33. In particular, the switching elements 31 and 33 reduce the loss of the switching elements 21 and 23 that switch in a large current region (periods (A) and (D) in FIG. 10), and the effect of reducing the loss is great. As a result, also in the present embodiment, it is possible to obtain an effect of providing a single-phase grid-connected inverter device with little loss.
 また、本実施例では単相系統連系インバータで説明したがこの限りでない。単相ブリッジ回路を三相ブリッジ回路に、三相系統の電圧・電流を検知するセンサ、三相に対応したPWM生成手段・リップル検出手段を備えた三相系統連系インバータでも上記制御を行うことで同様の効果が見込める。 In addition, although the present embodiment has been described with a single-phase grid-connected inverter, this is not restrictive. The above control is also performed in a three-phase grid-connected inverter equipped with a single-phase bridge circuit as a three-phase bridge circuit, a sensor that detects the voltage and current of the three-phase system, and a PWM generation means / ripple detection means that supports three phases. The same effect can be expected.
 図12は本発明の第3の実施例による分散電源システムの構成図である。300は分散電源システムである。301は、実施例1で示した単相系統連系インバータ装置1あるいは実施例2で示した単相系統連系インバータ装置2である。11は太陽電池パネルである。 FIG. 12 is a configuration diagram of a distributed power supply system according to a third embodiment of the present invention. Reference numeral 300 denotes a distributed power supply system. Reference numeral 301 denotes the single-phase grid-connected inverter device 1 shown in the first embodiment or the single-phase grid-connected inverter device 2 shown in the second embodiment. 11 is a solar cell panel.
 太陽電池パネル11は、実施例1と2における直流電源10に相当する。11は、太陽電池パネルのみならず、直流の電圧源であればなんでもよく、例えば、燃料電池や風力発電機の交流出力を直流に整流したものでもよい。 The solar cell panel 11 corresponds to the DC power source 10 in Examples 1 and 2. 11 is not limited to a solar cell panel, but may be any DC voltage source. For example, the AC output of a fuel cell or wind power generator may be rectified to DC.
 分散電源システム300は、実施例1で説明した単相系統連系インバータ装置1あるいは実施例2で示した単相系統連系インバータ装置2を備えていることから、従来の分散電源システムより電力損失が少なくて発熱量が少ない。このため、従来よりも放熱器や冷却ファンを小さくでき、小型で損失の少ない分散電源システムとすることができた。 Since the distributed power system 300 includes the single-phase grid-connected inverter device 1 described in the first embodiment or the single-phase grid-connected inverter device 2 described in the second embodiment, the power loss is higher than that of the conventional distributed power system. There is little heat generation. For this reason, a heatsink and a cooling fan can be made smaller than before, and a compact and low-loss distributed power supply system can be obtained.
 なお、本発明は前述した実施例に限定されるものではなく、様々な変形例が含まれる。例えば、前述した実施例は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 In addition, this invention is not limited to the Example mentioned above, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.
 また、前述した各構成や機能等は、それらの一部または全部を、例えば集積回路で設計する等によりハードウェアで実現してもよい。また、前述した各構成や機能等は、プロセッサがそれぞれの機能を実現するプログラムを解釈して実行することにより、ソフトウェアで実現してもよい。各機能を実現するプログラムの情報は、メモリ,ハードディスク,SSD(Solid State Drive)などの記録装置、または、ICカード,SDカード,DVD等の記録媒体に置くことができる。 In addition, each of the above-described configurations, functions, and the like may be realized in hardware by designing a part or all of them, for example, with an integrated circuit. Further, each of the above-described configurations, functions, and the like may be realized by software by a processor interpreting and executing a program that realizes each function. Information on the program that realizes each function can be stored in a recording device such as a memory, a hard disk, or an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
 また、制御線や情報線は説明上必要と考えられるものを示しており、製品上必ずしもすべての制御線や情報線を示しているとは限らない。実際には殆ど全ての構成が相互に接続されていると考えてよい。 In addition, the control lines and information lines indicate what is considered necessary for the explanation, and not all control lines and information lines on the product are necessarily shown. In practice, it can be considered that almost all the components are connected to each other.
1,2,301 単相系統連系インバータ装置
10 直流電源
11 太陽電池パネル
20~23,30~33 スイッチング素子
40~43 ダイオード
60 バイパスコンデンサ
61 コンデンサ
70,71 インダクタ
80 商用系統
90,91 電流センサ
100,200 制御手段
101,103 電流検出手段
102,104 電圧検出手段
105 ドライブ手段
106,107 PWM生成手段
108 系統連系制御手段
109 切替手段
110 比較手段
111,112 リップル検出手段
120 動作モード切替手段
300 分散電源システム
1, 2, 301 Single-phase grid-connected inverter device 10 DC power source 11 Solar cell panels 20 to 23, 30 to 33 Switching elements 40 to 43 Diode 60 Bypass capacitor 61 Capacitor 70, 71 Inductor 80 Commercial system 90, 91 Current sensor 100 , 200 Control means 101, 103 Current detection means 102, 104 Voltage detection means 105 Drive means 106, 107 PWM generation means 108 System interconnection control means 109 Switching means 110 Comparison means 111, 112 Ripple detection means 120 Operation mode switching means 300 Dispersion Power system

Claims (10)

  1.  ブリッジ回路とフィルタ回路と前記ブリッジ回路を制御する制御手段とを有し、直流電源から得た電力を前記ブリッジ回路、前記フィルタ回路の順に介して商用系統に供給するための系統連系インバータ装置において、
     前記ブリッジ回路は複数のスイッチからなり、
     前記制御手段は、前記商用系統の電圧のゼロクロス点を基点として所定の期間前から所定期間経過後までの期間で前記商用系統を流れる電流の歪みが抑えられるように前記スイッチを制御するモード1と、所定期間経過後から次の所定期間前までの期間で前記スイッチの損失を低減するように前記スイッチを制御するモード2とを有することを特徴とする系統連系インバータ装置。
    In a grid-connected inverter device having a bridge circuit, a filter circuit, and a control means for controlling the bridge circuit, and supplying power obtained from a DC power source to a commercial system through the bridge circuit and the filter circuit in this order ,
    The bridge circuit comprises a plurality of switches,
    The control means controls the switch so that distortion of the current flowing through the commercial system is suppressed in a period from a predetermined period before a predetermined period has elapsed with a zero cross point of the commercial system voltage as a base point; And a mode 2 for controlling the switch so as to reduce the loss of the switch during a period from the elapse of a predetermined period to the next predetermined period.
  2.  請求項1に記載の系統連系インバータ装置において、
     前記ブリッジ回路は、直列接続された第1のスイッチと第2のスイッチの両端と、直列接続された第3のスイッチと第4のスイッチの両端を直流電源の両端に接続して構成され、
     前記制御手段は、前記モード1において、前記商用系統の電圧が正のときに、前記第1のスイッチをオンすると共に前記第2のスイッチをオフかつ前記第3と前記第4のスイッチを相補PWMし、前記商用系統の電圧が負のときに、前記第3のスイッチをオンすると共に前記第4のスイッチをオフかつ前記第1と前記第2のスイッチを相補PWMし、
     前記制御手段は、前記モード2において、前記商用系統の電圧が正のときに、前記第1のスイッチをオンすると共に前記第2のスイッチと前記第3のスイッチをオフかつ前記第4のスイッチをPWMし、前記商用系統の電圧が負のときに、前記第3のスイッチをオンすると共に前記第4のスイッチと前記第1のスイッチをオフかつ前記第2のスイッチをPWMすることを特徴とする系統連系インバータ装置。
    In the grid interconnection inverter device according to claim 1,
    The bridge circuit is configured by connecting both ends of a first switch and a second switch connected in series, and both ends of a third switch and a fourth switch connected in series to both ends of a DC power supply,
    In the mode 1, when the voltage of the commercial system is positive, the control means turns on the first switch, turns off the second switch, and complements the third and fourth switches. When the voltage of the commercial system is negative, the third switch is turned on and the fourth switch is turned off, and the first and second switches are complementary PWMed,
    In the mode 2, when the voltage of the commercial system is positive, the control means turns on the first switch, turns off the second switch and the third switch, and turns off the fourth switch. PWM is performed, and when the voltage of the commercial system is negative, the third switch is turned on, the fourth switch and the first switch are turned off, and the second switch is PWMed. Grid-connected inverter device.
  3.  ブリッジ回路とフィルタ回路と前記ブリッジ回路を制御する制御手段とを有し、直流電源から得た電力を前記ブリッジ回路、前記フィルタ回路の順に介して商用系統に供給するための系統連系インバータ装置において、
     前記ブリッジ回路は、第1のスイッチと第2のスイッチと第3のスイッチと第4のスイッチとからなり、
     前記直流電源の両端は、直列接続された第1のスイッチと第2のスイッチの両端と、直列接続された第3のスイッチと第4のスイッチの両端とに接続され、
     前記第1のスイッチと前記第2のスイッチの接続点と、前記第3のスイッチと前記第4のスイッチの接続点は前記フィルタ回路に接続され、
     前記フィルタ回路は前記商用系統に接続され、
     前記制御手段は、前記商用系統の電圧のゼロクロス点を基点として所定の期間前から所定期間経過後までの期間において、前記商用系統の電圧が正のときに、前記第1のスイッチをオンすると共に前記第2のスイッチをオフかつ前記第3と前記第4のスイッチを相補PWMし、前記商用系統の電圧が負のときに、前記第3のスイッチをオンすると共に前記第4のスイッチをオフかつ前記第1と前記第2のスイッチを相補PWMするモード1と、所定期間経過後から次の所定期間前までの期間において、前記商用系統の電圧が正のときに、前記第1のスイッチをオンすると共に前記第2のスイッチと前記第3のスイッチをオフかつ前記第4のスイッチをPWMし、前記商用系統の電圧が負のときに、前記第3のスイッチをオンすると共に前記第4のスイッチと前記第1のスイッチをオフかつ前記第2のスイッチをPWMするモード2とを有することを特徴とする系統連系インバータ装置。
    In a grid-connected inverter device having a bridge circuit, a filter circuit, and a control means for controlling the bridge circuit, and supplying power obtained from a DC power source to a commercial system through the bridge circuit and the filter circuit in this order ,
    The bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch,
    Both ends of the DC power supply are connected to both ends of a first switch and a second switch connected in series, and both ends of a third switch and a fourth switch connected in series,
    The connection point of the first switch and the second switch, the connection point of the third switch and the fourth switch are connected to the filter circuit,
    The filter circuit is connected to the commercial system,
    The control means turns on the first switch when the voltage of the commercial system is positive during a period from a predetermined period before a predetermined period with the zero cross point of the commercial system voltage as a base point. When the second switch is turned off and the third and fourth switches are complementarily PWMed, when the voltage of the commercial system is negative, the third switch is turned on and the fourth switch is turned off. In mode 1 for complementary PWM of the first and second switches, and when the voltage of the commercial system is positive during a period from the lapse of a predetermined period to the next predetermined period, the first switch is turned on. In addition, the second switch and the third switch are turned off and the fourth switch is PWMed. When the voltage of the commercial system is negative, the third switch is turned on and the second switch is turned on. Switch and the system interconnection inverter device and having a mode 2 for PWM the first off and the second switch switches.
  4.  請求項1乃至3の何れかに記載の系統連系インバータ装置において、
     前記モード1と前記モード2を切り替える動作モード切替手段と、前記ブリッジ回路の出力電流のリップルの振幅値を検出するリップル検出手段を備え、
     前記ブリッジ回路の平均出力電流振幅値よりも前記ブリッジ回路の出力電流のリップルの振幅値が大きい期間を、前記商用系統の電圧のゼロクロス点を基点とした所定の期間前から所定期間経過後までの期間とし、
     前記ブリッジ回路の平均出力電流振幅値よりも前記ブリッジ回路の出力電流のリップルの振幅値が小さい期間を、前記所定期間経過後から次の所定期間前までの期間とすることを特徴とする系統連系インバータ装置。
    In the grid connection inverter apparatus in any one of Claims 1 thru | or 3,
    An operation mode switching unit that switches between the mode 1 and the mode 2, and a ripple detection unit that detects an amplitude value of a ripple of an output current of the bridge circuit;
    A period in which the amplitude value of the ripple of the output current of the bridge circuit is larger than the average output current amplitude value of the bridge circuit, from a predetermined period based on the zero crossing point of the voltage of the commercial system to after a predetermined period has elapsed. Period and
    A period in which the amplitude value of the ripple of the output current of the bridge circuit is smaller than the average output current amplitude value of the bridge circuit is a period from the lapse of the predetermined period to the next predetermined period. System inverter device.
  5.  請求項4に記載の系統連系インバータ装置において、前記リップル検出手段は、前記直流電源の電圧と、前記商用系統の電圧と、前記第2のスイッチあるいは前記第4のスイッチのオン時間を基に、前記ブリッジ回路における出力電流のリップルの振幅値を演算する機能を備えたことを特徴とする系統連系インバータ装置。 5. The grid interconnection inverter device according to claim 4, wherein the ripple detection means is based on the voltage of the DC power supply, the voltage of the commercial system, and the ON time of the second switch or the fourth switch. A grid-connected inverter device comprising a function of calculating an amplitude value of a ripple of an output current in the bridge circuit.
  6.  請求項4に記載の系統連系インバータ装置において、前記リップル検出手段は、前記商用系統の周波数をカットするハイパスフィルタと砲絡線検波回路を備えたことを特徴とする系統連系インバータ装置。 5. The grid interconnection inverter apparatus according to claim 4, wherein the ripple detection means includes a high-pass filter that cuts off the frequency of the commercial grid and an arc detector circuit.
  7.  請求項2又は3に記載の系統連系インバータ装置において、
     前記第1および第3のスイッチはIGBTとダイオードで構成され、前記第2および第4のスイッチはMOSFETとダイオードで構成されたことを特徴とする系統連系インバータ装置。
    In the grid connection inverter apparatus of Claim 2 or 3,
    The grid-connected inverter device, wherein the first and third switches are composed of IGBTs and diodes, and the second and fourth switches are composed of MOSFETs and diodes.
  8.  請求項2又は3に記載の系統連系インバータ装置において、
     前記第1~第4のスイッチをIGBTとMOSFETとダイオードで構成し、
     前記制御装置は、前記商用系統の電圧のゼロクロス点を基点として所定の期間前から所定期間経過後までの期間では、前記第1のスイッチのMOSFETを前記第2のスイッチと相補PWMさせ、前記第3のスイッチのMOSFETを前記第4のスイッチと相補PWMさせると共に、
     前記第2および第4のスイッチのIGBTを、前記第2および第4のスイッチのMOSFETよりも10n~1u秒先にオフさせることを特徴とする系統連系インバータ装置。
    In the grid connection inverter apparatus of Claim 2 or 3,
    The first to fourth switches are composed of IGBT, MOSFET and diode,
    The control device causes the MOSFET of the first switch to perform complementary PWM with the second switch in a period from a predetermined period before a predetermined period with a zero cross point of the commercial system voltage as a base point, and the second switch 3 and a complementary PWM with the fourth switch MOSFET,
    A grid-connected inverter device, wherein the IGBTs of the second and fourth switches are turned off 10 n to 1 u seconds before the MOSFETs of the second and fourth switches.
  9.  請求項1乃至8のいずれか1項に記載の系統連系インバータ装置を備えたことを特徴とする分散型電源システム。 A distributed power supply system comprising the grid-connected inverter device according to any one of claims 1 to 8.
  10.  請求項9に記載の分散型電源システムにおいて、前記系統連系インバータ装置の前記直流電源が太陽電池パネルであることを特徴とする分散型電源システム。 10. The distributed power supply system according to claim 9, wherein the DC power supply of the grid-connected inverter device is a solar battery panel.
PCT/JP2011/002606 2011-05-11 2011-05-11 Grid-connected inverter device, and distributed power source system provided with grid-connected inverter device WO2012153368A1 (en)

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