JPS5814758B2 - multilayer wiring board - Google Patents

multilayer wiring board

Info

Publication number
JPS5814758B2
JPS5814758B2 JP52100162A JP10016277A JPS5814758B2 JP S5814758 B2 JPS5814758 B2 JP S5814758B2 JP 52100162 A JP52100162 A JP 52100162A JP 10016277 A JP10016277 A JP 10016277A JP S5814758 B2 JPS5814758 B2 JP S5814758B2
Authority
JP
Japan
Prior art keywords
inner layer
copper foil
hole
multilayer wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52100162A
Other languages
Japanese (ja)
Other versions
JPS5434061A (en
Inventor
山田和雄
柄崎晃一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP52100162A priority Critical patent/JPS5814758B2/en
Publication of JPS5434061A publication Critical patent/JPS5434061A/en
Publication of JPS5814758B2 publication Critical patent/JPS5814758B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 この発明は多層配線基板に関するものである。[Detailed description of the invention] This invention relates to a multilayer wiring board.

一般に多層配線基板は、まず内層にあたる銅張積層板に
周知の印刷蝕刻法で回路パターンを形成し、次いで外層
にあたる銅張積層板と相互に位置合わせし、合成樹脂含
浸ガラス布を介してサンドインチ構造に形成した後、熱
圧着積層プレスを使って加熱圧着して各層の積層板を一
体化し、その後スルーホール法によって内部回路の導通
を図るのが普通である。
In general, multilayer wiring boards are manufactured by first forming a circuit pattern on the inner copper-clad laminate using a well-known printing and etching method, then aligning the circuit pattern with the outer copper-clad laminate, and then sand-inching it through synthetic resin-impregnated glass cloth. After forming the structure, it is common to heat and press the laminated plates using a thermocompression laminating press to integrate the laminated plates of each layer, and then to establish conduction of internal circuits using the through-hole method.

ところが、一体化した積層板にスルーホール法によって
孔明けをおこなう際、孔内の内層銅箔上に、孔明け加工
の切削熱で溶融した絶縁物である樹脂が付着し、孔明け
作業に引き続いておこなわれる孔内壁の銅めっき形成の
際、前述の樹脂の付着が原因で、内層銅箔とめっきの間
の電気的接続が不完全になり、多層配線基板として欠陥
商品になる。
However, when drilling holes in an integrated laminate using the through-hole method, resin, which is an insulator melted by the cutting heat of the hole drilling process, adheres to the inner layer copper foil in the hole, and the hole continues to be drilled. When forming copper plating on the inner wall of the hole, the electrical connection between the inner layer copper foil and the plating becomes incomplete due to the adhesion of the resin described above, resulting in a defective product as a multilayer wiring board.

したがって、孔明け作業において内層銅箔上に樹脂を融
着させないため、従来は、切削性の良いドリルをその摩
耗限界まで使用することなく、非常に無駄と思われる条
件で使用すると共に、例え樹脂が内層銅箔上に融着して
も除去できるような処理工程を後工程に設けることによ
り、この問題を克服する努力がなされてきた。
Therefore, in order to prevent the resin from being fused onto the inner layer copper foil during hole-drilling work, conventional drills with good cutting performance were not used to their wear limits, and were used under conditions that seemed to be extremely wasteful. Efforts have been made to overcome this problem by providing a post-processing step that can remove even if the inner copper foil is fused onto the inner layer copper foil.

しかし、使用するドリルの切削性のバラツキおよび孔明
け条件の変動、融着した樹脂を除去する後工程の処理の
バラツキなどのために、多数生産される多層配線基板の
全ての孔内の内層銅箔上に、融着樹脂の存在を皆無にす
ることは非常に難かしく、高価な多層配線基板が、これ
が原因で導通不良になることがたびたびあった。
However, due to variations in the machinability of the drills used, variations in the drilling conditions, and variations in the post-processing process for removing fused resin, the inner layer copper in all the holes of multilayer wiring boards produced in large numbers is It is very difficult to completely eliminate the presence of fusion resin on the foil, and expensive multilayer wiring boards often suffer from poor conductivity due to this.

この発明は、上述のような事情にかんがみてなされたも
のであり、内層銅箔とめっきの間の電気的接続の信頼性
の高い多層配線基板の提供を目的としている。
This invention was made in view of the above-mentioned circumstances, and aims to provide a multilayer wiring board with high reliability of electrical connection between inner layer copper foil and plating.

次に図を参照してこの発明を詳しく説明する。Next, the present invention will be explained in detail with reference to the drawings.

第1図は積層接着した多層配線基板にドリルで孔明けを
おこなった後の従来普通の基板断面を示す図であり、第
2図は、その後、内層と外層の導通を図るべく孔内壁に
銅めっきをおこなった後の従来普通の基板断面を示す図
である。
Figure 1 is a diagram showing a cross section of a conventional ordinary board after drilling a hole in a laminated and bonded multilayer wiring board. FIG. 2 is a diagram showing a cross section of a conventional conventional substrate after plating has been performed.

第1図および第2図において、1は多層配線基板、2は
孔、3は内層銅箔、4は絶縁基材、5は孔2の内壁銅め
っきを示す。
In FIGS. 1 and 2, 1 is a multilayer wiring board, 2 is a hole, 3 is an inner layer copper foil, 4 is an insulating base material, and 5 is an inner wall copper plating of the hole 2.

第3図は、第2図の円内に示した部分の拡大図であり、
内層銅箔3と孔内壁銅めつき5との断面接続形状の関係
を示す。
Figure 3 is an enlarged view of the part shown in the circle in Figure 2;
The relationship between the cross-sectional connection shapes between the inner layer copper foil 3 and the hole inner wall copper plating 5 is shown.

通常の内層銅箔3の断面形状は、第3図に示す如く、内
層銅箔3そのままの寸法厚で孔内壁銅めつき5とほゞ直
交して接続している。
As shown in FIG. 3, the normal cross-sectional shape of the inner layer copper foil 3 is connected almost orthogonally to the hole inner wall copper plating 5 with the dimensions and thickness of the inner layer copper foil 3 as it is.

第4図は、内層銅箔3と孔内壁銅めつき5との接続面積
が融着した樹脂6の存在によって大幅に減少した状況を
示す。
FIG. 4 shows a situation where the connection area between the inner layer copper foil 3 and the hole inner wall copper plating 5 is significantly reduced due to the presence of the fused resin 6.

第4図の例では、第3図に示した如き正常の接続面積に
比較して約1/2の接続面積に減少するため、このよう
な多層配線基板1の内層接続の電気的信頼性は当然低下
することが予想される。
In the example shown in FIG. 4, the connection area is reduced to about 1/2 compared to the normal connection area as shown in FIG. Naturally, it is expected that this will decline.

そこで、例え内層銅箔3上に樹脂6が融着したとしても
、必要充分な内層接続面積が確保できるように、孔内壁
に面した内層銅箔部分のみを、内層銅箔の厚さ方向に押
し広げることができれば多層配線基板1の内層接続の信
頼性は高くなるはずである。
Therefore, even if the resin 6 is fused onto the inner layer copper foil 3, in order to ensure a necessary and sufficient inner layer connection area, only the inner layer copper foil portion facing the inner wall of the hole should be fused in the thickness direction of the inner layer copper foil. If it can be expanded, the reliability of the inner layer connections of the multilayer wiring board 1 should be increased.

この発明は、上記の点に着目し、多層配線基板1の内層
銅箔3の孔内壁に面する部分が、内層銅箔の厚み方向に
広げられた形状とすることにより内層銅箔とめっきとの
接続面積を大幅に増大し、接続の信頼性を高めた多層配
線基板を提供することにある。
This invention focuses on the above points, and the part of the inner layer copper foil 3 of the multilayer wiring board 1 facing the inner wall of the hole is shaped to expand in the thickness direction of the inner layer copper foil, thereby making it possible to improve the relationship between the inner layer copper foil and the plating. An object of the present invention is to provide a multilayer wiring board that has a significantly increased connection area and improved connection reliability.

第5図は、この発明の実施により、内層銅箔の孔内壁に
面する部分が内層の厚み方向に押し広げられた状況を示
す図であり、7がその押し広げられた内層銅箔部分を示
す。
FIG. 5 is a diagram showing a situation in which the portion of the inner layer copper foil facing the inner wall of the hole is expanded in the thickness direction of the inner layer by implementing the present invention, and 7 shows the expanded inner layer copper foil portion. show.

第5図に示した例では押し広げられた内層銅箔7の存在
により、内層銅箔3とめつき部分5との接続面積が通常
時の約2倍になり、例え内層銅箔3上に、第4図に示し
たのと同程度の樹脂6が融着したとしても、内層接続面
積は第3図に示した如き通常の接続面積に比べ、約1.
5倍になるため接続の信頼性は充分なものとなる。
In the example shown in FIG. 5, due to the expanded inner layer copper foil 7, the connection area between the inner layer copper foil 3 and the mating portion 5 is approximately twice that of the normal one. Even if the same amount of resin 6 as shown in FIG. 4 is fused, the inner layer connection area will be approximately 1.5 mm larger than the normal connection area as shown in FIG.
Since the number of connections increases by five times, the reliability of the connection is sufficient.

次に、この発明の実施に際し用いられる工具の詳細と発
明実施のデータを詳しく説明する。
Next, details of tools used in carrying out the invention and data for carrying out the invention will be explained in detail.

第8図は、この発明の実施に際し用いられる、孔明け作
業用のドリルの形状を示す側面図である。
FIG. 8 is a side view showing the shape of a drill for drilling, which is used in carrying out the present invention.

第8図において、Sはシャンク部分、Fはフルート部分
、D0はフルート部分のドリル先端径、D1はシャンク
部手前のフルート部分のドリル径を示す。
In FIG. 8, S represents the shank portion, F represents the flute portion, D0 represents the drill tip diameter of the flute portion, and D1 represents the drill diameter of the flute portion in front of the shank portion.

一般に、ドリルによる切削の進行にともなって孔を押し
広げると同時に内層銅箔を押し広げるためには、フルー
ト部分の径が先端からシャンク部分に近づくにつれ大き
くなったものを用いるのがよいと考えられた。
Generally, in order to expand the hole and simultaneously expand the inner copper foil as cutting progresses, it is considered best to use a flute whose diameter increases from the tip to the shank. Ta.

そこで、一例として、フルート長F=9.0mm、先端
ドリル径Do=0.9mm、シャンク部手前のフルート
部分のドリル径D1=1.0mm、であってフルート部
分Fの径がドリル先端からシャンク方向に向かって徐々
に大きくなった構造のドリルを使用し、内層銅箔厚がそ
れぞれ異なった4種類の多層配線基板に孔明けをおこな
い、それぞれの基板の孔内壁の内層銅箔の断面形状を金
属頒微鏡を用いて観察しだ結果、予想した通りかなり厚
さ方向に押し広げられた形状を内層銅箔がもつことが分
った。
Therefore, as an example, the flute length F = 9.0 mm, the tip drill diameter Do = 0.9 mm, the drill diameter D1 of the flute portion in front of the shank portion = 1.0 mm, and the diameter of the flute portion F is from the drill tip to the shank. Using a drill with a structure that gradually increases in size in the direction of As a result of observation using a metal distribution microscope, it was found that the inner layer copper foil had a shape that was considerably expanded in the thickness direction, as expected.

内層銅箔厚t(単位ミクロン)と厚さ方向に押し広げら
れた部分の最大銅箔厚tMAX(単位ミクロン)を金属
顕微鏡を使用して測定した結果を第6図に示す。
FIG. 6 shows the results of measuring the inner layer copper foil thickness t (unit: microns) and the maximum copper foil thickness tMAX (unit: microns) of the portion expanded in the thickness direction using a metallurgical microscope.

第6図において、横軸は内層銅箔厚tをとり、縦軸は孔
内壁向の最大銅箔厚tMAXをとっている。
In FIG. 6, the horizontal axis represents the inner layer copper foil thickness t, and the vertical axis represents the maximum copper foil thickness tMAX in the direction of the inner wall of the hole.

第6図から分るように、tMAxはtに対して常に約2
5ミクロン大きく、例えば内層銅箔厚tが20ミクロン
の場合、孔内壁面の最大銅箔厚tMAXは45ミクロン
であり、孔内壁の内層銅箔は厚さ方向に押し広げられて
その内層の接続面積が約2.3倍に増大したことが分る
As can be seen from Figure 6, tMAX is always about 2 with respect to t.
If the inner layer copper foil thickness t is 5 microns larger, for example, 20 microns, the maximum copper foil thickness tMAX on the inner wall of the hole is 45 microns, and the inner layer copper foil on the inner wall of the hole is pushed out in the thickness direction and the inner layer is connected. It can be seen that the area has increased approximately 2.3 times.

このような結果を示した上記4種類の多層配線基板は、
孔内壁に銅めっきをおこなった後、外層パターンを形成
する周知の印刷蝕刻工程を経て完成され、内層接続部の
信頼性を評価する試験サンプルに供した。
The above four types of multilayer wiring boards that showed such results are:
After copper plating was performed on the inner wall of the hole, a well-known printing and etching process was performed to form an outer layer pattern, which was then completed and used as a test sample to evaluate the reliability of the inner layer connection.

また同時に従来の製造方法で製造した同様の多層配線基
板がその比較サンプルとして供された。
At the same time, a similar multilayer wiring board manufactured using a conventional manufacturing method was provided as a comparison sample.

多層配線基板の内層銅箔と孔内壁銅めっきとの接続の信
頼性を評価する試験方法は、各糧文献に報告されている
ごとく数多くあるが、本発明者は長年の経験から、26
0℃一定温度に保持された溶融はんだ上に試験サンプル
を10秒間浮かべた後取りあげ、デシケータ内に4時間
放置して室温まで冷却する所謂はんだ耐熱試験を採用し
た。
There are many test methods for evaluating the reliability of the connection between the inner layer copper foil of a multilayer wiring board and the copper plating on the inner wall of the hole, as reported in various literature.
A so-called solder heat resistance test was employed in which a test sample was floated on molten solder kept at a constant temperature of 0° C. for 10 seconds, then taken up, and left in a desiccator for 4 hours to cool to room temperature.

また内層接続の評価は、内層と接続した二つの孔間の直
流抵抗をミリオーム計を使用して4端子法で測定するこ
とによって、接続が不完全になる現象を直流抵抗値の増
加としてとらえ、その良否の判定は、試験にかける前の
測定値R0(単位ミリオーム)に対する試験後の測定値
R(単位はミリオーム)の比が、R/R0>1.2とな
る測定点を接続異常の起きた点とみなした。
In addition, the inner layer connection can be evaluated by measuring the DC resistance between the two holes connected to the inner layer using a 4-terminal method using a milliohmmeter, and capturing the phenomenon of incomplete connection as an increase in the DC resistance value. The quality of the test is determined by connecting the measurement point where the ratio of the measured value R0 (unit: milliohm) after the test to the measured value R0 (unit: milliohm) before the test is R/R0 > 1.2. It was considered as a point.

第7図は、この発明を実施して製作した試験サンプルと
従来の製造方法で製作した比較サンプルのはんだ耐熱試
験繰返し回数に対する接続異常の累積発生率を示した。
FIG. 7 shows the cumulative incidence of connection abnormalities with respect to the number of repetitions of the solder heat resistance test for the test sample manufactured by implementing the present invention and the comparative sample manufactured by the conventional manufacturing method.

この試験結果は、内層銅箔厚20ミクロンに相当する試
験サンプルの結果であり、図中○印が従来例の結果であ
り、X印はこの発明を実施したサンプルの結果である。
This test result is the result of a test sample corresponding to an inner layer copper foil thickness of 20 microns, and in the figure, the ○ mark is the result of the conventional example, and the X mark is the result of the sample implementing the present invention.

第7図から分るように、この発明を実施して製造された
、孔内壁面の内層銅箔が厚さ方向に押し広げられて成る
多層配線基板の内層接続の信頼性は、従来のそれに比し
、かなり高いと云える。
As can be seen from FIG. 7, the reliability of the inner layer connections of the multilayer wiring board manufactured by implementing the present invention, in which the inner layer copper foil on the inner wall of the hole is expanded in the thickness direction, is lower than that of the conventional one. In comparison, it can be said that it is quite high.

以上、この発明を詳しく説明したが、この発明の効果と
して次の二点を挙げることができる。
Although this invention has been explained in detail above, the following two points can be mentioned as effects of this invention.

第一に、孔内壁面の内層銅箔が厚さ方向に広げられた形
状とすることにより内層接続面積が大幅に増大するため
、高い内層接続信頼性を有する多層配線基板を得ること
ができる。
First, by forming the inner layer copper foil on the inner wall surface of the hole in a shape that is expanded in the thickness direction, the inner layer connection area is greatly increased, so that a multilayer wiring board having high inner layer connection reliability can be obtained.

第二に、樹脂の融着による内層接続面積の減少分を一掃
できる程の内層接続面積の大幅な増大が望めるため、内
層銅箔上に融着した樹脂を除去するための余分な工程を
省略でき、製品コストの低減が可能となる。
Second, the inner layer connection area can be significantly increased to the extent that the decrease in the inner layer connection area due to resin fusion can be wiped out, so the extra step of removing the resin fused onto the inner layer copper foil can be omitted. This makes it possible to reduce product costs.

【図面の簡単な説明】 第1図は積層接着した多層配線基板にドリルで孔明けを
おこなった後の従来普通の基板断面を示す図、第2図は
その後、内層と外層の導通を図るべく孔内壁に銅めっき
をおこなった後の従来普通の基板断面を示す図、第3図
は第2図の円内に示した部分の拡大図、第4図は内層銅
箔と銅めっきとの接続面積が融着した樹脂の存在により
減少した状況を示す図、第5図はこの発明の実施により
内層銅箔の孔内壁に面する部分が内層の厚み方向に押し
広げられた状況を示す図、第6図はこの発明を実施した
場合の内層銅箔厚tと孔内壁面の最大銅箔厚tMAXと
の関係の一例を示す図、第7図はこの発明を実施して製
作した試験サンプルと従来の方法で製作した比較サンプ
ルのはんだ耐熱試験繰返し回数に対する接続異常の累積
発生率を示す図、第8図はこの発明の実施に使用する孔
明け作業用ドリルの形状を示す側面図である。 図において、1は多層配線基板、2は孔、3は内層銅箔
、4は絶縁基材、5は孔内壁銅めっき、6は融着した樹
脂、7は押し広げられた内層銅箔、Sはシャンク部分、
Fはフルート部分、Doはドリルの先端径、D1はシャ
ンク寄りのドリル径を示す。
[Brief explanation of the drawings] Fig. 1 shows a cross section of a conventional ordinary board after drilling holes in a laminated and bonded multilayer wiring board, and Fig. 2 shows a cross section of a conventional board after drilling holes in a laminated and bonded multilayer wiring board. A diagram showing a cross section of a conventional ordinary board after copper plating has been applied to the inner wall of the hole, Figure 3 is an enlarged view of the part shown in the circle in Figure 2, and Figure 4 is a connection between the inner layer copper foil and the copper plating. FIG. 5 is a diagram showing a situation in which the area has been reduced due to the presence of the fused resin; FIG. FIG. 6 is a diagram showing an example of the relationship between the inner layer copper foil thickness t and the maximum copper foil thickness tMAX of the inner wall surface of the hole when the present invention is implemented, and FIG. 7 is a diagram showing a test sample produced by implementing the present invention. FIG. 8 is a diagram showing the cumulative incidence of connection abnormality with respect to the number of repetitions of the solder heat resistance test of comparative samples manufactured by the conventional method. FIG. In the figure, 1 is a multilayer wiring board, 2 is a hole, 3 is an inner layer copper foil, 4 is an insulating base material, 5 is a hole inner wall copper plating, 6 is a fused resin, 7 is an inner layer copper foil that has been pushed out, S is the shank part,
F indicates the flute portion, Do indicates the diameter of the tip of the drill, and D1 indicates the diameter of the drill near the shank.

Claims (1)

【特許請求の範囲】[Claims] 1 孔内壁に面する内層金属箔が該内層の厚さ方向に広
げられた形状を有するようにし、孔内壁面のめっきと内
層金属箔との接続面積の増大を図ったことを特徴とする
多層配線基板。
1. A multilayer, characterized in that the inner layer metal foil facing the inner wall of the hole has a shape that is expanded in the thickness direction of the inner layer, thereby increasing the connection area between the plating on the inner wall surface of the hole and the inner layer metal foil. wiring board.
JP52100162A 1977-08-23 1977-08-23 multilayer wiring board Expired JPS5814758B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52100162A JPS5814758B2 (en) 1977-08-23 1977-08-23 multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52100162A JPS5814758B2 (en) 1977-08-23 1977-08-23 multilayer wiring board

Publications (2)

Publication Number Publication Date
JPS5434061A JPS5434061A (en) 1979-03-13
JPS5814758B2 true JPS5814758B2 (en) 1983-03-22

Family

ID=14266609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52100162A Expired JPS5814758B2 (en) 1977-08-23 1977-08-23 multilayer wiring board

Country Status (1)

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JP (1) JPS5814758B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5716682A (en) * 1980-07-03 1982-01-28 Kibun Kk Food preservative
JPH0619584Y2 (en) * 1989-01-13 1994-05-25 ナンカイ工業株式会社 Coupling between the heald frame and the opening device
SE500777C2 (en) * 1992-04-14 1994-08-29 Hydro Pharma Ab Antimicrobial composition with potentiated effect containing, inter alia, certain monoglycerides, process for their preparation and their use

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4838461A (en) * 1971-09-20 1973-06-06
JPS5354775A (en) * 1976-10-28 1978-05-18 Seiko Instr & Electronics Through hole processing method of circuit plate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4838461A (en) * 1971-09-20 1973-06-06
JPS5354775A (en) * 1976-10-28 1978-05-18 Seiko Instr & Electronics Through hole processing method of circuit plate

Also Published As

Publication number Publication date
JPS5434061A (en) 1979-03-13

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