JPS58147171A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58147171A JPS58147171A JP3013882A JP3013882A JPS58147171A JP S58147171 A JPS58147171 A JP S58147171A JP 3013882 A JP3013882 A JP 3013882A JP 3013882 A JP3013882 A JP 3013882A JP S58147171 A JPS58147171 A JP S58147171A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- semiconductor
- auge
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 239000000956 alloy Substances 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 1
- 238000000313 electron-beam-induced deposition Methods 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 238000002474 experimental method Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 241001459757 Juga Species 0.000 description 1
- 241000801954 Karana Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、ｎ型ＡβＧＬＬ／４ｚ −ＧａＡ＃のへテロ
接合を有する高電子移動度半導体装置、即ち、ＨＥＭＴ
（ＨすｈＥｌｅｃｔｒｏｎ ｊｆｓハｊｔｔｙ Ｔｒａ
ｎｓｉｓｔｏｒ ：詳細には雑誌［１！Ｌ子技術」第
２２巻第１２号第８５頁乃至第９０頁参照）と呼ばれる
半導体装置を製造する方法の改良に関する。Detailed Description of the Invention Technical Field of the Invention The present invention relates to a high electron mobility semiconductor device having an n-type AβGLL/4z-GaA# heterojunction, that is, a HEMT.
(HElectron jfshajtty Tra
nsistor: For details, see the magazine [1! This invention relates to an improvement in a method for manufacturing a semiconductor device, which is referred to as "L-Semiconductor Technology", Vol. 22, No. 12, pages 85 to 90).
従来技術と問題点
ＨＥＭＴＩｄ％型ＡｆｌＧａＡｚとノン・ドープＧａＡ
ｚとからなる少なくとも一つのへテロ接合を有し、外型
ＡＩＩＧａＡｚ電子供給層からノン・ドープＧａＡｚチ
ャネル層へ電子がトランスファされることに依って生成
される２次元電子層が電流路、即ち、チャネルの働きを
するものである。この２次元電子層に対しては出力電極
、即ち、ソース電極及びドレイン電極をオーミック接触
させなけれはならない。２次元電子層が生成される深さ
は、前記へテロ接合形成時のパラメータで決定され、こ
の２次元電子層とオーミック接触をとる為には、適当な
深さの合金層（アロイ層）を形成する必要がおる。とこ
ろが、この合金層を再現性良く２次元電子層とオーミッ
ク接触させることができず、不完全なものが多い。Conventional technology and problems HEMTId% type AflGaAz and non-doped GaA
A two-dimensional electron layer having at least one heterojunction consisting of It acts as a channel. The output electrodes, ie, the source electrode and the drain electrode, must be in ohmic contact with this two-dimensional electronic layer. The depth at which the two-dimensional electronic layer is generated is determined by the parameters during the formation of the heterojunction, and in order to make ohmic contact with this two-dimensional electronic layer, an alloy layer of an appropriate depth is formed. It is necessary to form. However, it is not possible to bring this alloy layer into ohmic contact with the two-dimensional electronic layer with good reproducibility, and there are many cases where the alloy layer is incomplete.
発明の目的
本発明は、ＲＥＮＴ構造の半導体装置に於ける２次元電
子層と良好にオーミック接触する電極を再現性良く得ら
れるようにするものである。OBJECTS OF THE INVENTION The present invention makes it possible to obtain with good reproducibility an electrode that makes good ohmic contact with a two-dimensional electronic layer in a semiconductor device having a RENT structure.
発明の実施例
第１図は本発明を成すにあたって行なった実験に使用し
たモデルを表わす要部断面図である。EMBODIMENT OF THE INVENTION FIG. 1 is a cross-sectional view of the main parts of a model used in experiments conducted to realize the present invention.
図に於いて、１は半絶縁性ＧａＡｚ基板、２はノン・ド
ープＧａＡｚ層、５はｎ＋型ＡＩＩＧａＡｚ層、４は？
型ＧａＡｚ層、５は例えばＡｍＧａ／Ｎｉ／Ａ＆Ｌから
なるオーミック電極、６は２次元電子層（電子蓄積層）
をそれぞれ示す。In the figure, 1 is a semi-insulating GaAz substrate, 2 is a non-doped GaAz layer, 5 is an n+ type AII GaAz layer, and 4 is a ?
type GaAz layer, 5 is an ohmic electrode made of, for example, AmGa/Ni/A&L, and 6 is a two-dimensional electron layer (electron storage layer).
are shown respectively.
このモデルに於けるオーミック電極５を形成するには、
真空蒸着法、電子ビーム蒸着法、スパッタ法など適宜の
技法を採用し、ＡｕＧｇ／Ｎｉ ／Ａｕ層或いはＡｍＧ
ａ／Ｎｉ層或いはＡｕＧｇ／Ａ６１層を形成してから所
定温度で所定時間の熱処理を行なう。これに依シ、電極
金属の一部はオーミック接触すべき半導体層中にしみ込
むような状態となって合金化し、オーリンク接触が形成
される。To form the ohmic electrode 5 in this model,
AuGg/Ni/Au layer or AmG
After forming the a/Ni layer or the AuGg/A61 layer, heat treatment is performed at a predetermined temperature for a predetermined time. As a result, a portion of the electrode metal penetrates into the semiconductor layer to which ohmic contact is to be made and is alloyed, forming an oh-link contact.
第２図乃至第４図は前記のようにして得たオーきツク接
触を検査する為、イオン・スパッタリングを併用したオ
ージェ電子分光法にてモデルの深さ方向に於ける組成を
分析した結果を表わし、縦軸にはオージェ信号ピーク高
さを、横軸にはスパッタ時間をそれぞれ採っである。Figures 2 to 4 show the results of analyzing the composition in the depth direction of the model using Auger electron spectroscopy combined with ion sputtering to inspect the oak contact obtained as described above. The vertical axis represents the Auger signal peak height, and the horizontal axis represents the sputtering time.
第２図はＡｕＧｍ／Ａｕからなる電極を厚さ４００ 〔
Ａ”Ｊ程度に形成した場合であって、電極金属の一部で
おるＡｈａはＡＩＧａＡｚ 層６の途中までしかしみ込
んでいないので２次元電子層６に到達しない。これは、
段階で零になっていることから判断される。従って、２
次元電子層６からＡＩＧａＡｚ層６を介して外部に信号
を取出す必要がある場合、オーミック接触が良好でない
ことに基因して特性を充分に引き出すことができない。Figure 2 shows an electrode made of AuGm/Au with a thickness of 400 [
In the case where the electrode metal is formed to about A''J, Aha, which is a part of the electrode metal, does not penetrate into the AIGaAz layer 6 halfway, so it does not reach the two-dimensional electronic layer 6.
This can be judged from the fact that it has become zero in stages. Therefore, 2
When it is necessary to take out a signal from the dimensional electronic layer 6 to the outside via the AIGaAz layer 6, the characteristics cannot be fully extracted due to poor ohmic contact.
第５ 図１ｄ 、４ｍＧｇ／Ａｍ カラナｂｔ＋１ヲ厚
す１５００（、；）程度に形成した場合であって、九は
ＡＡＧａＡｚ層３を越え、２次元電子層６に達している
ことが判る。5. FIG. 1d shows the case where 4 mGg/Am Karana bt+1 is formed to a thickness of about 1500 (,;), and it can be seen that 9 exceeds the AAGaAz layer 3 and reaches the two-dimensional electronic layer 6.
即ち１，４１に関するオージェ信号が一旦現われてから
零になシ、Ｇａ及びＡｘのオージェ信号が続いている部
分にまでＡｓｈのオージェ信号が現われているのはＡｕ
がノン・ドープＧａＡｚ層２に達していることを示して
いる。In other words, once the Auger signals related to 1 and 41 appear, they become zero, and the reason why the Auger signals of Ash appear even in the part where the Auger signals of Ga and Ax continue is because of Au.
It is shown that the amount reaches the non-doped GaAz layer 2.
第４図はＡ −Ｇ ａ／Ａ縣からなる電極を厚さ３００
０ ＋ｊ）８！度に形成した場合でおって、この場合は
更に充分に２次元電子層６へ達していると判断される。Figure 4 shows an electrode consisting of A-G a/A groups with a thickness of 300 mm.
0 + j) 8! In this case, it is judged that the two-dimensional electronic layer 6 has been sufficiently reached.
このような冥験を数多く行なった結果、電極金属の膜厚
を大にすれは半導体層中にしみ込む深さも大になり２次
元電子層６に電極金属が到達すること、そして、また、
半導体と電極金属との合金化層の厚さは電極金属膜の厚
さと略等しいか或いは若干薄い程度となることが判った
。従って、ＨＥＭＴ ｉ造の半導体装置に於いて、２次
元電子層６に対して良好なオーミック接触を得る為には
表面から２次元電子層６までの深さと同程度か或いは稍
厚く電極金属層を形成すると良い。湧常、２次元電子＃
６の−厚さ社極めて小であり（〜１００〔１〕）、従っ
て、表向から２次元電子層６までの深さは、第１図′か
らするとｎ” Ｉ！ ＡＩＧａＡｚ層３及びＣ型ＧａＡ
ｚ層４の厚さに略等しいと考えて良い。このようにする
ことに依シ、良好なオーミック接触を有する電極を備え
たＨＥＭＴ構造の半導体装置を再埃性良く製造すること
ができる。As a result of many such experiments, we found that as the film thickness of the electrode metal increases, the depth at which it penetrates into the semiconductor layer also increases, and the electrode metal reaches the two-dimensional electronic layer 6.
It has been found that the thickness of the alloyed layer of the semiconductor and the electrode metal is approximately equal to or slightly thinner than the thickness of the electrode metal film. Therefore, in order to obtain good ohmic contact with the two-dimensional electronic layer 6 in a HEMT i-based semiconductor device, the electrode metal layer must be as thick as or slightly thicker than the depth from the surface to the two-dimensional electronic layer 6. It is good to form. Naturally, two-dimensional electron #
6 is extremely small (~100[1]), and therefore the depth from the surface to the two-dimensional electronic layer 6 is n'' from FIG. GaA
It may be considered that the thickness is approximately equal to the thickness of the z layer 4. By doing so, it is possible to manufacture a semiconductor device with a HEMT structure having electrodes having good ohmic contact with good dust resistance.
ところで、オーミック電極５は、第１層としてＡｕＧｅ
を、第２層としてＡｕ或いはＮｉ或いはＮｉＡｕなどを
使用しているが・、２次元電子層６とのオーミック接触
は、オーミック電極５を構成する金属材料及び半導体か
らなる合金化層と２次元電子層６との界面、即ち、第５
図に矢印で示した部分に於けるドーピング材としてのＧ
−の存在に大きく依存している。従って、少なくとも矢
印の部分では第１層であるＪｕＧａのしみ込みが第２層
であるＡｂ ＋ Ｎｓ ＋ＮｉＡμなどのしみ込みよシ
外側にあることが好ましい。そのようにする為には第５
図に見られるように、オーミック電極５の第１層５Ｉに
対し、第２層５、のチャネル方向に於けるパターンを同
一にするか或いは若干内側に在るように形成すると良い
。By the way, the ohmic electrode 5 is made of AuGe as the first layer.
Although Au, Ni, NiAu, etc. are used as the second layer, the ohmic contact with the two-dimensional electronic layer 6 is due to the alloy layer made of metal materials and semiconductors constituting the ohmic electrode 5, and the two-dimensional electronic layer. The interface with layer 6, that is, the fifth
G as a doping material in the area indicated by the arrow in the figure
− is highly dependent on the existence of Therefore, at least in the area indicated by the arrow, it is preferable that the penetration of JuGa, which is the first layer, be on the outside of the penetration of Ab + Ns + NiAμ, etc., which is the second layer. In order to do so, the fifth step is
As shown in the figure, it is preferable to form the second layer 5 so that the pattern in the channel direction is the same as that of the first layer 5I of the ohmic electrode 5, or so that it is located slightly inside.
本発明では、オーミック電極の厚さに条件を与えてオー
ミック接触を改善するものでおるが、該オーミック電極
の合金化層とオーミック接触する２次元電子層の面濃度
ｎ＃を成る範囲にするとそのオーミック接触性は更に向
上させることができる。In the present invention, the ohmic contact is improved by giving conditions to the thickness of the ohmic electrode, and if the areal concentration n# of the two-dimensional electron layer that makes ohmic contact with the alloy layer of the ohmic electrode is set within the range. Ohmic contact can be further improved.
即チ、ＨＥＭＴに於いてはトランスコンダクタンス（＝
ｇ、）は高い値を示し、特に液体窒素温度ではＱｍは
着しく増大する。実際に測定されるｆｆ、（以下ム１と
する）との間には次式が成立する。In other words, in HEMT, transconductance (=
g,) shows a high value, and especially at liquid nitrogen temperature, Qm increases considerably. The following equation holds true between actually measured ff (hereinafter referred to as M1).
ＲＩ：ゲートにより変化しない抵抗
今、Ｉｎｇに対し、Ｒｚの影響を小さくするにはどの程
度の固有接触抵抗（＝ρ０）が必要かを見積ると、Ｒ，
・ｙ＊” ＜＜ １ （２１が満
足されるように、
ｐｚ ＜＜ ０．２ （３）
但し、Ｑｍｉ％ ＝ ５００ Ｃ＊Ｓ／ｙａ＋ｗ）とす
ると、
Ｒｐ ＋ Ｒｅ （コンタクト抵抗）
ｈＩ
Ｒｅ中□ （４）
Ｚ＝ ０．１ （−議〕＝１１極幅
Ｐ、＝１００（Ω／口〕 ： シート抵抗前記の関係か
ら
ｐ、 ＜４ ｘ １０−’ （Ω−ＯＮ” ）
（５１が得られる。従って、らに対するＲ
、の影響を小さくするには式（５）の関係が必要である
。しかしなカラ、ρ０と町の関係は第６図に見られる実
験結果の如く、強い依存性を鳴している。第６図が示す
ところから、ちとしては、
％＃ ＞ ９ ×１０” 〔ｃｍ−” 〕なる範囲が必
要であることが判る。この範囲の表面濃度を持つ２次元
電子層を備えたＨＥＭｒを作製すればオーミック接触抵
抗は更に低下するので高利得になる。RI: Resistance that does not change depending on the gate Now, if we estimate how much specific contact resistance (=ρ0) is required to reduce the influence of Rz on Ing, we get R,
・y*"<< 1 (so that 21 is satisfied, pz << 0.2 (3)
However, if Qmi% = 500 C*S/ya+w), then Rp + Re (contact resistance) hI Re medium (4) Z = 0.1 (-) = 11 pole width P, = 100 (Ω/mouth) ]: Sheet resistance From the above relationship, p, <4 x 10-'(Ω-ON")
(51 is obtained. Therefore, R for et al.
In order to reduce the influence of , the relationship shown in equation (5) is necessary. However, as shown in the experimental results shown in Figure 6, the relationship between ρ0 and town shows a strong dependence. From what FIG. 6 shows, it can be seen that a range of %#>9×10"[cm-"] is required. If a HEMr with a two-dimensional electron layer having a surface concentration in this range is manufactured, the ohmic contact resistance will be further reduced, resulting in a high gain.
発明の効果
本発明に依れは、ｎ型ＡＩＧａＡｚ電子供給層とノン・
ドープＧａＡｇチャネル層が隣接し、骸寛子供給層から
遷移された電子が該チャネル層表面に蓄積されて形成さ
れる２次元電子層を電流路とする半導体装置（ＨＥＭ
Ｔ ）を製造する場合に於いて、半導体表面にオーオッ
ク接触の電極を構成する金属層を前記半導体表面から前
記２次元電子層までの深さに略等しいか或いはそれ以上
の厚さに形成し、それを熱処理することに依り、前記電
極を構成する金属と半導体との合金化層を前記２次元電
子層に確実に到達させることができ、従って、高利得の
半導体装置を得ることが可能である。Effects of the Invention According to the present invention, an n-type AIGaAz electron supply layer and a non-
A semiconductor device (HEM) in which a two-dimensional electron layer is formed by adjacent doped GaAg channel layers and electrons transferred from the Mukuro Hiroki supply layer are accumulated on the surface of the channel layer as a current path.
T), a metal layer constituting an OOC contact electrode is formed on the semiconductor surface to a thickness that is approximately equal to or greater than the depth from the semiconductor surface to the two-dimensional electronic layer, By heat-treating it, it is possible to ensure that the alloy layer of metal and semiconductor constituting the electrode reaches the two-dimensional electron layer, and therefore it is possible to obtain a high-gain semiconductor device. .
第１図は本発明に成すにあって行なった実験に使用した
モデルの要部断面図、第２図乃至第４図はオージェ信号
ピーク高さ対スパッタ時間の関係を表わす線図、第５図
は他のモデルの要部断面図、第６図はｐｃ対〜の関係を
表わす線図である。
図に於いて、１は半絶縁性ＧａＡｚ基板、２はノン・ド
ープＧａＡｚ層、５はｎ＋型ＪＩＧａＡａ層、４は♂型
ＧｍＡｚ層、５はオーミック電極、６は２次元電子層で
ある。
特許出願人富士通株式会社
代理人 弁理士 玉蟲久五部
（外３名）
Ｍ１図
第５図
第２図
スバ・ンタ時間〔分］
第３ 図
スパッタ時間〔分〕
第４図
スパッタ時間 〔分〕
第６図Fig. 1 is a cross-sectional view of the main part of the model used in the experiments conducted to implement the present invention, Figs. 2 to 4 are diagrams showing the relationship between Auger signal peak height and sputtering time, and Fig. 5 is a cross-sectional view of a main part of another model, and FIG. 6 is a diagram showing the relationship between PC and ~. In the figure, 1 is a semi-insulating GaAz substrate, 2 is a non-doped GaAz layer, 5 is an n+ type JI GaAa layer, 4 is a male type GmAz layer, 5 is an ohmic electrode, and 6 is a two-dimensional electronic layer. Patent applicant Fujitsu Ltd. agent Patent attorney Gobe Tamamushi (3 others) M1 Figure 5 Figure 2 Subaru time [minutes] Figure 3 Sputter time [minutes] Figure 4 Sputter time [minutes] Figure 6
Claims (1)
チャネル層が隣接し、前記電子供給層から前記チャネル
層に遷移す、る電子で構成される２次元電子層を１１流
路とする高電子移動度半導体装置を製造する場合に於い
て、半導体表面にグオーミック電極を形成する為の金属
層を前記半導体表面から前記２次元電子層までの深さに
略醇しいか或いはそれ以上の厚さに形成し、しかる後、
それを熱処理して前記金属と半導体との合金層を前記２
次元電子層に到達させる工程が含まれてなることを特徴
とする半導体装置の製造方法。n-type AIGaAz and non-doped GaAz
When manufacturing a high electron mobility semiconductor device having 11 flow paths, a two-dimensional electron layer composed of adjacent channel layers and electrons transitioning from the electron supply layer to the channel layer, A metal layer for forming a guohmic electrode is formed at a depth from the semiconductor surface to the two-dimensional electronic layer to a thickness that is approximately the same or thicker, and then,
Heat treatment is performed to form an alloy layer of the metal and the semiconductor.
A method for manufacturing a semiconductor device, comprising a step of reaching a dimensional electron layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3013882A JPS58147171A (en) | 1982-02-26 | 1982-02-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3013882A JPS58147171A (en) | 1982-02-26 | 1982-02-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58147171A true JPS58147171A (en) | 1983-09-01 |
| JPH0325932B2 JPH0325932B2 (en) | 1991-04-09 |
Family
ID=12295402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3013882A Granted JPS58147171A (en) | 1982-02-26 | 1982-02-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147171A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62202563A (en) * | 1986-03-03 | 1987-09-07 | Agency Of Ind Science & Technol | Hetero-junction field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694780A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
| JPS58130575A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Manufacture of field effect transistor |
-
1982
- 1982-02-26 JP JP3013882A patent/JPS58147171A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694780A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
| JPS58130575A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Manufacture of field effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62202563A (en) * | 1986-03-03 | 1987-09-07 | Agency Of Ind Science & Technol | Hetero-junction field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0325932B2 (en) | 1991-04-09 |
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