JPS58147109A - Method of producing laminated ceramic condenser - Google Patents
Method of producing laminated ceramic condenserInfo
- Publication number
- JPS58147109A JPS58147109A JP3003282A JP3003282A JPS58147109A JP S58147109 A JPS58147109 A JP S58147109A JP 3003282 A JP3003282 A JP 3003282A JP 3003282 A JP3003282 A JP 3003282A JP S58147109 A JPS58147109 A JP S58147109A
- Authority
- JP
- Japan
- Prior art keywords
- slit
- capacitor
- chips
- chip
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は積Iv(ラミックコンデンサの製造方法の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an improvement in a method for manufacturing a product Iv (ramic capacitor).
(b) 技術の背累
高周波特性に優れ、小形大容量で信頼性か^い利点を有
する積層セラミックコンデンサは、一般に薄いセラミッ
ク生シート(グリーンシート)上に複数個の内部電極を
印刷し、このグリーンシートを向枚も積み重ねて一体化
させる積層法で積層セラミック生シートを作成すゐ、又
は厚いグリーンシート上に内部電極と篩篭体層(グリー
ンシートと同じセラミック粉末を用いている)を交互に
印刷する印刷法で積層セラミック生シートを作成し、こ
れをチップに切断してバーンアウト及び焼成したのち端
子電極を形成して完成逼れるチップ形のものと、該チッ
プ形コンデンサの端子電極にリード端子の一端を接続し
その他端が導出された外装を形成した外装形のものが4
bゐ。(b) Multilayer ceramic capacitors, which have excellent cumulative high-frequency characteristics, small size, large capacity, and reliability, are generally manufactured by printing multiple internal electrodes on a thin ceramic green sheet (green sheet). A laminated ceramic raw sheet is created using a lamination method in which green sheets are stacked together with the facing sheets, or internal electrodes and sieve casing layers (using the same ceramic powder as the green sheet) are alternately placed on a thick green sheet. A raw laminated ceramic sheet is created using a printing method, which is cut into chips, burnt out and fired, and then terminal electrodes are formed to complete the process. There are 4 types of exterior type that form an exterior where one end of the lead terminal is connected and the other end is led out.
b.
(c) 従来技術と問題点
従来、積層セラミックコンデンサの端子m極は上述した
如く、チップに切断しバーンアウト・焼成旭理したのち
対向する2つの端子電極形成面に導電性ペーストを塗付
して形成するため、多くのチップを所定向きに揃える吟
の工数を要するのみならず、端子電極形成面を検知する
ことを目的としたチップ形状にする等の不都合かあり、
その改豐が望すれていた・特に、取着されたり−ド熾子
を介して回路接続されゐ外殻形槓層セラtyクコンデン
ナは、端子電極が外装にて保−されリード端子の一端が
該電極に接続されてい為のKmわらず、はんだ付けで回
路接続されゐチップ形のそれと同等の端子電極が形成さ
れてい友という無駄もあった。(c) Conventional technology and problems Conventionally, as mentioned above, the terminal m pole of a multilayer ceramic capacitor is cut into chips, subjected to burnout and sintering, and then a conductive paste is applied to the two opposing terminal electrode formation surfaces. In order to form the chip in a specific manner, it not only takes a lot of man-hours to align a large number of chips in a predetermined direction, but there are also disadvantages such as making the chip shape for the purpose of detecting the surface on which the terminal electrode is formed.
Improvements have been desired.In particular, in the case of shell-type ceramic condensers that are attached or connected to circuits through lead wires, the terminal electrodes are protected by the exterior and one end of the lead terminal is Regardless of the Km connected to the electrode, a terminal electrode equivalent to that of a chip type was formed and the circuit was connected by soldering, which was a waste.
(祷 発明の目的
本発明は上記欠点を除去し、安価な積層セラミックコン
デンサをユーザに提供することであるC(・)発明の構
成
上記目的は、複数個の積層電極が内部に形成された積層
セラミック生シートは端子電極を形成すみ面に沿って少
なくと4M1l記棟j−電極を切断する深さの蘂1のス
リット及び端子電極を形成しな一面に沿って適宜深さの
第2のスリットを形成する工程、前記第1のスリットの
内壁にセラミック生シートの焼成と同時焼成が可能な導
電性ペーストを塗着す為工程、第1次バーンアウト工程
、前記第1及び第2のスリットより割断してチップに分
離する工程、第2次バーンアウト工程を含むことを特徴
とした積層セラミックコンデンサの製造方法により達成
される。(Purpose of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and provide a user with an inexpensive multilayer ceramic capacitor. The ceramic green sheet has a slit of at least 4M1L along the corner surface where the terminal electrode is formed, and a second slit of appropriate depth along the side where the terminal electrode is not formed. a step of applying a conductive paste that can be fired simultaneously with the firing of the raw ceramic sheet to the inner wall of the first slit, a first burnout step, and a step of forming a conductive paste on the inner wall of the first slit. This is achieved by a method for manufacturing a multilayer ceramic capacitor characterized by including a step of cutting and separating into chips and a second burnout step.
(f) 発明の実施例
以下、従来方法になゐ積層セラミックコンデンサの一般
的構造例を示す側面図でToコ第1図と、本発明方法に
係わる主要工程を示した第2図と、印刷法により積層内
部電極が形成された積層セラ建ツク生シートの側面図を
示す第3図と、本発明方法の一実施例に係わり前記セラ
ミック生シートに第1及び第2のスリットを形成した平
面図でああ第4図と、前記第1のスリットの断面形状を
示す第5図と、本発明方法の7実施例に係わり導電性ペ
ーストを塗付した前記第1のスリットの断面を示す第6
図と、前記第1及びwL2のスリットにれるペースト、
即ち例えば内部電極13及び14の形成に用いたペース
トと同等のものとし、スクリ、−ン印刷法又はマスクを
用いた吹付は法によりスリット12の内壁及び生シート
10の上面に骸ペーストが有害な広がりで塗着しないよ
うにした〇會か、使用した導電性ペーストはスリン)1
1の内−Kmれ込むようにするため粘度は内部電極用O
ものより低いもの、例え#i10.00〜2000ポア
ズのものが適当であり、かつ、若干量のフリットガラス
を混入すゑことにより端子電極形成面と0Ii1着力が
増大して好ましい。(f) Examples of the Invention Below, Figure 1 is a side view showing a general structural example of a multilayer ceramic capacitor produced using a conventional method, and Figure 2 is a side view showing the main steps involved in the method of the present invention. FIG. 3 shows a side view of a laminated ceramic raw sheet with laminated internal electrodes formed thereon by the method, and a plane view showing first and second slits formed in the ceramic raw sheet according to an embodiment of the method of the present invention. Figure 4 shows the cross-sectional shape of the first slit, and Figure 6 shows the cross-section of the first slit coated with conductive paste according to the seventh embodiment of the method of the present invention.
The figure and the paste inserted into the first and wL2 slits,
That is, for example, the paste should be the same as that used for forming the internal electrodes 13 and 14, and the screen printing method or spraying using a mask will prevent harmful paste from forming on the inner walls of the slits 12 and the upper surface of the raw sheet 10. The conductive paste used was Surin) 1.
The viscosity is O for the internal electrode in order to allow -Km of 1 to penetrate.
It is suitable to have #i of 10.00 to 2,000 poise, and it is preferable to mix a small amount of frit glass to increase the adhesion to the terminal electrode forming surface.
次いで、第2図に示す第4工程においてマイラーシート
9よ!llけ〈離した生シート1oFi、第1次0/’
−ンアウト即ち不完全なバーンアウト、例えば100℃
〜150℃まで8時間程度かけて緩やかKJ!甑し15
0℃で約2時間維持して半硬化させたのち、第5工程に
おいてスリット11及び12により割断し、第7図に示
す未焼成チップ16が得られり。Next, in the fourth step shown in FIG. 2, the Mylar sheet 9! llke〈Release raw sheet 1oFi, 1st 0/'
- incomplete burnout, e.g. 100°C
- Gentle KJ for about 8 hours up to 150℃! Koshikishi 15
After being semi-cured by maintaining it at 0° C. for about 2 hours, it is cut through slits 11 and 12 in a fifth step to obtain green chips 16 shown in FIG. 7.
さらに次いで、第2図のl1E6エ程及び第7エ程に示
す如(,180℃〜200’Ctで除々に昇温し適宜時
間だけ維持して十分なバーンアウトを施し −た
のち、生シート10の焼成温[1で加熱して第7図の積
層セラきフグコンデンサ16−即ち内部電極13及び1
4をチップ17の内部に形成し、チップ17の所定対向
端面に端子を極15′及び15 を形成してなるチップ
形積層セラミックコンデンサ16 が完成される。Further, as shown in steps 11E6 and 7 in FIG. The laminated ceramic blowfish capacitor 16 in FIG.
4 is formed inside the chip 17, and terminal poles 15' and 15 are formed on predetermined opposing end surfaces of the chip 17, thereby completing a chip-type multilayer ceramic capacitor 16.
なお、本発明方法になる端子電極15′及び15″の厚
さは従来方法にて形成された端子電極(第1図の3及び
4)に比べて、使用ペースト、中のガ −ラスフ
リット量(含まず又は微小)及び粘度(低い)の違いに
より極めて薄く形成されるため、ニッケル(Ni )め
っきを施してはんだ付は性を高めゐ或いは導電性接着剤
で回路接続させることが望ましい。Note that the thickness of the terminal electrodes 15' and 15'' formed by the method of the present invention is greater than that of the terminal electrodes (3 and 4 in Fig. 1) formed by the conventional method, depending on the paste used and the amount of glass frit ( Because it is formed extremely thin due to the difference in viscosity (low) and viscosity (low), it is desirable to plate it with nickel (Ni) to improve solderability, or to connect the circuit with a conductive adhesive.
第8図は第7図に示したチップ形コンデンサ16’の端
子電極15 及び15 にニッケル層18及び19を被
着し、そこKIJ−ド端子20又Fi21の一端をそれ
ぞれはんだ22にて接続して樹脂外髄23を形成した外
装形積層セラミックコンデンサ24を示す側断面図であ
り、外装22から導出され九リード端子20及び21の
他端はプリント板のスルーホールに嵌挿・けんだ付けさ
れ為等によつて回路接続されるようになる。In FIG. 8, nickel layers 18 and 19 are applied to the terminal electrodes 15 and 15 of the chip-type capacitor 16' shown in FIG. It is a side cross-sectional view showing an exterior type multilayer ceramic capacitor 24 with a resin outer core 23 formed thereon. The circuit will be connected due to various reasons.
(ロ)発明の詳細
な説明した如く、本発明方法になえ積層セラ電ツクコン
デンサは端子を極を形成するに際して、各チップに切断
すゐ前に導電性ペーストを塗着し、その焼成は該チップ
(セラミック)の焼成と同時に行會われるため、従来の
様に婦子電極形成を各個片て行なうことなく作成時間が
大幅に短縮できたのみならず、従来工程の様に自動化に
際して端子電極を形成す2Iii11面と形成しにい端
面とを識別すまための形状にする会費がないことにより
設計の自由度が^められた効果を有す石。(b) As described in detail, when using the method of the present invention to form a terminal into a multilayer ceramic electric capacitor, a conductive paste is applied before cutting into each chip, and the baking process is carried out. Since the process is carried out at the same time as the firing of the chip (ceramic), not only is it possible to significantly shorten the production time by eliminating the need to form the terminal electrodes on each individual piece as in the conventional process, but also it is possible to form the terminal electrodes during automation, unlike in the conventional process. A stone that has the effect of increasing the degree of freedom in design because there is no membership fee to create a shape that distinguishes the 2Iiii11 face that forms the 2Iiii11 face and the end face that does not form.
$111−は従来方法にX/lゐ積層セラ電ツクコンデ
ンサの一般的構造例を示す側面メ、第2図は本発明方法
に係わゐ積層セラミックコンデンサの土豪工程図、第3
図は印刷法の従来工程により作成され九積層セラミック
生シートの側面図、第4図は本発明方法の一実施例に係
わり前記セラミック生シートに第1及び第2のスリット
を形成した平面図、@5図は前記第1のスリットの形状
を示す拡大断面図、v、6図は本発明方法の一実施例に
係わり前記第1のスリットに導電性ペーストを塗着した
状態を示す拡大断面図、第7図は前記第1及びaR2の
スリットより割断したチップ(チップ形積層セラ建ツク
コンデンサ)を示す拡大側面図、第8図は前記チップを
焼成しリード端子を接続した外装形積層セラ建ツクコン
デンサを示す拡大側断面図であゐ〇
なお、図中において1.16はチップ形flt層セラミ
ックコンデンサ、2.17t′iコンデンサチツプ、3
.4.15 、15 は端子電極、6.7.13゜1
41i内部′WIL極、lOは積層セラミック生シート
、11Fi′f!A1のスリy)、12は第2のス1】
ット、15は導電性ペースト艙着層、16は未焼成のセ
ンデンサチップ、24Fi外俟形積層セラミックコンデ
ンナを示す〇
第1図 第2図
上
第3図
If”1$111- is a side view showing a general structure example of an X/L multilayer ceramic capacitor according to the conventional method, FIG.
The figure is a side view of a nine-layer ceramic green sheet produced by a conventional printing process, and FIG. 4 is a plan view of a ceramic green sheet with first and second slits formed according to an embodiment of the method of the present invention. @ Figure 5 is an enlarged cross-sectional view showing the shape of the first slit, and Figures V and 6 are enlarged cross-sectional views showing the state in which the conductive paste is applied to the first slit according to an embodiment of the method of the present invention. , FIG. 7 is an enlarged side view showing a chip (chip-type multilayer ceramic capacitor) cut through the first and aR2 slits, and FIG. 8 is an exterior-type multilayer ceramic structure in which the chip is fired and lead terminals are connected. This is an enlarged side cross-sectional view showing a capacitor. In the figure, 1.16 is a chip-type flt-layer ceramic capacitor, 2.17 is a capacitor chip, and 3 is a chip-type flt-layer ceramic capacitor.
.. 4.15, 15 are terminal electrodes, 6.7.13゜1
41i internal 'WIL pole, lO is laminated ceramic raw sheet, 11Fi'f! A1's pick y), 12 is the second pick 1]
15 is a conductive paste adhesion layer, 16 is an unfired sensor chip, and a 24Fi round-shaped multilayer ceramic capacitor is shown.
Claims (1)
生シートをチップに切断し該チップの所定対向端面に端
子電極を形成してなゐ積層セラミックコンデンサにおい
て、前記セラミック生シート は端子電極を形成する面
に沿って少なくとも前記積層電極を切断する深さの第1
のスリット及び端子電極を形成しない面に沿って適宜深
さの第2のスリットを形成する工程、前記第1のスリッ
トの内壁にセラミック生シートのIAA我と同時焼成が
可能な導電性ペーストを塗着する工程、第1次バーンア
ウト工程、前記第1及び第2のスリットより割断してチ
ップに分離する工程、第2次バーンアウト工程を含むこ
とを軽挙とした積層セラミックコンデンサの製造方法0In a multilayer ceramic capacitor, a laminated raw ceramic sheet having a plurality of laminated electrodes formed therein is cut into chips, and terminal electrodes are formed on predetermined opposing end faces of the chips, wherein the raw ceramic sheet is the terminal electrode. at least the first depth of cutting the laminated electrode along the plane forming the
forming a second slit of an appropriate depth along the surface where the slit and the terminal electrode are not formed; coating the inner wall of the first slit with a conductive paste that can be fired simultaneously with the raw ceramic sheet IAA; A manufacturing method for a multilayer ceramic capacitor 0 that does not mention the following steps: a step of attaching the capacitor, a first burnout step, a step of cutting through the first and second slits to separate the chips, and a second burnout step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3003282A JPS58147109A (en) | 1982-02-26 | 1982-02-26 | Method of producing laminated ceramic condenser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3003282A JPS58147109A (en) | 1982-02-26 | 1982-02-26 | Method of producing laminated ceramic condenser |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58147109A true JPS58147109A (en) | 1983-09-01 |
Family
ID=12292471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3003282A Pending JPS58147109A (en) | 1982-02-26 | 1982-02-26 | Method of producing laminated ceramic condenser |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58147109A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62106611A (en) * | 1985-11-05 | 1987-05-18 | 株式会社村田製作所 | Manufacture of cylindrical capacitor |
JP2003526903A (en) * | 1999-04-20 | 2003-09-09 | シーゲイト テクノロジー エルエルシー | Formation of electrode pattern for differential PZT activator |
-
1982
- 1982-02-26 JP JP3003282A patent/JPS58147109A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62106611A (en) * | 1985-11-05 | 1987-05-18 | 株式会社村田製作所 | Manufacture of cylindrical capacitor |
JPH0528484B2 (en) * | 1985-11-05 | 1993-04-26 | Murata Manufacturing Co | |
JP2003526903A (en) * | 1999-04-20 | 2003-09-09 | シーゲイト テクノロジー エルエルシー | Formation of electrode pattern for differential PZT activator |
JP4713742B2 (en) * | 1999-04-20 | 2011-06-29 | シーゲイト テクノロジー エルエルシー | Method for forming electrode pattern of differential PZT actuator |
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