JPS58147066A - Gate turn off thyristor - Google Patents
Gate turn off thyristorInfo
- Publication number
- JPS58147066A JPS58147066A JP3077482A JP3077482A JPS58147066A JP S58147066 A JPS58147066 A JP S58147066A JP 3077482 A JP3077482 A JP 3077482A JP 3077482 A JP3077482 A JP 3077482A JP S58147066 A JPS58147066 A JP S58147066A
- Authority
- JP
- Japan
- Prior art keywords
- gto
- layer
- type
- auxiliary
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 101100449816 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GTO1 gene Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
この！Ｊ！明唸補助サイリスタを内蔵するゲート・ター
ンオフサ４リスクに関するものである。[Detailed description of the invention] This! J! This relates to a gate turn-off switch with a built-in auxiliary thyristor.
一般に、大電流をしや１するのに適したＰ】Ｐｎ４層構
造から表る電力用のゲート・ターンオフサ４リスク（以
下単にＧＴＯと言う）は麺１図に示すように、−島状エ
ミッタ（１つ１つの風ミッタをセグメントと宣う）をゲ
ート電極がと多凹む構造面図である。同図において、（
１１１１ａ形ペース層１（２１はＰ形ベース層、（３）
はＰ形エミッタ層、（４）は多島状に形成したｎ形エミ
ッタ層、（５）は前記Ｐ形エミッタ層（３１にオーミッ
ク接触する陽電極、（６１＃ｉ前記ｌ形エミッタ層（４
）にオーミック接触する陰電極、（７）は前記Ｐ形ベー
ス層（２１にオーミック接触するゲート電極である。In general, the power gate turn-off switch (hereinafter simply referred to as GTO) that appears from the P]Pn four-layer structure, which is suitable for suppressing large currents, has an island-like emitter ( FIG. 2 is a structural plan view in which each wind transmitter (hereinafter referred to as a segment) is recessed into a gate electrode. In the same figure, (
1111a type pace layer 1 (21 is P type base layer, (3)
is a P-type emitter layer, (4) is an n-type emitter layer formed in the form of an archipelago, (5) is a positive electrode in ohmic contact with the P-type emitter layer (31), (61#i is the L-type emitter layer (4)
) is a cathode in ohmic contact with the P-type base layer (21), and (7) is a gate electrode in ohmic contact with the P-type base layer (21).
次に、上記構成によるＧ’ｆ’Ｏではターンオンし九Ｇ
ＴＯをターンオフさせるにはゲート電極（７）と陰電極
（６１間を逆バイアスすることによって、電流をひき抜
く。このため、大電流のしゃ断には細長い島状のＵ形エ
ミッタ層（４）を多数個形成すると共に、この１形工ミ
゛ツタ層（４）直下のＰ形ベース層（２１の横方向抵抗
Ｒ（第１図参ｊｌ）を減少させる必要がある。Next, in G'f'O with the above configuration, turn on and 9G
To turn off the TO, current is drawn out by applying a reverse bias between the gate electrode (7) and the cathode (61).For this reason, a long and narrow island-shaped U-shaped emitter layer (4) is used to cut off the large current. In addition to forming a large number of them, it is necessary to reduce the lateral resistance R (jl in FIG. 1) of the P-type base layer (21) directly below the first-former Ivy layer (4).
しかしｋから、この構造によるＧＴＯはｎ形エミッタ層
（４）、Ｐ形ベース層（２１および態形ベース層（１）
で構成されるトランジスタ部の電流増幅率の低下により
、各セグメントのゲート・トリガ電流Ｉｔｔが増大する
。しかも、一般のサイリスタに比べてゲート対こうエミ
ッタ局長がはるかに長くなるため、ＧＴＯ全体のゲート
・トリガ電流Ｉｆｔは１〜２ムと非常に大きなものとな
る。また、とのＧＴＯを完全にひろげターンオンさせる
ために社ゲート・トリガ電流Ｘｔｔの１０倍以上のハイ
・ゲート・ドライブが必要と力るので、０丁００オンゲ
ート電流としてＩＯＡ以上のものが必要となる。このオ
ンゲートは１，０００ム、２．０００ムのしゃ断が要求
辿れるＧＴＯにおいては更に太きく−ｅ６、ターンオン
損失が大きくなるうえ、ターンゲート回路も大きく危シ
、特に高周波動作において大きな欠点となる。However, from k, the GTO with this structure consists of an n-type emitter layer (4), a P-type base layer (21) and a morphology base layer (1).
The gate trigger current Itt of each segment increases due to a decrease in the current amplification factor of the transistor section constituted by . Moreover, since the gate-to-emitter length is much longer than that of a general thyristor, the gate trigger current Ift of the entire GTO becomes very large, 1 to 2 μm. Also, in order to completely expand and turn on the GTO, a high gate drive of more than 10 times the gate trigger current Xtt is required, so an on-gate current of more than IOA is required. . This on-gate is even thicker in the GTO-e6, which requires a cut-off of 1,000 μm or 2,000 μm, resulting in a large turn-on loss and a large and dangerous turn gate circuit, which is a major drawback especially in high-frequency operation.
そこで、従来、前記の欠点を除くものとして、補助ＧＴ
ＯをＶ３ｍ！したＧＴＯか提案されている。Therefore, conventionally, in order to eliminate the above-mentioned drawbacks, auxiliary GT
O to V3m! A new GTO has been proposed.
すなわち、第２図は従来の補助ＧＴＯを内蔵したＧＴＯ
を示す断面図である。同図において、（８）は主Ｇ’ｌ
’Ｏ，（９）は補助Ｇ’ｒＯ，Ｑｌは前記主Ｇ Ｔ ０
（８）のｌ形ベース層（１１と共有する補助Ｇ’ｆ’０
（９）の態形ベース層、ａｌ）は前記１０丁０（８）の
Ｐ形ペース層（２１と共有する補助ＧＴＯ（９）ＯＰ
形ヘー ス層、ａ３ｔ［ｒｌｌ＝ ｃｔｏ（ａ＋Ｏｐ形
エミッタ層（３）と共有する補助Ｇ Ｔ ０（９）のＰ
形エミッタ層、αｊは補助Ｇ Ｔ ０（９）の態形エミ
ッタ層、α憂はこのｎ形エミッタ層ａ３にオーミック接
触し、主ＧＴＯ（８１のゲート電極（７）に接触する陰
電極、（Ｉｓは補助Ｇ Ｔ ０（９）のゲート電極、翰
は前記主ＧＴσ８）の陽電極（５）に接続する補助Ｇ
Ｔ ０（９）の陽電極である。In other words, Figure 2 shows a conventional GTO with a built-in auxiliary GTO.
FIG. In the same figure, (8) is the main G'l
'O, (9) is the auxiliary G'rO, Ql is the main G T 0
(8) l-shaped base layer (auxiliary G'f'0 shared with 11)
The form base layer (al) of (9) is the auxiliary GTO (9) OP shared with the P-type space layer (21) of the 10-0 (8).
type Heath layer, a3t[rll=cto(a+P of auxiliary G T 0 (9) shared with Op type emitter layer (3)
The type emitter layer, αj, is the type emitter layer of the auxiliary GT 0 (9), α is in ohmic contact with this n-type emitter layer a3, and the negative electrode, ( Is is the gate electrode of the auxiliary GT 0 (9), and the wire is the auxiliary G connected to the positive electrode (5) of the main GT σ8).
It is the positive electrode of T 0 (9).
この構造によるＧｉＯは前記の欠点を除去することがで
きるが、しかし％Ｐ形ベース層（２）が主ＧＴＯ（８）
と補助Ｇ Ｔ ０（９）で連結されておシ、さらに、補
助Ｇ Ｔ ０（９）の陰電極ａ−が主Ｇテ０（８）のゲ
ート電極（７）に短絡している丸め、補助Ｇ Ｔ ０（
９）のゲート・陰電極に十分な逆バイアスがかからなく
なシ、補助Ｇ Ｔ ０（９）のターンオフ能力が低下す
る欠点があった。GiO with this structure can eliminate the above-mentioned drawbacks, but the %P type base layer (2) is the main GTO (8).
and an auxiliary G T 0 (9) connected to the auxiliary G T 0 (9), and further, a rounded shape in which the negative electrode a- of the auxiliary G T 0 (9) is short-circuited to the gate electrode (7) of the main G T 0 (8); Auxiliary G T 0 (
There is a drawback that the turn-off ability of the auxiliary G T 0 (9) is deteriorated because a sufficient reverse bias is not applied to the gate/cathode of (9).
したがって、この発明の目的は補助ＧＴＯのゲート・陰
電極を十分に逆パイーアスすることができ、補助Ｇテ０
のターンオン能力を向上することができるＧＴＯを提供
するものである。Therefore, an object of the present invention is to sufficiently reverse bias the gate and cathode of the auxiliary GTO.
The purpose of the present invention is to provide a GTO that can improve the turn-on ability of the vehicle.
このような目的を達成するため、この発明は主ＧＴＯと
補助ＧＴＯの間で、Ｐ形ベース層に形成した分離態形領
域と、主Ｇ’ＴＯのゲート電極と補助ＧＴＯＯ陰電極鵞
接続する！ｌＷ！を電極と、前記分離ｎ形領賊とこの接
続電極との間に形成し九絶縁暎とを設Ｈたものであシ、
以下実施例を用いて詳細に説明する。To achieve this purpose, the present invention connects the main GTO and the auxiliary GTO with a separate region formed in the P-type base layer, and the gate electrode of the main G'TO and the negative electrode of the auxiliary GTOO! lW! and nine insulating holes formed between the separated n-type conductor and the connecting electrode,
This will be explained in detail below using examples.
第３図はこの発明に係るＧＴＯの一実施例を示す断面図
である。同図において、ａηは主ＧＴＯ（泪と補 ６助
Ｇ Ｔ ０（９）との間に形成し九分離領域、篩は前記
Ｐ形ペース層にリン等の不純物によって形成した分離繭
形領域、ａｌは１０丁０（８）のゲート電極（７）と補
助Ｇ Ｔ ０（９）の陰電極α４とを接続する接続電極
、（至）はこの分離ｎ形領域錦と接続電極ａｌとの間に
形成した８１０２などの絶縁膜、（２１）Ｕ前記分離ａ
形領域錦の深さと幅によって決定されゐ抵抗値ＲＤの分
離抵抗である。FIG. 3 is a sectional view showing an embodiment of the GTO according to the present invention. In the same figure, aη is a separated region formed between the main GTO (Year and auxiliary GTO (9)), and a sieve is a separated cocoon-shaped region formed in the P-type paste layer with impurities such as phosphorus; al is a connection electrode that connects the gate electrode (7) of 10-0 (8) and the negative electrode α4 of auxiliary G T 0 (9), and (to) is between this separated n-type region brocade and the connection electrode al (21)U said separation a
It is a separation resistor with a resistance value RD determined by the depth and width of the shape area.
この構造によるＧＴＯでは分離抵抗（２１）の大きさが
、補助ｃ Ｔ ０（９）のゲート逆バイアスの大きさを
決定するので、この分離抵抗（２１）Ｄ大きさを適性値
、例えば数１０００に設定することにより、補助ＧＴＯ
（９）のゲート・陰電極に十分な逆バイアスをかけるこ
とができる。このため、補助ＧＴＯ（９１がターンオン
したのち、主Ｇ Ｔ ０（８１をターンオンさせること
ができる。In the GTO with this structure, the magnitude of the isolation resistor (21) determines the magnitude of the gate reverse bias of the auxiliary c By setting the auxiliary GTO
(9) A sufficient reverse bias can be applied to the gate/cathode. Therefore, after the auxiliary GTO (91) is turned on, the main GTO (81) can be turned on.
以上詳細に説明したように、この発明に係るゲート・タ
ーンオフ能力リ２り、によれば補助ＧＴＯのゲート・陰
極間に十分な逆バイアスをかけることができる丸め、こ
の補助ＧＴＯのターンオフ能力が向上し、オン損失の少
をいＧＴＯを構成することができる効果がある。As explained in detail above, according to the gate turn-off ability improvement according to the present invention, it is possible to apply a sufficient reverse bias between the gate and cathode of the auxiliary GTO, and the turn-off ability of this auxiliary GTO is improved. However, it is possible to construct a GTO with less on-loss.
第１図は従来のゲート・ターンオフサイリスタを示す断
面図、第２図社従来の補助ゲート・タンオフサイリスタ
を内置したゲート・ターンオフサイリスタを示す断面図
、第３図はこの発明に係るゲート・ターンオフサイリス
タの一実施例を示す断面図である。
（１１−・・・１形ベ一ス層、（２１・・・−Ｐ形ペー
ス層、（３１・・・・Ｐ形エミッタ層、（４）・・−・
ｎ形エミッタ層、（５）・・−・陽電極、（６）・・・
・陰電極、（７）・・・・ゲート電極、（８）・・・・
主ＧＴＯ１（９）・・・・補助Ｇ’ｒＯ％（ＩＩ・・・
ｅｎ形ペース層、ａｌ）・・・・Ｐ形ベース層、α２・
・魯・Ｐ形エミッタ層、０・・・ｅＩＩ形エミッタ層、
α尋・・・−陰電極、αり・・・・ゲート電極、（ｌｅ
・′・・・陽電極、ａη・・・・分離領域、篩・・・・
分離ｎ影領域、ａｌ・・・１接続電極、翰・・・・絶縁
膜、（２１）・・・・分離抵抗。
代理人 葛 野 信 −（外１名）Fig. 1 is a sectional view showing a conventional gate turn-off thyristor, Fig. 2 is a sectional view showing a gate turn-off thyristor with a conventional auxiliary gate turn-off thyristor installed therein, and Fig. 3 is a sectional view showing a gate turn-off thyristor according to the present invention. FIG. 2 is a sectional view showing an example of a thyristor. (11-...1 type base layer, (21...-P type paste layer, (31...P type emitter layer, (4)...
N-type emitter layer, (5)... positive electrode, (6)...
・Cathode electrode, (7)...Gate electrode, (8)...
Main GTO1 (9)... Auxiliary G'rO% (II...
en-type pace layer, al)...P-type base layer, α2.
・P-type emitter layer, 0... eII-type emitter layer,
α fathom...-cathode, αri...gate electrode, (le
・′・・・Positive electrode, aη...Separation area, sieve...
Separation n shadow area, al...1 connection electrode, wire...insulating film, (21)...separation resistor. Agent Shin Kuzuno - (1 other person)
Claims (1)
形工ンツタ層、このｎ形エミッタ層にオーミック接触す
る陰電極、前記Ｐ形成−ス層にオーミック接触すネゲー
ト電極、前記Ｐ形エミッタ層にオーミック接触する陽電
極から構成するＴ’ｎｐｎ４層構造の主ゲート・ターン
オフサイリスタと、この主ゲート・ターンオフサイリス
タのＰ形エミッタ層、ｎ形ベーメ層およびＰ形ベース層
を共有し、このＰ形ベース層上に形成したｎ形エミッタ
層、このｌ形エミッタ層に１−ミック接触すると共に主
ゲート・ターンオフサイリスタのゲート電極とＩｌ絞す
る陰電極、前記共有のＰ形ベース層上にオーミック接触
するゲート電極から構成するＰｎＰｎ４層構造の、補助
ゲート・ターンオフサイリスタとを儒えたゲート・ター
ンオフサ４リスクにおいて、前記主ゲート・ターンオフ
サイリスタと補助ゲート・ターンオフサイリスタの間で
、前記Ｐ形ベース層に形成した分離ｎ形領琥と、主ゲー
ト・ターンオフサ４リスクのゲート電極と補助ゲートの
ターンオフサイリスタの陰電極をＩＩ綬する＊＊電極と
、前記分離ｎ影領域ととの接続電極との間に形成しえ絶
縁膜とを設ヒたことを特徴とするゲート・ターンオフサ
イリスタ。 □a P-type emitter layer, an n-type space layer, a P-type base layer and a one-type conductor layer, a cathode in ohmic contact with the n-type emitter layer, a negating electrode in ohmic contact with the P-type space layer, and the P-type emitter. A main gate/turn-off thyristor with a T'npn four-layer structure consisting of a positive electrode in ohmic contact with the main gate/turn-off thyristor, and a P-type emitter layer, an n-type Boehme layer, and a P-type base layer of this main gate/turn-off thyristor are shared. an n-type emitter layer formed on the shared p-type base layer; a negative electrode in 1-mic contact with the l-type emitter layer and in contact with the gate electrode of the main gate turn-off thyristor; and an ohmic contact on the shared p-type base layer. In the gate turn-off switch 4 having an auxiliary gate turn-off thyristor and having a PnPn four-layer structure consisting of a gate electrode of formed between the separated n-type connecting electrode, the gate electrode of the main gate turn-off sensor 4 risk, the cathode electrode of the turn-off thyristor of the auxiliary gate, and the connecting electrode with the separated n-type shadow region. A gate turn-off thyristor characterized by having a thin insulating film. □
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3077482A JPS58147066A (en) | 1982-02-25 | 1982-02-25 | Gate turn off thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3077482A JPS58147066A (en) | 1982-02-25 | 1982-02-25 | Gate turn off thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58147066A true JPS58147066A (en) | 1983-09-01 |
Family
ID=12313026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3077482A Pending JPS58147066A (en) | 1982-02-25 | 1982-02-25 | Gate turn off thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147066A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62204353U (en) * | 1986-06-18 | 1987-12-26 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50102275A (en) * | 1974-01-07 | 1975-08-13 | ||
| JPS51116683A (en) * | 1975-04-04 | 1976-10-14 | Mitsubishi Electric Corp | Semiconductor control unit |
| JPS54163686A (en) * | 1978-06-15 | 1979-12-26 | Nippon Electric Co | Semiconductor device |
-
1982
- 1982-02-25 JP JP3077482A patent/JPS58147066A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50102275A (en) * | 1974-01-07 | 1975-08-13 | ||
| JPS51116683A (en) * | 1975-04-04 | 1976-10-14 | Mitsubishi Electric Corp | Semiconductor control unit |
| JPS54163686A (en) * | 1978-06-15 | 1979-12-26 | Nippon Electric Co | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62204353U (en) * | 1986-06-18 | 1987-12-26 | ||
| JPH0528781Y2 (en) * | 1986-06-18 | 1993-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6043032B2 (en) | gate turn off thyristor | |
| US4092703A (en) | Gate controlled semiconductor device | |
| JPS6019147B2 (en) | gate turn off thyristor | |
| JPH0691244B2 (en) | Gate turn-off thyristor manufacturing method | |
| JPS6353702B2 (en) | ||
| JPH0138381B2 (en) | ||
| JPS58147066A (en) | Gate turn off thyristor | |
| JPS5938056Y2 (en) | semiconductor switchgear | |
| JPH01253274A (en) | Reverse conduction gto thyristor | |
| JPS58194366A (en) | Semiconductor control rectifier | |
| JPH0682832B2 (en) | Semiconductor switching device | |
| JPH0691246B2 (en) | Semiconductor device | |
| JPS61182259A (en) | Gate turn-off thyristor | |
| JPH0448024Y2 (en) | ||
| JPS587068B2 (en) | thyristor | |
| JPS583388B2 (en) | Hand tie souchi | |
| JPH0117266B2 (en) | ||
| JPS58206159A (en) | Gate turn-off thyristor | |
| JPS6146983B2 (en) | ||
| JPS6348135Y2 (en) | ||
| JPS55108765A (en) | Semiconductor device | |
| JPS60957B2 (en) | Manufacturing method for semiconductor devices | |
| JPH01111375A (en) | Gate turn-off thyristor | |
| JPH0752777B2 (en) | Fast diode | |
| JPS60170934A (en) | Manufacture of semiconductor device |